WAFER ACCEPTANCE TESTING METHOD AND STRUCTURE OF A TEST KEY USED IN THE METHOD
A wafer acceptance testing (WAT) method for monitoring GC-DT misalignment and a test key structure are disclosed. The test key includes a deep trench capacitor structure biased to a first voltage (VDT). The deep trench capacitor structure is formed in a substrate, on which active areas are defined. The deep trench capacitor structure includes a buried strap out diffusion region that is formed within the active area and is electrically connected to the deep trench capacitor structure. The deep trench capacitor structure is isolated by shallow trench isolation (STI). A GC-T electrode layout and a GC-B electrode layout are formed over the substrate. The GC-T electrode layout, which is biased to a second voltage (VGC-T), includes a plurality of columns of GC-T fingers. The GC-B electrode layout, which is biased to a third voltage (VGC-B), includes a plurality of columns of GC-B fingers that interdigitate the plurality of columns of GC-T fingers over the active areas and STI. A first capacitance C1 of a first capacitor contributed by the plurality of columns of GC-T fingers and the buried strap out diffusion region is measured. A second capacitance C2 of a second capacitor contributed by the plurality of columns of GC-B fingers and the buried strap out diffusion region is measured. The first capacitance C1 and second capacitance C2 are compared, wherein when C1≠C2, GC-DT is misaligned.
1. Field of the Invention
The present invention relates to a wafer acceptance testing (WAT) method, and more particularly, to a WAT method for monitoring gate conductor-deep trench (GC-DT) misalignment and a test key structure used in this method.
2. Description of the Prior Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) should be continuously tested in every step so as to maintain device quality. Usually, a testing circuit is simultaneously fabricated with an actual device so that quality of the actual device can be judged by a performance of the testing circuit. The quality of the actual device therefore can be well controlled. Typically, such testing circuit, which is also referred to as “test key”, is disposed on peripheral area of each chip or die.
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It is the primary object of the present invention to provide a novel wafer acceptance testing (WAT) method for accurately monitoring GC-DT misalignment.
Another object of the present invention is to provide a novel WAT method and structure of a test key used in this WAT method.
According to the claimed invention, a wafer acceptance testing (WAT) method for monitoring gate conductor-deep trench (GC-DT) misalignment is provided. A test key structure comprising a deep trench capacitor structure biased to a first voltage (VDT) embedded in a substrate is provided. At least one active area is defined on the substrate. The deep trench capacitor structure is electrically connected to an out diffusion in the active area and is isolated by shallow trench isolation (STI). The deep trench capacitor structure comprises interdigitated GC-T electrode layout and GC-B electrode layout. The GC-T electrode layout is biased to a second voltage (VGC-T), and the GC-B electrode layout is biased to a third voltage (VGC-B). The GC-T electrode layout comprises a plurality of first GC fingers, and the GC-B electrode layout comprises a plurality of second GC fingers. The capacitance of a first capacitor C1 is measured. The GC-T electrode layout serves as a first electrode of the first capacitor C1. The out diffusion serves as a second electrode of the first capacitor C1. The capacitance of a second capacitor C2 is also measured. The GC-B electrode layout serves as a first electrode of the second capacitor C2. The out diffusion serves as a second electrode of the second capacitor C2. The capacitance of the first capacitor C1 with the capacitance of the second capacitor C2 are compared, wherein if C1≠C2, GC-DT misalignment occurs.
Other objects, advantages and novel features of the invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
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The cross sections of the plurality of elongated finger deep trench portions 22, 24, 26, and 28 are illustrated in
Phase 1: deep trench etching.
Phase 2: buried plate and capacitor dielectric (or node dielectric) forming.
Phase 3: first polysilicon deep trench fill and first recess etching.
Phase 4: collar oxide forming.
Phase 5: second polysilicon deposition and second recess etching.
Phase 6: third polysilicon deposition and third recess etching.
Phase 7: shallow trench isolation (STI) forming.
According to the preferred embodiment, the storage node 113 consists of three layers of polysilicon: Poly-1, Poly-2 and Poly-3. Poly-1 is electrically insulated from the buried plate 111 by the capacitor dielectric 112. Poly-2 is electrically insulated from the substrate 10 by the oxide collar 114. Poly-3, which is also referred to as “buried strap poly”, is in contact with the substrate 10. Typically, Poly-3 is non-doped polysilicon. In a later thermal stage, dopants in the heavily doped Poly-2 will diffuse to the substrate 10 in contact with the Poly-3.
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The novel wafer acceptance testing method for monitoring GC-DT misalignment during the fabrication of trench capacitor DRAM devices according to this invention is demonstrated through
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Those skilled in the art will readily observe that numerous modification and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A wafer acceptance testing (WAT) method for monitoring gate conductor-deep trench (GC-DT) misalignment, comprising the steps of:
- providing a test key structure comprising a deep trench capacitor structure biased to a first voltage (VDT) embedded in a substrate, an active area being defined on the substrate, wherein the deep trench capacitor structure is electrically connected to an out diffusion in the active area and is isolated by shallow trench isolation (STI), and the deep trench capacitor structure comprises an interdigitated GC-T electrode layout and a GC-B electrode layout, wherein the GC-T electrode layout is biased to a second voltage (VGC-T), and the GC-B electrode layout is biased to a third voltage (VGC-B), and wherein the GC-T electrode layout comprises a plurality of first GC fingers, the GOB electrode layout comprises a plurality of second OC fingers;
- measuring a capacitance of a first capacitor C1, wherein the GC-T electrode layout serves as a first electrode of the first capacitor C1 and the out diffusion serves as a second electrode of the first capacitor C1;
- measuring a capacitance of a second capacitor C2, wherein the GC-B electrode layout serves as a first electrode of the second capacitor C2 and the out diffusion serves as a second electrode of the second capacitor C2; and
- comparing the capacitance of the first capacitor C1 with the capacitance of the second capacitor C2, wherein if C1≠C2, GC-DT misalignment occurs.
2. The WAT method according to claim 1 wherein the second voltage (VGC-T) equals to the third voltage (VGC-B).
3. The WAT method according to claim 1 wherein the deep trench capacitor structure further comprises a buried plate disposed in the substrate adjacent to a lower portion of the deep trench capacitor structure, a storage node, and a capacitor dielectric disposed between the storage node and the buried plate, wherein the storage node is electrically connected to the out diffusion.
4. The WAT method according to claim 1 wherein the GC-T electrode layout comprises a first bridge portion for electrically connecting the plurality of first GC fingers with a first contact portion.
5. The WAT method according to claim 1 wherein the GC-B electrode layout comprises a second bridge portion for electrically connecting the plurality of second GC fingers with a second contact portion.
6. A test key structure for monitoring gate conductor-deep trench (GC-DT) misalignment, comprising:
- a deep trench capacitor structure biased to a first voltage (VDT), wherein the deep trench capacitor structure is embedded in a substrate and comprises an out diffusion formed in an active area of the substrate, and wherein the deep trench capacitor structure is isolated by shallow trench isolation (STI);
- an insulation layer formed on the active area;
- a GC-T electrode layout biased to a second voltage (VGC-T), the GC-T electrode layout comprising a plurality of first GC fingers; and
- a GC-B electrode layout biased to a third voltage (VGC-B), the GC-B electrode layout comprising a plurality of second GC fingers, wherein the first GC fingers and the out diffusion constitute a first capacitor C1, and the second GC fingers and the out diffusion constitute a second capacitor C2, and wherein the first GC fingers and the second GC fingers are interdigitated.
7. The test key structure according to claim 6 wherein there is no source/drain ion doped region implanted into the substrate between two adjacent GC fingers.
8. The test key structure according to claim 6 wherein the GC-T electrode layout comprises a first bridge portion for electrically connecting the plurality of first GC fingers with a first contact portion.
9. The test key structure according to claim 6 wherein the GC-B electrode layout comprises a second bridge portion for electrically connecting the plurality of second GC fingers with a second contact portion.
Type: Application
Filed: Dec 10, 2003
Publication Date: Jun 16, 2005
Inventor: Ping Hsu (Taipei Hsien)
Application Number: 10/707,398