Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a channel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the channel structure. The channel structure is separated from the first word line by a gate dielectric layer.

Abstract: The present application provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate having an active region; a recess gate structure disposed in the substrate and intersecting the active region; a bit line contact including a polysilicon stack and disposed on the substrate; a conductive pillar disposed over the substrate and electrically connected to the active region; a landing pad disposed on the conductive pillar and electrically connected to the conductive pillar; and a stack of dielectric layers disposed over the substrate and laterally surrounding the bit line contact. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The second polysilicon layer is in direct contact with the stack of dielectric layers.

Abstract: The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a bottom contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; a liner layer positioned between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of partition layers; and a top contact layer positioned on the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

Abstract: The present application provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate having an active region; a recess gate structure disposed in the substrate and intersecting the active region; a bit line contact including a polysilicon stack and disposed on the substrate; a conductive pillar disposed over the substrate and electrically connected to the active region; a landing pad disposed on the conductive pillar and electrically connected to the conductive pillar; and a stack of dielectric layers disposed over the substrate and laterally surrounding the bit line contact. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The second polysilicon layer is in direct contact with the stack of dielectric layers.

Abstract: The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a bottom contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; a liner layer positioned between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of partition layers; and a top contact layer positioned on the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

Abstract: The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a bottom contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; a liner layer positioned between the bottom contact layer and the substrate, between the bottom contact layer and the plurality of bit line structures, and between the bottom contact layer and the plurality of partition layers; and a top contact layer positioned on the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

Abstract: The present application provides a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate having an active region; a recess gate structure disposed in the substrate and intersecting the active region; a bit line contact including a polysilicon stack and disposed on the substrate; a conductive pillar disposed over the substrate and electrically connected to the active region; a landing pad disposed on the conductive pillar and electrically connected to the conductive pillar; and a stack of dielectric layers disposed over the substrate and laterally surrounding the bit line contact. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The second polysilicon layer is in direct contact with the stack of dielectric layers.

Abstract: The present disclosure provides a memory device and a method of manufacturing the memory device. The memory device includes a semiconductor substrate defined with an active area and including a plurality of fins protruding from the semiconductor substrate and disposed within the active area, wherein each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and between an adjacent pair of the plurality of fins, wherein the first word line includes an oxide layer conformal to surfaces of the adjacent pair of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed over the first conductive member and surrounded by the oxide layer; and an isolation extending into the semiconductor substrate and surrounding the active area.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate with an active region; a gate structure disposed in a gate trench in the active region; an impurity region disposed adjacent to the gate structure; at least two bit line structures positioned on the substrate; a contact layer positioned on the substrate and between the at least two bit line structures; and a conductive neck layer positioned on the contact layer and between the at least two bit line structures. The impurity region has an upper portion defining a top surface of the impurity region and a lower portion defining a bottom surface of the impurity region. A width of the top surface of the impurity region is greater than a width of the bottom surface of the impurity region.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate with an active region; a gate structure disposed in a gate trench in the active region; an impurity region disposed adjacent to the gate structure; at least two bit line structures positioned on the substrate; a contact layer positioned on the substrate and between the at least two bit line structures; and a conductive neck layer positioned on the contact layer and between the at least two bit line structures. The impurity region has an upper portion defining a top surface of the impurity region and a lower portion defining a bottom surface of the impurity region. A width of the top surface of the impurity region is greater than a width of the bottom surface of the impurity region.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

Abstract: The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Abstract: The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Abstract: The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Abstract: The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.