Patents by Inventor Ping Hsu
Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145155Abstract: Provided is a core structure of an inductor element. The manufacturing method thereof is to embed a magnetic conductor including at least one magnetic conductive layer in a core body and to from a plurality of apertures for passing coils around the magnetic conductor in the core body. Accordingly, the magnetic conductor is designed in the core body by using the integrated circuit carrier board manufacturing process, such that the overall size and thickness of the inductor element can be greatly reduced, thereby facilitating product miniaturization using the inductor element.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Che-Wei HSU, Shih-Ping HSU
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Publication number: 20240136280Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
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Publication number: 20240136728Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.Type: ApplicationFiled: September 4, 2023Publication date: April 25, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Shih-Ping HSU
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Publication number: 20240128005Abstract: The invention provides an electronic device and its manufacturing method. The electronic device includes a first conductive component, which includes a first seed layer, a first conductive layer, a first conductive thickening layer, and a first insulating layer. The first seed layer has a plurality of first seed blocks. The first conductive layer has a plurality of first conductive blocks. Each of the first conductive blocks is disposed on a top surface of the first seed block, respectively. The first conductive thickening layer has a plurality of first conductive thickened blocks, which covers one side surface of each first seed block and one side surface of each first conductive block respectively. The first insulating layer covers the first seed layer, the first conductive layer, and the first conductive thickening layer.Type: ApplicationFiled: September 8, 2023Publication date: April 18, 2024Inventor: Shih-Ping Hsu
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Patent number: 11950513Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.Type: GrantFiled: July 5, 2022Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
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Patent number: 11949190Abstract: An electrical connector includes: an insulating body; and a first row of terminals and a second row of terminals housed in the insulating body, each terminal in the first row of terminals having a tail portion, a contact portion, and a body portion, the first row of terminals including a signal terminal pair having a pair of signal terminals and a ground terminal arranged on one side of the signal terminal pair, wherein a first center distance between the contact portions of the signal terminal pair is different from a second center distance between the contact portion of the ground terminal and the contact portion of an adjacent signal terminal.Type: GrantFiled: November 12, 2021Date of Patent: April 2, 2024Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Chih-Ping Chung, Chun-Hsiung Hsu, Kuei-Chung Tsai
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Publication number: 20240101602Abstract: Provided is a peptide and method in preventing or treating infections caused by a wide spectrum of pathogens, including bacteria and fungus in hosts such as plants and animals. Methods of preventing or treating plant diseases and infection in animals are also provided.Type: ApplicationFiled: November 24, 2021Publication date: March 28, 2024Inventors: Rita P.Y. Chen, Chiu-Ping CHENG, Chien-Chih YANG, Kung-Ta LEE, Ying-Lien CHEN, Li-Hang Hsu, Hsin-Liang CHEN, Sung CHEN
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Patent number: 11940659Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
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Patent number: 11940737Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.Type: GrantFiled: May 7, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
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Publication number: 20240096838Abstract: A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.Type: ApplicationFiled: September 18, 2023Publication date: March 21, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chu-Chin HU, Shih-Ping HSU, Chih-Kuai YANG
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240085781Abstract: In a method of cleaning a photo mask, the photo mask is placed on a support such that a pattered surface faces down, and an adhesive sheet is applied to edges of a backside surface of the photo mask.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Hao-Ping CHENG, Ta-Cheng LIEN
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Publication number: 20240088070Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
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Publication number: 20240069677Abstract: A floating image generation device is disclosed, which includes a light source, an image generation module, and a floating image generation unit. The image generation module is disposed above the light source and includes a shading unit and an image generation unit. The shading unit is capable of changing light transmissivity state. The image generation unit is disposed above the shading unit. The floating image generation unit is disposed above the image generation unit. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a first floating image when the shading unit is in a first light transmissivity state. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a second floating image when the shading unit is in a second light transmissivity state.Type: ApplicationFiled: October 18, 2023Publication date: February 29, 2024Inventors: CHIH-PING HSU, RAN-SHIOU YOU, YU JEN LAI, YA HAN KO
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Patent number: 11917813Abstract: The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.Type: GrantFiled: November 17, 2021Date of Patent: February 27, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ping Hsu
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Patent number: 11908693Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.Type: GrantFiled: February 11, 2022Date of Patent: February 20, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ping Hsu
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Publication number: 20240055786Abstract: Printed circuit board assemblies (PCBAs) are a fundamental component used in nearly all electronics. PCBAs provide electrical connections and mechanical support to electronic components and are generally made of copper layers laminated onto, though, and/or between one or more non-conductive substrate layers. Press-fit pin connections are often driven through the non-conductive substrate layers to connect power or ground across multiple conductive copper layers within a PCBA and/or connect electronic components on opposing sides of the substrate layer(s). Some new PCBA designs utilize fewer, but larger contact pins (e.g., power pins) in place of a greater number of smaller contact pins. With larger contact pin sizes, press-fit pin connections become more difficult to achieve with repeatable reliability in electrical connection without damaging surrounding features in a PCBA.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Inventors: Pai-Ping HSU, Shun-Wen SHIH
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Patent number: 11894268Abstract: A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layerType: GrantFiled: January 12, 2022Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ping Hsu
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Publication number: 20240036352Abstract: A floating display device which includes a display light source, an optical imaging sheet and a micro-lens array sheet is provided. The micro-lens array sheet has a plurality of micro-lenses arranged in an array. The optical imaging sheet has a plurality of sub-imaging units arranged in an array corresponding to the micro-lenses. The sub-imaging unit includes a plurality of first sub-imaging units and a plurality of second sub-imaging units. Each of the first sub-imaging units has a first main imaging pattern, and each of the second sub-imaging unit has a second main imaging pattern. The first main imaging pattern and the second main imaging pattern have the same pattern. Wherein, the second sub-imaging units are arranged to form an auxiliary imaging pattern. At least a number of the second sub-imaging units respectively include a base imaging pattern, and the base imaging pattern is located around the second main imaging pattern.Type: ApplicationFiled: July 17, 2023Publication date: February 1, 2024Inventors: CHIH-PING HSU, RAN-SHIOU YOU, YA HAN KO
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Patent number: 11829561Abstract: A floating image generation device is disclosed, which includes a light source, an image generation module, and a floating image generation unit. The image generation module is disposed above the light source and includes a shading unit and an image generation unit. The shading unit is capable of changing light transmissivity state. The image generation unit is disposed above the shading unit. The floating image generation unit is disposed above the image generation unit. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a first floating image when the shading unit is in a first light transmissivity state. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a second floating image when the shading unit is in a second light transmissivity state.Type: GrantFiled: September 30, 2022Date of Patent: November 28, 2023Assignee: DARWIN PRECISIONS CORPORATIONInventors: Chih-Ping Hsu, Ran-Shiou You, Yu Jen Lai, Ya Han Ko