Patents by Inventor Ping Hsu

Ping Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250224097
    Abstract: A contactless key is provided, including a substrate, a plurality of light-emitting elements, a light-blocking element, and an imaging film. The light-emitting elements are fixed to the substrate. The light-blocking element is fixed to the substrate. The light-blocking element has a plurality of accommodating spaces, a first surface, and a second surface. The first surface is opposite the second surface, and the first surface has a plurality of light outlets. The accommodating spaces penetrate through the first surface and the second surface and communicate with each other via the light outlets. The light-emitting elements are respectively located in the accommodating spaces. The imaging film is opposite the first surface.
    Type: Application
    Filed: December 10, 2024
    Publication date: July 10, 2025
    Inventors: SYUAN-WEI JHANG, CHIH-PING HSU, WEI CHEN
  • Patent number: 12347919
    Abstract: The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: July 1, 2025
    Assignee: Phoenix Pioneer Technology Co., Ltd.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Publication number: 20250185236
    Abstract: The present application discloses a semiconductor structure includes a substrate having an active area, dielectric structures, and word lines. The active area is located between the dielectric structures. The word lines are situated in the active area and are surrounded by a first insulating film over the substrate. Each word line includes a word line channel film inwardly positioned in the first insulating film and the substrate, a word line electrode disposed over and surrounded by the word line channel film, and a word line insulating film conformally disposed between the word line channel film and the word line electrode. A lower portion of the word line channel film penetrates an upper portion of the substrate, while an upper portion of the word line channel film is positioned in the first insulating film above a top surface of the substrate.
    Type: Application
    Filed: February 12, 2025
    Publication date: June 5, 2025
    Inventor: PING HSU
  • Publication number: 20250174874
    Abstract: A hollow antenna substrate includes at least three layers of substrate structure. The first layer of the substrate has a first patterned metal layer and a first dielectric layer, with the first patterned metal layer embedded within the first dielectric layer, and a first upper surface and a first lower surface of the first patterned metal layer exposed to the first dielectric layer. The second layer is stacked on the first layer and has a second dielectric layer with a second patterned opening formed therein. The third layer is stacked on the second layer and has a third patterned metal layer and a third dielectric layer, with the third patterned layer embedded in the third dielectric layer and a third upper surface and a third lower surface exposed. The second patterned opening forms a hollow structure. A manufacturing method for the hollow antenna substrate is also provided.
    Type: Application
    Filed: November 27, 2024
    Publication date: May 29, 2025
    Inventors: PAO-HUNG CHOU, MING-YEH CHANG, SHIH-PING HSU
  • Publication number: 20250140646
    Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventor: PING HSU
  • Publication number: 20250142728
    Abstract: Provided is a coil carrier board, including a base coil layer, a conductive layer stacked on and bonded to the base coil layer, at least one build-up coil layer stacked on and bonded to the conductive layer, and an opening connecting the base coil layer, the conductive layer and the build-up coil layer. The coil carrier board has thick copper, fine line spacing and appropriate rigidity by means of the build-up circuit process and the structural design of the insulating layer of a photosensitive dielectric material bonded with a thermosetting dielectric material. Accordingly, the high current-carrying efficiency of the coil carrier board is enhanced, and the overall structure of the coil carrier board has better flatness, rigidity and high interlayer alignment accuracy, thereby facilitating miniaturization and automated assembly production.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Che-Wei HSU, Wen-Hung HU, Shih-Ping HSU
  • Publication number: 20250142719
    Abstract: A flexible circuit board designed for chip integration is provided. The flexible circuit board includes an insulating substrate, a conductive copper layer, a first tin layer, a second tin layer, and a first solder resist layer. The first tin layer has a first tin thickness, and the second tin layer has a greater second tin thickness. A first tin surface of the first tin layer and a second tin surface of the second tin layer are substantially level.
    Type: Application
    Filed: October 8, 2024
    Publication date: May 1, 2025
    Inventors: Chiu-Hong Lai, Wen Ping Hsu, Yi Ling Hsieh, Dong-Sheng Li, Yi Ren Chian, San Lee, Pei-Ying Lee, Ting-Yi Kuo
  • Publication number: 20250140749
    Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side; a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias positioned along the second substrate and extending through the second substrate; and a plurality of conductive lines positioned on the second substrate.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 1, 2025
    Inventor: PING HSU
  • Publication number: 20250140747
    Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side; a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias positioned along the second substrate and extending through the second substrate; and a plurality of conductive lines positioned on the second substrate.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventor: PING HSU
  • Publication number: 20250140651
    Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 1, 2025
    Inventor: PING HSU
  • Publication number: 20250089885
    Abstract: A brush roller structure includes a foam body, a central channel, a microporous area, and through holes. The foam body comprises flow channels formed by interlaced pores, and the pores have an average pore diameter ranging from 300 ?m to 500 ?m. The central channel is arranged in the foam body and communicates with the flow channels. The microporous area is located on the surface of the foam body, and has micro pores, and the diameter of the micro pores is smaller than the average diameter of the pores in the foam body. The through holes are arranged on the outer surface of the foam body, wherein the depth of the through holes is between 50 ?m and 300 ?m, and the ratio of the total area of the through holes to the outer surface of the foam body is between 10% and 90%.
    Type: Application
    Filed: June 4, 2024
    Publication date: March 20, 2025
    Inventor: Chen-Ping HSU
  • Publication number: 20250054780
    Abstract: Disclosed is a central shaft of cleaning roller, including a shaft body and a hollow inner flow channel disposed in the shaft body, and a plurality of dispersed through holes fluidly-communicable with the hollow inner flow channel arranged on an outer wall of the shaft body, and a plurality of groove structures radially extending around the surface of the outer wall of the shaft body, and the groove structures have protruding end edges protruding from the surface of the outer wall. The central shaft of cleaning roller can be used to provide better adhesion for an interface between a foam material and the outer wall thereof.
    Type: Application
    Filed: April 15, 2024
    Publication date: February 13, 2025
    Inventor: Chen-Ping HSU
  • Patent number: 12218444
    Abstract: Printed circuit board assemblies (PCBAs) are a fundamental component used in nearly all electronics. PCBAs provide electrical connections and mechanical support to electronic components and are generally made of copper layers laminated onto, though, and/or between one or more non-conductive substrate layers. Press-fit pin connections are often driven through the non-conductive substrate layers to connect power or ground across multiple conductive copper layers within a PCBA and/or connect electronic components on opposing sides of the substrate layer(s). Some new PCBA designs utilize fewer, but larger contact pins (e.g., power pins) in place of a greater number of smaller contact pins. With larger contact pin sizes, press-fit pin connections become more difficult to achieve with repeatable reliability in electrical connection without damaging surrounding features in a PCBA.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: February 4, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pai-Ping Hsu, Shun-Wen Shih
  • Patent number: 12215275
    Abstract: Compositions and methods for increasing recovery, or flowback, of hydrocarbon compounds from hydrocarbon-containing subterranean oil formations. Concentrates include a sulfonated and/or a sulfated surfactant, an alkoxylated alcohol surfactant, a coupling agent, a hydrotrope, an additional surfactant, and water. Injectate compositions for oil recovery include the concentrate and a water source such as a produced water and/or seawater. Inclusion of particular hydrotropes such as sodium xylene sulfonate and/or potassium toluene phosphate in the compositions provides higher yields of hydrocarbons recovered. Larger amounts of hydrotrope result in an increase in injectate interfacial tension, but also result, as judged by decreased turbidity, in improved compatibility of the surfactant system in injectates made with water sources comprising salts.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 4, 2025
    Inventors: Duy T. Nguyen, Tzu-Ping Hsu
  • Publication number: 20250038129
    Abstract: An inner lead structure of a flexible circuit board includes a flexible substrate, a circuit layer and a dummy circuit layer. A chip mounting area defined on the flexible substrate is provided for a chip, contacting locations defined within the chip mounting area are provided for conductive elements of the chip. The circuit layer includes inner leads, ends of the inner leads are arranged on the contacting locations and provided to be electrically connected to the conductive elements. At least one of first dummy lines of the dummy circuit layer is arranged in a space between the adjacent inner leads. The space having a distance greater than 50 um is divided into multiple spaces having distances not greater than 50 um. Proportion of the spaces without the first dummy lines and having a distance greater than 50 um is less than 0.5% in all spaces.
    Type: Application
    Filed: March 27, 2024
    Publication date: January 30, 2025
    Inventors: Wen-Ping Hsu, Yi-Ling Hsieh
  • Patent number: 12154866
    Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: November 26, 2024
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
  • Publication number: 20240371741
    Abstract: A layout structure of a flexible circuit board includes a flexible substrate, a circuit layer and a dummy circuit layer which are arranged on the flexible substrate. The circuit layer includes first inner leads, second inner leads, an inverted U-shape connection line and a horizontal inner lead. A first distance between the first inner leads is less than a second distance between the second inner leads. One of dummy leads of the dummy circuit layer is located between the first and second inner leads, another dummy lead is located between the second inner leads. The dummy leads are provided to allow lead spaces on both sides of the inverted U-shape connection line is the same. Thus, etching solution will not flow laterally in an etching space between the inverted U-shape connection line and the horizontal inner lead.
    Type: Application
    Filed: March 25, 2024
    Publication date: November 7, 2024
    Inventors: Hou-Chang Kuo, Wen-Ping Hsu, Ting-Yi Kuo, Yi-Ling Hsieh
  • Patent number: 12124638
    Abstract: A key scanning method and an input device thereof are provided. The key scanning method for an input device with at least a first key group and a subsidiary key group comprises: triggering a first main scan line electrically connected to the first key group and reading electrical signals received via a plurality of signal sensing lines electrically connected to the first key group to determine whether any said key among the first key group is triggered; and triggering a non-triggered one of a plurality of subsidiary scan lines electrically connected to the subsidiary key group and reading electrical signals received via another plurality of signal sensing lines electrically connected to the subsidiary key group to determine whether any said key among the subsidiary key group is triggered, wherein the first main scan line and the subsidiary scan lines are triggered one after another for multiple times.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: October 22, 2024
    Assignees: Darfon Electronics Corp., DARFON ELECTRONICS (SUZHOU) CO., LTD.
    Inventor: Te Ping Hsu
  • Patent number: 12108871
    Abstract: A brush roller and its manufacturing method and brush roller mold is provided, the brush roller is manufactured by foaming a gaseous pore filler, while solving the problem of using a solid pore filler foaming method to manufacture the brush roller. In addition, the brush roller of the present invention has a plurality of fluid channels communicating between any adjacent two, and the plurality of fluid channels respectively extend to the surface of the brush roller to form pores to improve the fluid permeability of the brush roller, and in the brush roller manufacturing method of the present invention, after the PVA emulsified solution is cured, the compressive stress under the condition of the predetermined compression ratio can be formed to meet the expected brush roller, and it can be used to brush the circuit substrate.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: October 8, 2024
    Assignee: Cenefom Corp.
    Inventor: Chen-Ping Hsu
  • Publication number: 20240321515
    Abstract: A coil winding machine is adapted for winding a conductive flat wire onto an iron core. The coil winding machine includes a base, a tension mechanism mounted on the base and adapted for delivering the flat wire and providing tension to the flat wire, a rotary mechanism mounted on the base and including a core base that is rotatable and that is adapted to be mounted with the iron core, and at least one clamping mechanism mounted on the base, being co-rotatable with the core base, and operable for abutting the flat wire tightly against the iron core. A tension provided by the tension mechanism, a pressure provided by the clamping mechanism, and a rotational speed of the core base correspond to one another such that rotation of the core base and the at least one clamping mechanism winds the flat wire onto the iron core.
    Type: Application
    Filed: September 12, 2023
    Publication date: September 26, 2024
    Inventors: Ren-Yo HUANG, Chih-Ping HSU, Chien-Sheng HUANG, Cheng-En WU