Fabrication methods for electronic system modules
This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.
This application claims priority to Provisional Application Ser. No. 60/318,271 filed Sep. 7, 2001.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates generally to an electronic system module and method of fabrication, and more particularly to an electronic system module fabricated on a carrier from which it can be released.
2. Description of the Related Art
The number of input/output (I/O) connections required by integrated circuit (IC) chips is increasing, to several hundred for recent microprocessor chips. As verification of complex designs becomes an increasing portion of the total design activity, it is desirable to increase the I/O count further, to provide access to more internal nodes for testing. Flip chip assembly methods have helped to provide more I/O connections because they provide an area array of connections across the entire face of an IC chip, rather than just at the perimeter as with wire bonding. However, it continues to be desirable to reduce the pad pitch, the distance between bonding pad centers, in order to achieve more I/O connections per unit area of IC chip.
A recent advance in flip chip assembly capability has been the introduction of stud bumping machines that can provide gold stud bumps on IC chips with pad pitches of less than 100 microns. However, to take advantage of this capability, the system board that receives the bumped devices must have fine traces in order to route all of the signals with space efficiency, and to support bonding pitches less than 100 microns. The most recent packaging technology to be commercially introduced is called land grid array, LGA. It builds up the wiring layers by plating a base layer of copper that has been patterned with photo resist. The external terminal pitch claimed for this packaging method is “less than 0.5 mm”. None of the available printed circuit board technologies can support direct mounting of bumped devices at a pitch of 100 microns or less. The current invention is capable of pad pitches of less than 100 microns, including a viable method for reworking defective IC chips at this bonding density.
For many years the minimum trace width available from printed circuit board vendors has been around 100 microns. Recently, advanced multi-layer circuit processes have achieved trace widths of 17 microns. The current invention is capable of achieving trace widths of 5 microns or less, together with a trace pitch of 10 microns or less.
One way to achieve fine line interconnection circuits is to employ a semiconductor fabrication facility and to build the interconnection circuit on a silicon wafer; hence the term, wafer level packaging, WLP. The precision of the associated photolithographic methods, the clean room environment with low particulate count, and the advanced substrate handling equipment of such a facility can all contribute to high-density interconnection circuits. However, the application of IC chip manufacturing facilities to this problem is more than what is required. An intermediate alternative is to apply the manufacturing resources of a glass panel fabrication facility, where the minimum feature sizes are 10 to 20 times larger than for IC chips (but still adequate for the most advanced assembly processes), and the manufacturing cost per unit area of devices produced is less than 5% of the cost per unit area of IC chips. In addition, the glass panel fabrication facility can produce system boards of any size up to approximately a meter square, whereas the largest wafers produced have a diameter of 300 mm. In order to avoid the rigidity and weight of the glass substrate, and to provide better thermal access to the heat producing components for cooling them, it is desirable to discard the glass carrier after most of the processing is done.
Typically, WLP has used redistribution circuits to map from the fine pitch available with flip chip bonding to the coarser pitch of a printed circuit board. The current invention eliminates the redistribution circuits because the printed circuits produced (termed interconnection circuits) include fine features that easily accommodate the fine pitch of the flip chip bonding.
It has been common practice to produce printed circuit boards at one facility, and perform system assembly and test at another facility. However, there are major advantages to integrating the circuit board manufacturing process with the assembly and test process to create a single, unified, fabrication, assembly, and test process. One advantage is in reducing the time to develop and debug a new design. Flexibility in the proposed process allows adaptation to component and assembly yield problems as they arise (as each additional component is assembled), providing more detailed testing sequences as necessary. For example, during prototype testing, components may be assembled onto the circuit substrate one at a time, providing a test environment of a partial system, and making the minimum change of a single IC chip between one test and the next. The test software can be adapted to address detailed issues as they arise. Once confidence has been achieved at this level, components may be assembled and tested in functional groups as the product moves into production. A tighter integration of personnel is also achieved because all of the variables are controlled in one place. This flexibility, wherein the assembly process is tailored to yield issues in real time, is not available with conventional testing methods. Usually, an entire system is assembled before any system testing is performed. The current invention employs incremental system level testing, as each component is attached to the circuit assembly. The testing of each component is performed fewer times, because the incremental assembly and test process essentially guarantees system integrity at each step. This contrasts with conventional methods requiring component test, sub-assembly test, and system test, with numerous iterations if problems develop.
More accurate and complete testing of components is provided when they are tested in their system environment, rather than individually. The system environment is created with the actual system, or a subset thereof, rather than a simulated environment created by test vectors programmed into a general-purpose tester. This can lead to lower test cost and faster test development, by eliminating the need to generate and debug detailed system response patterns. If the system level requirements are satisfactorily met, then the minutiae of component level characteristics become irrelevant. Alternatively, only the functions relevant to proper system function are tested; this is a much more manageable set of requirements than the total set of functions that all the assembled components are capable of performing.
The signal voltage swing is reducing with each new generation of IC chip technology. This makes it more difficult to test remotely through a cable, and still achieve the necessary noise margins. Providing test chips on the motherboard will provide shorter trace lengths for testing, which will be more robust with respect to both timing issues and noise margin.
Each component may be verified at an elevated system temperature before attaching the next component. This can be accomplished by heating the glass carrier underneath the circuit assembly. By providing a pre-determined test temperature to the entire circuit assembly, a speed grade can be associated with the module, as has been done in the past at the component level. Greater emphasis can be placed on environmental stress testing at the system level. Also accelerated life testing can be performed early in the life cycle of a product, and lessons learned about particular components can be incorporated into the system level test. The only tests performed on each component correspond to system level requirements; by not testing component requirements that are irrelevant to the particular system, higher system yields may be achievable.
The physical structure of the system module of the current invention can lead to other conveniences. An example relates to accelerated life testing of a module. Because the current invention allows a sophisticated system (circuit assembly) to be implemented in a module of small size, and because the system module packaging includes a metal envelope surrounding the module that provides good heat distribution, temperature control can be achieved by placing the module on a hot plate rather than in a bulky and inaccessible environmental chamber.
Hermetic packaging techniques and electromagnetic shielding techniques can be applied at the module level to improve both performance and manufacturing cost. Performance is improved because a single metal envelope encloses almost the entire module, avoiding the interference from individual components and the wiring between them. Cost is reduced because hermeticity and shielding are provided with a simple process applied once to the entire system, rather than being addressed individually at each of the components.
Such a unified process has only recently become feasible. It depends on using common semiconductor manufacturing equipment to support fabrication of the interconnection circuits, bonding sites, test connection fixtures, module cables, and the module layers that create hermeticity and electromagnetic shielding. It also depends on the fact that sophisticated and programmable IC chips can now implement the testing function across all of the components in a system, including digital, analog, and RF functions, if multiple IC chips are employed for testing. Adding these functions to the system using the current invention is not as expensive as in the past, because the packaging and assembly cost is minimal. Preferably, a tester is included with every module produced, but the cost of the tester is small compared with the system level assembly and performance benefits, and the reduction in system development time.
R. K. Traeger, “Hermeticity of Polymeric Lid Sealants”, Proc. 25th Electronics Components Conf., 1976, p.361, has documented the water permeabilities of silicones, epoxies, fluorocarbons, glasses and metals. Traeger's data shows that, in terms of providing a barrier to water, a layer of metal that is 1 micron thick is approximately equivalent to a layer of glass that is 1 mm thick, and also equivalent to a layer of epoxy that is 100 cm thick.
Generally flip chip bonding techniques require an epoxy under-layer between flip chip mounted IC chips and the circuit board. The purpose of the under-layer is to provide mechanical strength to withstand repeated thermal cycling without developing cracks in the area of the flip chip bonds. The thermal stress arises because of the difference in thermal coefficients of expansion (TCEs) between the IC chip material and the board material. Gelatinized solvents have typically been used to dissolve the epoxy; they leave a residue that must be cleaned off. The process of cleaning off the residue has typically resulted in damage to the fine pitch bonding sites, to the point where they cannot be reliably re-bonded. The under-layer is unnecessary with the current invention because the flexibility of the final interconnection circuit substantially eliminates thermally induced stress in the region of the flip chip bonds. Without the thermally induced stress, no cracking will occur. Thermal stresses are still present during assembly (because the interconnection circuit is rigid at this point), but are avoided during operation in the field (when the interconnection circuit is flexible). The number and extent of thermal cycles during assembly are more predictable and controllable than the thermal cycles arising from operation in the field. Stress testing in the laboratory can be used to quantify the acceptable temperature limits, and assure crack-free circuit assemblies. Avoiding the under-layer makes a robust rework process possible. This general concept is referred to in the art as compliant packaging technology. A related issue is the recent requirement for low stress in IC chips that use ultra-low-k dielectric materials. IC chips attached to flexible substrates will experience low stress and will be accommodating of the ultra-low-k dielectrics.
SUMMARY OF THE INVENTIONA glass substrate for 5th generation fabrication of LCD circuits is typically 1100 by 1250 mm in area, and 1.1 mm thick, which can be used in carrying out the present invention. However, the glass carrier of the current invention can be of any size. The unit manufacturing costs of interconnection circuits and related circuit assemblies of the current invention are lower if larger glass panels are used. The glass or other rigid carrier provides mechanical support for all of the fabrication, component assembly, test, and rework process steps, and also has excellent dimensional stability. This dimensional stability transfers to the multi-layer circuits that are built up as a series of films on top of the glass. This transferred dimensional stability is a primary reason that fine line features such as trace widths less than 5 microns are possible with the current invention. It is also important however, that the final version of the interconnection circuit be flexible, because the flexibility allows the use of epoxy under layers to be avoided, leading to more robust rework processes for removing and replacing defective chips. The flexibility also allows system boards to be folded in compact devices such as cellular phones.
A release agent is applied to a glass panel substrate, except for a clear region near the edges. The clear region is characterized by high adhesion between the glass and the polymer base layer to be subsequently formed on the glass. The high adhesion region provides an anchor that firmly attaches the polymer to the glass around the perimeter of the panel. The release layer creates low adhesion between glass and polymer, so that after a circuit assembly has been built on top, it can be readily peeled off.
Alternate layers of metal interconnect and dielectric such as a photo-definable polymer are built up on the base layer. Two-level contacts are formed between adjacent metal layers, and stacked contacts are provided between groups of adjacent layers. Preferably each input/output (I/O) pad of an assembled IC chip is a node of the multi-layer interconnection circuit. At the center of each I/O pad a stacked contact is created, with stubs at every metal layer, for convenient routing of traces. The base polymer layer, the dielectric layers and the metal layers are flexible, and when the multi-layer interconnection circuit is subsequently removed from the glass panel, it too is flexible. Attached IC chips are usually not flexible, but if a folding line on the interconnection circuit is kept clear of IC chips, then the circuit assembly can be folded at the folding line.
While the multi-layer interconnection circuit is still attached to the glass carrier, it is convenient to form wells filled with solder on the array of interconnection circuits, in large substrate form. Each well is designed to accept a stud bump of an attached component. Gold stud bumps are formed at I/O pads of all IC chips to be assembled. To create the wells a thick layer of polymer is applied on top of the interconnection circuit. Openings in this layer are formed at I/O pad bonding sites. The openings in the cured polymer layer form a mask, and solder paste is wiped over the mask to fill the openings, thus forming a well at each of the I/O bonding sites.
The glass carrier is diced with a diamond saw to separate individual circuit assemblies from one another, and provide a more convenient form for component assembly, test, and rework. The interconnection circuit itself must be tested, before any assembly is done. This test is performed using a test fixture that connects through a module access port to an external tester. The module access port may include I/O pads (module access pads) for every node of the multi-layer interconnection circuit. The assembly and rework steps require that IC chips and other surface mounted components are precisely located in order that the bonding tool can accurately align bonding sites on the components with corresponding bonding sites on the interconnection circuit. Accordingly, the circuit assembly remains attached to the glass carrier, and its dimensional accuracy is maintained until these steps are completed.
A module cable with high-density interconnections is attached to each circuit assembly. The circuit assemblies are then separated from their individual glass carriers by peeling the base substrate away from the carrier. Since the adhesion force is low in these regions, they can be separated without damage.
Additional metal coatings are applied to create a circuit module that is hermetically sealed and electro-magnetically shielded. To effectively cool the dense circuit module, it may be bonded to a heat sink, and the heat sink may be cooled with a circulating fluid.
BRIEF DESCRIPTION OF THE DRAWINGS
It should be understood that for diagrammatic purposes the figures are not drawn to scale.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Stacked contact 50 is necessarily larger in horizontal area than two-level contact 33, because of the long sloping contact walls of the stacked contact. The trace pitch for parallel runs of metal is a critical parameter for densely packed interconnection circuits. Parallel runs of metal generally require contacts to traces on other layers for effective trace routing of a multi-layer interconnection circuit. To achieve minimum trace pitch for such parallel runs, it is desirable to use contacts of minimum size. This can be accomplished if contacts that are formed at locations other than at the I/O pads are limited to two-level contacts. This is shown in
Having explained the details of building a high density interconnect structure in the form of a flexible multi-layer interconnection circuit, we shall now focus on assembly and testing of IC chips on the interconnection circuit, to form a circuit assembly.
The amount of paste in a well is approximately 1.5×10−7 gm in the preferred embodiment, at a material cost of approximately US$0.10 (10 cents) per gram. The labor and equipment costs of forming wells filled with solder are low for large glass carriers because several million wells are created in parallel. Included in the processing are a photolithographic step to form the solder paste mask, and wiping of a squeegee over the mask to deposit solder paste in the wells. The cost per stud bump using the Kulicke and Soffa 8098 bonder is approximately 0.03 cents, based on 200,000 bumps on an 8-inch wafer. Consequently, the cost of each flip chip connection in the current invention, including the stud bump and the corresponding well, is less than 0.05 cents or US$0.0005. This compares with current costs per connection of at least one cent for wire bonding and other flip chip bonding methods. Such a low cost for the current invention means that additional test points can be added to the module access port to make testing easier and more effective, perhaps decreasing the overall system cost due to testing economies.
The layout of circuit assembly 80 is so dense, both in the fine line traces, and in the fine pitch assembly, that conventional connectors and cables are not well suited for interconnecting modules of this type; they would occupy a large fraction of the total module space. Consequently, part of the current invention is to provide an effective means for connecting circuit assemblies to testers, and circuit modules to other circuit modules or to other electronic systems employing different manufacturing methods. The same methods that are used to fabricate circuit assembly 80 can also be used to fabricate a test fixture and a module cable.
In
Before permanently assembling a module cable to the circuit assembly, it is desirable to coat the top surface with a dielectric layer and a metal layer. The dielectric layer prevents shorting of components when the metal layer is subsequently applied. The metal layer provides a shield at the top surface, except for small holes at the module access pads, as will be further described in reference to
Referring back to
It is desired to create a continuous metal envelope around the circuit assembly including the interconnection circuit and the attached components, with only a small opening at each of the module access pads. It is critical that the top and bottom metal layers form an overlapping seam of continuous metal at the edge of the circuit assembly. A preferred method for achieving this is shown in
In
Claims
1. An electronic module comprising:
- a flexible interconnection circuit having conductive traces with a width of five microns or less and a trace pitch of ten microns or less, and,
- a plurality of integrated circuit chips mounted on said interconnection circuit using flip chip bonding.
2. The electronic module of claim 1 wherein said flip chip bonds include stud bumps on each input/output pad of said integrated circuit chips, and corresponding wells filled with solder on said interconnection circuit, said wells connecting with traces connected to nodes of said interconnection circuit.
3. The electronic module of claim 2 wherein said nodes of said interconnection circuit connect with module access pads provided at the surface of said electronic module.
4. The electronic module of claim 3 wherein said module access pads connect with wells filled with solder.
5. The electronic module of claims 2 or 4 wherein said wells filled with solder are spaced with a pitch of 100 microns or less.
6. The electronic module of claim 1 wherein said integrated circuit chips are thermally coupled to a heat sink.
7. The electronic module of claim 6 wherein said thermal coupling includes a layer of conductive adhesive between faces of said integrated circuits or between films covering said faces of said integrated circuits and a surface of said heat sink.
8. The electronic module of claim 6 wherein said heat sink includes a cooling fluid.
9. A method for fabricating a multi-layer interconnection circuit comprising the steps of:
- providing a rigid carrier,
- applying a base polymer layer on said rigid carrier,
- fabricating a multi-layer interconnection circuit having alternate layers of patterned metal and patterned polymer on said base layer, said patterned metal layers having traces with line widths of 5 microns or less and a metal trace pitch of 10 microns or less.
10. A method for fabricating a multi-layer interconnection circuit comprising the steps of:
- providing a rigid carrier,
- applying a release layer to said rigid carrier,
- applying a base polymer layer on said release layer,
- fabricating a multi-layer interconnection circuit having alternate layers of patterned metal and patterned polymer on said base polymer layer, said patterned metal layers having traces with line widths of 5 microns or less and a metal trace pitch of 10 microns or less.
11. A method for fabricating an interconnection device comprising the steps of:
- providing a rigid carrier,
- applying a release layer to said rigid carrier,
- applying a base polymer layer on said release layer,
- fabricating a multi-layer interconnection circuit having alternate layers of patterned metal and patterned polymer on said base polymer layer, said patterned metal layers having traces with line widths of 5 microns or less and a metal trace pitch of 10 microns or less,
- applying a polymer layer over said interconnection circuit, said polymer layer having openings positioned over selected traces, and,
- filling said openings with solder.
12. The method of claims 9, 10 or 11 wherein said rigid carrier is a glass carrier.
13. The method of claims 9, 10 or 11 wherein said patterned polymer is photo-defined.
14. The method of claims 9, 10 or 11 wherein said interconnection circuit or said interconnection device is separated from said rigid carrier after processing.
15. The method of claims 9, 10 or 11 wherein said interconnection circuit is flexible.
16. The method of claims 10 or 11 wherein said release layer is a fluorinated silicone.
17. The method of claim 10 or 11 wherein said release layer is not present near the edges of said rigid carrier, to provide an edge region of strong adhesion between said base polymer layer and said rigid carrier.
18. The method of claim 10 or 11 wherein said release layer is not present in streets provided at the periphery of each of said multi-layer interconnection circuits, said streets providing regions of strong adhesion between said base polymer layer and said rigid carrier.
19. The method of claim 12 wherein said glass carrier measures more than 500 mm on a side.
20. An interconnection device comprising:
- a rigid substrate,
- one or more layers of patterned metal having traces with line widths of 20 microns or less and a metal trace pitch of 40 microns or less,
- a polymer layer applied over said traces having openings positioned over selected traces, and,
- solder filling each of said openings.
21. A stacked contact formed between a plurality of patterned metal layers of an interconnection circuit, comprising:
- planarizing layers of patterned polymer between each of said patterned metal layers,
- contact windows with tapered walls in each of said planarizing layers, wherein said contact windows are positioned above contacting traces of metal on a preceding layer, and,
- patterned metal of succeeding metal layers with traces positioned over said contact windows to contact said contacting traces of metal on said preceding layers.
22. The stacked contact of claim 21 wherein said patterned polymer is photo-defined.
23. The stacked contact of claim 21 wherein said patterned polymer is photo-imageable Cyclotene.
24. The stacked contact of claim 21 wherein trace stubs are provided at each metal layer in the stacked contact.
25. A multi-layer interconnection circuit wherein a stacked contact providing connection between all of the conducting layers is included at each input/output pad of each integrated circuit chip to be assembled on said multi-layer interconnection circuit.
26. The multi-layer interconnection circuit of claim 25 wherein contacts of said multi-layer interconnection circuit, other than said stacked contacts, are limited to two-level contacts where a desired minimum trace pitch is to be maintained.
27. A method for forming closely spaced wells filled with solder on a flexible interconnection circuit comprising the steps of:
- providing a rigid carrier for said interconnection circuit,
- applying a layer of polymer on said interconnection circuit,
- etching openings in said polymer layer at each input/output pad, and,
- depositing solder paste in said openings.
28. The method of claim 27 wherein said solder paste is deposited in said openings using a squeegee.
29. A method for assembling integrated circuit chips on an interconnection circuit having conductive traces comprising the steps of:
- providing a stud bump on each input/output pad of each of said integrated circuit chips,
- fabricating wells filled with solder on said interconnection circuit, said wells having a one-to-one correspondence with said input/output pads of said integrated circuit chips and said wells are positioned above selected conductive traces,
- inserting said stud bumps of each of said integrated circuit chips in said corresponding wells filled with solder, and,
- heating and cooling said solder to make permanent connections.
30. The method of claim 29 wherein said interconnection circuit is flexible.
31. A circuit assembly comprising:
- a plurality of integrated circuits having stud bumps at each input/output pad,
- an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said stud bumps of said integrated circuits, and,
- electrical and mechanical bonding at each of said input/output pads wherein each of said stud bumps connects with solder in each of said wells to form a permanent connection.
32. The circuit assembly of claim 30 wherein said interconnection circuit is flexible.
33. A method for building a tested circuit assembly having multiple integrated circuit chips on an interconnection circuit, comprising the steps of:
- stud bumping each input/output pad of each of said integrated circuit chips,
- fabricating wells filled with solder on said interconnection circuit, said wells having a one-to-one correspondence with said input/output pads of said integrated circuit chips and each well is connected to a trace of said interconnection circuit chip,
- selecting the first integrated circuit chip to be assembled,
- inserting stud bumps of said integrated circuit chip in corresponding wells of said interconnection circuit,
- heating and cooling said solder to make a permanent connection between said stud bumps of said integrated circuit chip and said corresponding wells,
- testing said integrated circuit chip in said circuit assembly,
- if the result of said testing of said integrated circuit chip is “pass”, selecting the next integrated circuit chip to be assembled and continuing at step d until all of said integrated circuit chips have been assembled and have tested with a result of “pass”,
- if the result of said test of said integrated circuit chip is “fail”, applying heat until said solder melts in said corresponding wells of said failed integrated circuit chip, and removing said stud bumps of said failed integrated circuit from said corresponding wells,
- inspecting said corresponding wells and touching up if necessary,
- selecting a replacement for said failed integrated circuit and continuing at step d. until all of said integrated circuit chips have been assembled and have tested with a result of “pass”.
34. The method of claim 33 wherein said circuit assembly includes a module access port for connecting to a tester, said module access port comprising an array of module access pads, each of said module access pads connecting to a node of said interconnection circuit.
35. A method for testing an interconnection circuit comprising the steps of:
- providing a module access port including an array of module access pads, each module access pad connecting to a node of said interconnection circuit,
- providing means to connect from said module access port to a tester, thereby connecting nodes of said interconnection circuit to corresponding nodes of said tester, and,
- testing said nodes of said interconnection circuit for correct connectivity.
36. A method for incremental assembly and test of a circuit assembly comprising the sequential steps of:
- providing a tested interconnection circuit,
- providing a full set of electronic components required by said circuit assembly,
- selecting the first electronic component to be assembled,
- assembling said electronic component on said interconnection circuit,
- testing said electronic component in the system environment including the subset of electronic components already assembled,
- if said electronic component operates correctly in said system environment, selecting the next electronic component to be assembled,
- if said electronic component is a defective component in said system environment, removing said defective component and selecting a replacement electronic component, and,
- repeating steps d through g until all of said electronic components are assembled and tested on said interconnection circuit with none of said defective components remaining, to create a version of said circuit assembly meeting all of the tested specifications.
37. The method of claim 36 wherein the unit of assembly is a group of components rather than a single component.
38. The method of claim 36 wherein said testing of said electronic components is performed using special-purpose electronic components that are the first of said electronic components to be assembled on said circuit assembly.
39. The method of claim 36 wherein said testing of said electronic components is performed using an external tester.
40. A test fixture for testing an electronic assembly comprising:
- a rigid substrate,
- an interconnection circuit fabricated on said rigid substrate having two sets of input/output pads, one set connecting to said circuit assembly and another set connecting with a tester, said interconnection circuit having conductive traces that connect between corresponding input/output pads of each of said sets, and,
- a stud bump at each of said input/output pads in each of said sets.
41. The test fixture of claim 40 and including a fine pitch of said input/output pads at the end connecting with said circuit assembly and a coarser pitch of said input/output pads at the end connecting with said tester.
42. The test fixture of claim 40 and including three or more sets of input/output pads for connection to three or more circuit assemblies or electronic systems.
43. A module cable for connecting between a parent module and another electronic system comprising:
- a rigid carrier for supporting said module cable during manufacture and assembly, including the steps of connecting said module cable to said parent module and to said electronic system,
- a base polymer layer on said rigid carrier,
- an interconnection circuit fabricated on said base polymer layer having two sets of input/output pads, one set at the parent end of said module cable and one set at the other end, with conductive traces that connect in a one-to-one relationship between each of said input/output pads in each of said sets, and,
- a stud bump at each input/output pad in each of said sets of input/output pads of said module cable.
44. The module cable of claim 43 and including a release layer between said rigid carrier and said base polymer layer.
45. The module cable of claim 43 and including three or more sets of I/O pads for connection to three or more electronic modules or systems.
46. The module cable of claim 43 wherein said rigid carrier is separated from said module cable after said connecting steps are performed.
47. The module cable of claim 43 wherein a portion of said rigid carrier is removed after each of said connecting steps is performed.
48. A method for building an electronic module with an attached module cable comprising the steps of:
- providing a module cable having a rigid carrier, a base polymer layer, an interconnection circuit fabricated on said base polymer layer having two sets of input/output pads, a first set at a first end of said module cable and a second set at the other end, with conductive traces that connect in a one-to-one relationship between one of said input/output pads in said first set and a corresponding input/output pad in said second set, and a stud bump at every input/output pad in each of said first and second sets of input/output pads of said module cable,
- providing wells filled with solder at a surface of said electronic module, said wells connecting with nodes of said electronic module and having a one-to-one relation with said first set of input/output pads of said module cable,
- inserting said stud bumps of said first set of input/output pads in said wells,
- applying heat until said solder melts, and,
- cooling to form a permanent connection between said module cable and said electronic module.
49. The method of claim 48 and including the step of removing a portion of said rigid carrier after said permanent connection has been made.
50. The method of claim 48 and including the step of removing said rigid carrier after a permanent connection has been made to an electronic system at each end of said module cable.
51. The method of claim 48 and including 3 or more sets of input/output pads on said module cable, each set connecting with a separate electronic module or system.
52. The method of claim 51 and including the step of removing said rigid carrier after said permanent connections have been made to said separate electronic modules or systems.
53. A hermetically sealed electronic circuit module having attached components comprising:
- a module access port including an array of module access pads,
- a dielectric layer coating said circuit module at surfaces having attached components, with openings at said module access pads, and,
- a continuous metal film coating the entire surface of said circuit module, except for openings at said module access pads.
54. An electro-magnetically shielded electronic circuit module having attached components comprising:
- a module access port including an array of module access pads,
- a dielectric layer coating said circuit module at surfaces having attached components, with openings at said module access pads, and,
- a continuous metal film coating the entire surface of said circuit module, except for openings at said module access pads.
55. The electro-magnetically shielded circuit module of claim 54 wherein said continuous metal film is grounded.
Type: Application
Filed: Feb 25, 2005
Publication Date: Jun 30, 2005
Inventor: Peter Salmon (Sunnyvale, CA)
Application Number: 11/066,964