Semiconductor device and method of fabricating the same
A semiconductor device includes a semiconductor substrate, an insulative film formed above the semiconductor substrate, the film having a first groove and a second groove greater in width than the first groove, a wiring lead buried in the first groove of the insulative film to have a substantially flat surface, and a capacitor buried in the second groove of the insulative film to have a substantially flat surface, the capacitor having a multilayer structure including a first conductive film identical in material to the lead, a capacitor dielectric film, and a second conductive film.
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This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-276987, filed on Sep. 12, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates generally to a semiconductor device and, more particularly, to a semiconductor device having a buried wiring lead (wire lead) structure. This invention also relates to methodology of fabricating a semiconductor device of the type employing the buried wiring lead structure.
2. Description of Related Art
Metal wiring lines or leads are used to achieve electrical interconnection among elements of a semiconductor integrated circuit (IC) chip. Traditionally such on-chip metal wiring leads are typically manufacturable by patterning a metal film made of aluminum (Al) or else as formed on or above an electrically insulative dielectric film using lithography and anisotropic etching techniques in combination. As the circuit elements decrease in size due to the quest for higher integration in the chip, the wiring leads are becoming smaller in line width and in marginal spacing (pitch). This miniaturization makes it difficult to bury a dielectric film in space between patterned leads. An approach to avoiding this difficulty is to make use of a damascene method in place of prior known A1 lead formation methods. The damascene method is the one that processes or micromachines a dielectric film to form therein a wiring lead groove and then buries conductive material, such as copper (Cu) or the like, in this groove by metal plating techniques.
In addition, in cases where capacitive elements of large capacitance are required within IC chips, metal-insulator-metal (MIM) capacitors are employed from time to time in lieu of conventional silicon-insulator-silicon (SIS) capacitors. MIM capacitors are typically designed to have a lamination or multilayer structure of upper and lower metallic layers with a dielectric film interposed between them. Preferably in this case, electrodes of such MIM capacitors are fabricated at the same time that on-chip leads are formed.
See FIGS. 13 to 16. These diagrams illustrate, in cross-section, some of major steps in the process for simultaneously forming a MIM capacitor and its associative Cu wiring lead by the damascene method. The simultaneous MIM-capacitor/Cu-lead fabrication process has been disclosed, for example, in Published Unexamined Japanese Patent Application No. 2001-36010 (“JP-A-2001-36010”). Firstly, as shown in
Unfortunately the prior art Cu-damascene method stated above is encountered with several problems which follow.
First, as shown in
Second, as shown in
Third, the Cu lead 4a can unintentionally be oxidized on its surface exposed to a corresponding contact hole during formation of the upper lead 9's contact holes by anisotropic etching, which would result in an increase in electrical resistivity.
SUMMARY OF THE INVENTIONA semiconductor device in accordance with one aspect of this invention includes a semiconductor substrate, an insulative film formed above the semiconductor substrate, the film having a first groove and a second groove greater in width than the first groove, a wiring lead buried in the first groove of the insulative film to have a substantially flat surface, and a capacitor buried in the second groove of the insulative film to have a substantially flat surface, the capacitor having a multilayer structure including a first conductive film identical in material to-the lead, a capacitor dielectric film, and a second conductive film.
A method of fabricating a semiconductor device in accordance with another aspect of the invention includes forming a first groove in a wiring region of an insulative film overlying a semiconductor substrate while forming in a capacitor region a second groove greater in width than the first groove, depositing a first conductive film above the insulative film with the first groove and the second groove formed therein in such a way that the first conductive film is buried in the first and second grooves to fully fill the first groove while partially filling the second groove to a level between a bottom and a top of the second groove, depositing a capacitor dielectric film above the first conductive film so that the capacitor dielectric film is buried in the second groove to partially fill the second groove, depositing a second conductive film above the capacitor dielectric film so that the second conductive film is buried in the second groove to fully fill the second groove, and polishing the second conductive film, the capacitor dielectric film and the first conductive film until exposure of the insulative film to thereby form a wiring lead with the first conductive film buried in the first groove while forming a capacitor with the first conductive film, the capacitor dielectric film and the second conductive film buried in the second groove.
A semiconductor device in accordance with still another aspect of the invention includes a semiconductor substrate, an insulative film formed above the semiconductor substrate, the film having a wiring groove with a widened contact portion formed therein, and a wiring lead with a first conductive film buried in the wiring groove, wherein the wiring lead has a structure with a second conductive film selectively covering an upper surface of the first conductive film at a central part of the contact portion and with the first conductive film being substantially planarly buried in the wiring groove at remaining part other than the contact portion.
A semiconductor device fabrication method in accordance with yet another aspect of the invention includes forming in an insulative film above a semiconductor substrate a groove having a wiring lead portion and a contact portion as continued thereto, the contact portion being greater in width than the wire lead portion, depositing above the insulative film with the groove formed therein a first conductive film in such a way that the first conductive film is buried in the groove to fully fill the wiring lead portion while partially filling the contact portion, depositing above the first conductive film a second conductive film so that the second conductive film is buried to fully fill the contact portion, and polishing the second conductive film and the first conductive film to thereby form a wiring lead with the first conductive film buried in the wiring lead portion and with a multilayer of the first and second conductive films buried in the contact portion.
BRIEF DESCRIPTION OF THE DRAWINGS
Some illustrative embodiments of this invention will be explained in detail with reference to the accompanying drawings below.
Embodiment 1 A semiconductor integrated circuit (IC) device in accordance with one embodiment of the invention is shown in
Practically as an example, the wiring lead groove 13a is arranged to measure 0.2 micrometers (μm) in width and 0.4 μm in depth. The capacitor groove 13b is designed to have its width which falls within a range of from about 10 to 100 μm, although it differs depending upon the required capacitance value on a case-by-case basis. Capacitor groove 13b has a depth that is set at an appropriate value required for the entirety of such capacitor. Additionally, as shown in
Thereafter, as shown in
The capacitor dielectric film 15 is a silicon nitride (SiN) film with a thickness of approximately 0.1 μm, by way of example. The second conductor film 16 may be a titanium nitride (TiN) film with a thickness of about 0.15 μm. These films are deposited by chemical vapor deposition (CVD) techniques. The process condition required here is that the capacitor groove 13b is not fully filled with the buried films in a direction along the depth thereof even when the deposition of capacitor dielectric film 15 is completed.
Thereafter, the device structure of
Subsequently, after having formed a Cu diffusion preventing insulator film (not shown) when the need arises, deposit an interlayer dielectric (ILD) film 17 as shown in
With the illustrative embodiment, as the capacitor and the wiring leads are planarly buried in the grooves, the ILD film 17 shown in
While in the first embodiment (Embodiment 1) the wiring lead groove and capacitor groove are made different in depth from each other, a similar structure is obtainable even when the grooves are modified to be identical in depth to each other. An embodiment employing this approach will next be discussed in conjunction with FIGS. 5 to 8 below. Note that like parts and parts performing similar functions in this embodiment are designated by like reference numerals used in the previous embodiment.
As shown in
Thereafter, as shown in
An example of the capacitor dielectric film 15 is a SiN film with a thickness of about 0.1 μm. The second conductor film 16 may be a TiN film which is about 0.15 μm thick. These films are deposited by CVD methods. The process condition required here is that even at the stage that the capacitor dielectric film 15 has been deposited, the capacitor groove 13b is not yet fully filled with the buried film 15 in the direction along the depth thereof.
The resultant structure of
Subsequently, after having formed a Cu outdiffusion preventing dielectric film (not shown) as circumstances demand, deposit an ILD film 17 as shown in
With this embodiment also, as both the capacitor and its associated wiring lead(s) are buried planarly in the grooves, the ILD film 17 shown in
An explanation will next be given of an embodiment which is capable of precluding oxidation at wiring lead contact portions with reference to
Thereafter, as shown in
Thereafter, apply planarization processing to the resultant device structure. More specifically, use CMP methods to polish the second conductor film 25 and first conductor film 24 until the surface of dielectric film 22 is exposed as shown in
After having formed a Cu diffusion preventing dielectric film (not shown) when the need arises, deposit an ILD film 26 as shown in
As apparent from the foregoing, with this embodiment, it is possible to form the required TiN film excellent in oxidation resistivity only at the Cu-lead contact portion. This makes it possible to successfully prevent any unwanted oxidation of Cu wiring leads after completion of the formation of contact holes, thus enabling achievement of low resistance contacts with increased stability and enhanced reliability.
It must be noted here that while the technique is discussed for designing the wiring leads to have a multilayer structure in order to improve the corrosion resistivity of contact portions of buried Cu leads, this technique per se is known in the art to which the invention pertains. One method is as follows. Firstly bury a Cu film in a wiring lead groove. Then apply wet etching to the surface of this Cu film for recessing. Next, deposit a TiN film thereon by CVD or other similar suitable processes; thereafter, planarize the surface of resultant device structure. Unfortunately this approach does not come without accompanying a penalty: the Cu film can decrease in thickness for the entirety of wiring leads. This is because the entire part of the buried Cu leads must experience recess-etching. The Cu film thinning results in a likewise increase in electrical resistivity of the wiring leads. In contrast, the embodiment stated above is free from such risk of lead resistivity increase. This can be said because the TiN film is left only at the central portion of a buried Cu wiring lead with respect only to the contact portion. The “TiN film centralization” feature precludes any possible increase in on-chip lead resistance. In this respect, this embodiment is superior than the prior art.
This embodiment is also employable in the MIM capacitor-containing lead structures of Embodiments 1-2 stated supra. Note however that in this case, a need is felt to prevent a capacitor dielectric film from residing in the lead contact portion. Thus the process includes an additional step of etching the capacitor dielectric film.
Optionally the wiring lead and the lead contact portion as simultaneously formed in this embodiment may be modified to have a so-called “dual damascene” lead structure as in the wiring leads formed of third conductive film discussed previously.
Furthermore, although in Embodiments 1-3 the second conductor film is made of TiN, this is replaceable by other similar suitable materials including, but not limited to, titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).
It has been stated that according to this invention, it is possible to obtain a semiconductor device having a preferable damascene on-chip wiring lead structure.
While the present invention has been particularly shown and described with reference to the specific embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit, scope and teachings of the invention. The invention is, therefore, to be limited only as indicated by the scope of the appended claims.
Claims
1-11. (canceled)
12. A method of fabricating a semiconductor device, said method comprising:
- forming a first groove in a wiring region of an insulative film overlying a semiconductor substrate while forming in a capacitor region a second groove greater in width than the first groove;
- depositing a first conductive film above said insulative film with said first groove and said second groove formed therein in such a way that said first conductive film is buried in the first and second grooves to fully fill said first groove while partially filling said second groove to a level between a bottom and a top of said second groove;
- depositing a capacitor dielectric film above said first conductive film so that said capacitor dielectric film is buried in said second groove to partially fill said second groove;
- depositing a second conductive film above said capacitor dielectric film so that said second conductive film is buried in said second groove to fully fill said second groove; and
- polishing said second conductive film, said capacitor dielectric film and said first conductive film until exposure of said insulative film to thereby form a wiring lead with said first conductive film buried in said first groove while forming a capacitor with said first conductive film, said capacitor dielectric film and said second conductive film buried in said second groove.
13. The method according to claim 12, wherein said second groove is formed to be deeper than said first groove, and wherein said first conductive film is buried in said first groove by deposition to a thickness equal to or greater than a depth of said first groove.
14. The method according to claim 12, wherein said first and second grooves are formed to substantially the same depth, and wherein said first conductive film is buried in said first groove by deposition to a thickness equal to or greater than half of a width of said first groove.
15. The method according to claim 12, wherein said first conductive film is a metal-plated Cu film.
16. The method according to claim 12, further comprising:
- depositing an interlayer dielectric film covering said wiring lead and said capacitor;
- forming, in said interlayer dielectric film, contact openings for connection to said lead and said capacitor and an upper-level wiring lead groove coupled thereto; and
- burying a third conductive film in said contact openings and said upper-level wiring lead groove.
17. The method according to claim 12, further comprising:
- forming above said insulative film another insulative film covering said capacitor and said lead; and
- forming in said another insulative film a first hole leading to said second conductive film of said capacitor and a second hole being coupled to said lead and being substantially the same in depth as said first hole.
18. A method of fabricating a semiconductor device comprising:
- forming in an insulative film above a semiconductor substrate a groove having a wiring lead portion and a contact portion as continued thereto, said contact portion being greater in width than said wire lead portion;
- depositing above said insulative film with said groove formed therein a first conductive film in such a way that said first conductive film is buried in said groove to fully fill said wiring lead portion while partially filling said contact portion;
- depositing above said first conductive film a second conductive film so that said second conductive film is buried to fully fill said contact portion; and
- polishing said second conductive film and said first conductive film to thereby form a wiring lead with said first conductive film buried in said wiring lead portion and with a multilayer of the first and second conductive films buried in said contact portion.
19. The method according to claim 18, wherein said first conductive film is a metal-plated Cu film and said second conductive film is a chemically vapor deposited film made of a material selected from the group consisting of Ti, TiN, Ta, TaN, W and WN.
20. The method according to claim 18, further comprising:
- depositing an interlayer dielectric film covering said wiring lead;
- forming in said interlayer dielectric film a contact opening for connection to said contact portion and an upper-level wiring lead groove coupled thereto; and
- burying a third conductive film in said contact opening and said upper-level wiring lead groove.
Type: Application
Filed: Feb 16, 2005
Publication Date: Jul 7, 2005
Applicant: Kabushiki Kaisha Toshiba (Tokyo)
Inventor: Kazutaka Akiyama (Matsudo-shi)
Application Number: 11/058,295