Encapsulated semiconductor components and methods of fabrication
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
This invention relates generally to semiconductor manufacture and packaging. More particularly, this invention relates to encapsulated semiconductor components, to methods for fabricating the components, and to systems incorporating the components.
BACKGROUND OF THE INVENTIONIn semiconductor manufacture, different types of components have been developed recently, that are smaller and have a higher input/output capability than conventional plastic or ceramic packages. For example, one type of semiconductor component is referred to as a chip scale package (CSP) because it has an outline, or “footprint”, that is about the same as the outline of the die contained in the package.
Typically, a chip scale package includes a dense area array of solder bumps, such as a standardized grid array as disclosed in U.S. Pat. No. 6,169,329 to Farnworth et al. The solder bumps permit the package to be flip chip mounted to a substrate, such as a package substrate, a module substrate or a circuit board. Another type of component, referred to as a bumped die, can also include solder bumps in a dense area array. Bumped dice are sometimes considered as the simplest form of a chip scale package. Another type of component, referred to as a BGA device, is also sometimes considered a chip scale package. Yet another type of component as disclosed in U.S. Pat. No. 6,150,717 to Wood et al. is referred to as a direct die contact (DDC) package.
The quality, reliability and cost of these types of components is often dependent on the fabrication method. Preferably a fabrication method is performed on a substrate, such as a semiconductor wafer, containing multiple components, in a manner similar to the wafer level fabrication of semiconductor dice. A wafer level fabrication method permits volume manufacture with low costs, such that the components are commercially viable.
In addition to providing volume manufacture, the fabrication method preferably produces components that are as free of defects as possible. In this regard, semiconductor dice include relatively fragile semiconductor substrates that are susceptible to cracking and chipping. It is preferable for a fabrication method to protect the dice, and prevent damage to the fragile semiconductor substrates of the dice. Similarly, it is preferable for the completed components to have structures which provide as much protection as possible for the dice.
The present invention is directed to a novel wafer level fabrication method for fabricating semiconductor components, such as chip scale packages, BGA devices and DDC devices, in large volumes, at low costs, and with minimal defects. In addition, the fabrication method produces components with increased reliability, and with a chip scale outline, but with the dice protected on six surfaces by polymer layers.
SUMMARY OF THE INVENTIONIn accordance with the present invention, encapsulated semiconductor components, methods for fabricating the components, and systems incorporating the components are provided.
In a first embodiment, the component comprises a semiconductor package in a chip scale configuration, and containing a single die having a circuit side, a back side and four edges. The die includes a semiconductor substrate thinned from the back side, and integrated circuits in a required configuration on the circuit side. In addition, the die includes die contacts on the circuit side in electrical communication with the integrated circuits.
In addition to the die, the component includes planarized contact bumps on the die contacts, and terminal contacts on the planarized contact bumps. The terminal contacts can comprise conductive bumps or balls, in a dense area array, such as a grid array, or alternately planar pads configured as an edge connector. The component also includes a circuit side polymer layer on the circuit side of the die encapsulating the planarized contact bumps, a back side polymer layer on the thinned back side of the die, and edge polymer layers on the edges of the die.
For fabricating the component, a substrate is provided which contains a plurality of semiconductor dice having the die contacts formed thereon. For example, the substrate can comprise a semiconductor wafer, or portion thereof, which contains dice separated by streets. Initially, conductive bumps are formed on the die contacts using a suitable process, such as bonding pre-formed balls, electroless deposition, electrolytic deposition, or stenciling and reflowing of conductive bumps. Trenches are then formed in the substrate between the dice to a depth that is less than a thickness of the substrate. The trenches can be formed by scribing, etching or lasering the substrate.
The circuit side polymer layer is then formed on the bumps and in the trenches, and both the circuit side polymer layer and the bumps can be planarized. The circuit side polymer layer can be formed using a nozzle deposition process, a transfer molding process, an injection molding process, a screen printing process, a stenciling process, a spin resist process, a dry film process, a stereo lithographic process, or any other suitable deposition process. The circuit side polymer layer protects the dice during the fabrication process, and also protects the dice in the completed components. Following formation of the circuit side polymer layer, the substrate is thinned from the back side, such that the polymer filled trenches are exposed. The thinning step can be performed by mechanically planarizing the substrate or by etching the substrate.
Next, the back side polymer layer is formed on the thinned back side of the substrate and can also be planarized. The back side polymer layer can be formed as described above for the circuit side polymer layer. The back side polymer layer protects the dice during the fabrication process, and also protects the dice in the completed components.
Next, the terminal contacts are formed on the contact bumps using a suitable deposition or bonding process. Finally, grooves are formed through the polymer filled trenches to singulate the completed components from one another. The grooves have a width that is less than the width of the polymer filled trenches, such that the edge polymer layers which comprise portions of the polymer filled trenches, remain on the four edges of the dice. The singulated component is encapsulated on six sides (i.e., circuit side, back side, four edges) by the circuit side polymer layer, the back side polymer layer and by edge polymer layers on the four edges. Prior to the singulation step, the components can be tested and burned-in while they remain on the substrate. In addition, the components are electrically isolated on the substrate, which is a particular advantage for burn-in testing.
A second embodiment component includes conductive vias in the thinned substrate, which electrically connect the die contacts to terminal contacts formed on the back side polymer layer. The terminal contacts can comprise conductive bumps or balls, or alternately planar pads configured as an edge connector. In addition, the conductive vias can be used to electrically connect terminal contacts on both sides of the component for stacking multiple components, and for facilitating testing of the components.
A third embodiment component is singulated by etching the substrate. The component includes a circuit side polymer layer, contact bumps embedded in the polymer layer, and terminal contacts on the contact bumps. In addition, the component includes a thin sealing coat, such as vapor deposited parylene, on five surfaces.
A fourth embodiment component includes a circuit side polymer layer, contact bumps embedded in the polymer layer, and terminal contacts on the contact bumps. In addition, the component includes a thinned semiconductor substrate having a back side coat tape for protecting and laser marking the substrate. Alternately, a heat sink can be attached directly to the back side of the thinned semiconductor substrate.
A fifth embodiment component includes a circuit side polymer layer, which comprises two separate polymer materials, including an imageable polymer material (e.g., a photopolymer), and a second polymer material having tailored electrical characteristics. The imageable polymer material also covers the edges of the component, and is formed into dams having a criss-cross pattern configured to retain the tailored polymer material. Depending on the material, the imageable polymer material can be blanket deposited, exposed, and then developed, using a conventional UV photolithography system, or alternately a laser stereo lithography system.
A sixth embodiment pin grid array component includes conductive vias in a thinned die having conductive members in electrical communication with die contacts. In addition, a semiconductor substrate of the thinned die has been planarized and etched to expose portions of the conductive members which form terminal contact pins for the component.
A seventh embodiment component includes a thinned die having conductive vias formed by laser machining and etching openings in a thinned semiconductor substrate. In addition, the thinned substrate can include doped contacts, having a different conductivity type than the bulk of the substrate. The thinned substrate can be etched very thin, such that a very thin component is provided.
An eighth embodiment ball grid array component includes conductive vias in a thinned die having conductive members in electrical communication with die contacts. In addition, a semiconductor substrate of the thinned die has been planarized and etched to expose portions of the conductive members which are used to form a pattern of redistribution conductors. Further, balls are bonded to the redistribution conductors to form terminal contacts in a ball grid array.
In each embodiment, the components can be used to construct systems such as MCM packages, multi chip modules and circuit boards. In addition, prior to assembling the systems, the components can be tested at the wafer level, such that each of the components can be certified as a known good component (KGC) prior to incorporation into the system.
BRIEF DESCRIPTION OF THE DRAWINGS
As used herein, the term “semiconductor component” refers to an electronic element that includes a semiconductor die. Exemplary semiconductor components include semiconductor packages, semiconductor dice, BGA devices, and DDC devices.
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In the illustrative embodiment, the dice 10 are formed on the wafer 12 with integrated circuits and semiconductor devices using techniques that are well known in the art. As also shown in
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Each die 10 also includes a pattern of die contacts 18 formed on the circuit side 20, in a dense area array, in electrical communication with the integrated circuits thereon. As shown in
The die contacts 18 can be formed on the circuit side 20 of the wafer 12 using known techniques, such as deposition and patterning of one or more redistribution layers in electrical communication with the bond pads (not shown) for the dice 10. One such technique is described in U.S. Pat. No. 5,851,911 to Farnworth, which is incorporated herein by reference. Alternately, the die contacts 18 can comprise the bond pads of the dice 10. In addition, the die contacts 18 can be electrically insulated from the semiconductor substrate 14 by insulating layers (not shown), formed of suitable materials such as BPSG, SiO2 or polyimide.
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As another alternative, the trenches 28 can be formed in the substrate 14 by laser machining the wafer 12 using a laser machining system. A suitable laser system for laser machining the trenches 28 is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700.
The trenches 28 can have a criss-cross pattern as shown, similar to a tic tac toe board, such that each trench is parallel to some trenches and perpendicular to other trenches. As such, the trenches 28 substantially surround each die 10, defining the four edges 30 of each die 10, and the rectangular polygonal peripheral shape of each die 10 as well.
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In the illustrative embodiment, the wafer 12 has a thickness Tw of about 28 mils (725 μm), and the trenches 28 have a depth d of about 10 mils (254 μm). In addition to the depth d, the trenches 28 have a width W, which in the illustrative embodiment is about 4 mils (101.6 μm). The scribing step can be performed using a dicing saw having saw blades with the width W, which are configured to penetrate the circuit side 20 of the wafer 12 to the depth d. Alternately, with an etching process for forming the trenches 28, openings in an etch mask determine the width W, and control of the etch process end points the trenches 28 with the depth d.
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The good die dam 32 can comprise a polymer material deposited on the wafer 12 using a suitable deposition process such as deposition through a nozzle, screen printing, stenciling or stereographic lithography. In the illustrative embodiment, the good die dam 32 is deposited on the wafer 12 using a nozzle deposition apparatus. The nozzle deposition apparatus is under computer control, and is configured to move in x and y directions across the wafer 12, and in z directions towards and away from the wafer 12. One suitable nozzle deposition apparatus, also known as a material dispensing system, is manufactured by Asymtek of Carlsbad, Calif.
The good die dam 32 can comprise a curable polymer material having a relatively high viscosity, such that the polymer material sticks to the wafer 12, and stays in a desired location. Suitable curable polymers for the good die dam 32 include silicones, polyimides and epoxies. In addition, these polymer materials can include fillers such as silicates configured to reduce the coefficient of thermal expansion (CTE) and adjust the viscosity of the polymer material. One suitable curable polymer is manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL” FP4451. The good die dam 32 can also comprise a polymer such as parylene, deposited using a vapor deposition process to be hereinafter described.
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In the illustrative embodiment, the support dam 34 comprises a same material as the good die dam 32, and is deposited using the previously described nozzle deposition apparatus. Alternately, the support dam 34 can comprise one or more pre-formed polymer elements attached to the wafer 12. In this case, the support dam 32 can have a serpentine-shape, a donut shape, or can merely be a segment or ribbon of material, that supports a particular area on the wafer 12.
Following deposition, both the good die dam 32 and the support dam 34 can be cured to harden the polymer material. For example, curing can be performed by placing the wafer 12 in an oven at a temperature of about 90′ to 165° C. for about 30 to 60 minutes.
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The circuit side polymer layer 36 can comprise a curable polymer such as a silicone, a polyimide or an epoxy. In addition, these materials can include fillers, such as silicates, configured to reduce the coefficient of thermal expansion (CTE) and adjust the viscosity of the polymer material. One suitable curable polymer material is manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL” FP4450.
Following deposition, the circuit side polymer layer 36 can be cured to harden the polymer material. For example, curing can be performed by placement of the wafer 12 in an oven at a temperature of about 90° to 165° C. for about 30 to 60 minutes.
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The circuit side planarization step can be performed using a mechanical planarization apparatus (e.g., a grinder). One suitable mechanical planarization apparatus is manufactured by Okamoto, and is designated a model no. VG502.
The circuit side planarization step can also be performed using a chemical mechanical planarization (CMP) apparatus. A suitable CMP apparatus is commercially available from a manufacturer such as Westech, SEZ, Plasma Polishing Systems, or TRUSI. The circuit side planarization step can also be performed using an etch back process, such as a wet etch process, a dry etch process or a plasma etching process.
In the illustrative embodiment, the circuit side planarization step can be performed such that the thickness of the circuit side polymer layer 36 is reduced by an amount sufficient to expose and planarize the surfaces of the contact bumps 24. In the illustrative embodiment, the planarized circuit side polymer layer 24P has a thickness Tcs of about 12 mils (304.8 μm). As another alternative the circuit side planarization step need not also planarize the contact bumps 24. For example, the contact bumps 24 can remain generally concave in shape, and can protrude past the surface of the planarized circuit side polymer layer 36P.
Rather than the above nozzle deposition and planarizing process, the circuit side polymer layer 36 can be formed by another suitable deposition process, such as an injection molding process, a transfer molding process, a stenciling process, a screen printing process, a spin resist process, a dry film process, or a stereographic lithographic process. As another alternative, the circuit side polymer layer 36 can comprise a polymer such as parylene, deposited using a vapor deposition process to be hereinafter described. As yet another alternative, the circuit side polymer layer 36 can comprise a wafer level underfill material to be hereinafter described.
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The amount of semiconductor material removed by the back side thinning step is dependent on the thickness Tw of the wafer 12, and on the depth d of the trenches 28. For example, if the thickness Tw of the wafer 12 is about 28 mils (725 μm), and the depth d of the trenches is about 10 mils (25.4 μm), then at least 18 mils (457.2 μm) of semiconductor material must be removed to expose the polymer filled trenches 28P. In the illustrative embodiment about 22 mils (558.8 μm) of semiconductor material is removed, such that the thickness Ts (
The thickness Ts of the thinned substrate 14T can be related to the original thickness Tw of the wafer 12 by the formula Ts=Tw−y, where y represents the amount of material removed by the back side thinning step.
Optionally, a chemical polishing step (CMP) can be performed to remove grind damage to the thinned semiconductor substrate 14T. Polishing can be performed using a commercial CMP apparatus from a manufacturer such as Westech, SEZ, Plasma Polishing Systems or TRUSI. As another option an etching step can be performed using an etchant such as TMAH, to remove grind damage to the thinned semiconductor substrate 14T.
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Alternately, the planarized back side polymer layer 38P can be formed by attaching or laminating a polymer film, such as a polyimide or epoxy tape, having an adhesive surface and a desired thickness to the thinned back side 22T. In this case the back side planarizing step can be eliminated. One suitable polymer film is a polymer tape manufactured by Lintec, and designated #LE 5950. As another alternative, the back side polymer layer 38P can be formed by an injection molding process, a transfer molding process, a spin resist process, a dry film process, a stereo lithographic process, or any other suitable process.
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Following forming of the planarized back side polymer layer 38P, pin one indicators (not shown) can be laser printed on the back side polymer layer 38P, and also on the circuit side polymer layer 36P, as required. This printing step can be performed using a conventional laser printing apparatus. Preferably the planarized back side polymer layer 38P is opaque to the wavelength of the laser being employed during the printing step.
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The terminal contacts 42 (and the contact bumps 24 as well) can also be formed by electrolytic deposition, by electroless deposition, or by bonding pre-fabricated balls to the planarized contact bumps 24P. A ball bumper can also be employed to bond pre-fabricated balls. A suitable ball bumper is manufactured by Pac Tech Packaging Technologies of Falkensee, Germany. The terminal contacts 42 can also be formed using a conventional wire bonder apparatus adapted to form a ball bond, and then to sever the attached wire.
Because the terminal contacts 42 are in effect “stacked” on the planarized contact bumps 24P, a relatively large spacing distance is provided for flip chip mounting, and the reliability of the component 16 is increased. In addition, the offset, or spacing, provided by the planarized contact bumps 24P and the terminal contacts 42, may allow the component 16 to be flip chip mounted without requiring an underfill for some applications.
Optionally, the terminal contacts 42 can be rigidified with a polymer support layer as described in U.S. Pat. No. 6,180,504 B1 to Farnworth et al., which is incorporated herein by reference. As another option, the terminal contacts 42 can be formed in a standardized grid array as described in U.S. Pat. No. 6,169,329 to Farnworth et al., which is incorporated herein by reference. As yet another option, the terminal contacts 42 can be formed as described in U.S. Pat. No. 6,281,131 B1 to Gilton et al., which is incorporated herein by reference.
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The singulating step can be performed using a dicing saw having saw blades with the width Wg. Alternately the singulating step can be performed using another singulation method, such as cutting with a laser or a water jet or be etching the substrate 14T with a suitable wet or dry etchant. By way of example, if the width of the trenches 28 is about 4 mils (101.6 μm), and the width Wg of the grooves 44 is about 2 mils (50.8 μm), the edge polymer layers 40 will have a thickness of about 1 mil (25.4 μm).
Prior to the singulating step, the components 16 on the wafer 12 can be tested and burned-in using a wafer level test process. Suitable wafer level burn-in test procedures are described in U.S. Pat. No. 6,233,185 B1 to Beffa et al., which is incorporated herein by reference. In addition, a wafer level burn-in apparatus is described in U.S. Pat. No. 6,087,845 to Wood et al., which is incorporated herein by reference.
Because the components 16 on the wafer 12 are electrically isolated by the polymer filled trenches 28P and the back side planarization step, burn-in testing is improved, as defective components 16 remain electrically isolated, and do not adversely affect the burn-in test procedure. In addition, the active circuitry on the thinned semiconductor die 10T is protected from damage during test and burn-in. Further, the components 16 have a physical robustness that facilitates testing and handling of the components 16 by the manufacturer and the end user.
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In addition, the component 16 includes the planarized circuit side polymer layer 36P which covers the circuit side 20 of the thinned die 14T, and encapsulates the planarized contact bumps 24P. The planarized contact bumps 24P are thus supported and rigidified by the planarized circuit side polymer layer 36P. In addition, the planarized contact bumps 24P function as interconnects between the die contacts 18 and the terminal contacts 42. Still further, the planarized circuit side polymer layer 36P has been mechanically planarized to a precise thickness with a planar surface.
The component 16 also includes the terminal contacts 42 bonded to the planarized contact bumps 24P. In addition, the terminal contacts 42 are arranged in a dense area array such as a ball grid array (BGA), such that a high input/output capability is provided for the component 16.
The component 16 also includes the planarized back side polymer layer 38P which covers the thinned back side 22T of the thinned die 10T. Again, the planarized back side polymer layer 38P has been mechanically planarized to a precise thickness with a planar surface.
In addition, the component 16 includes four edge polymer layers 40 which cover and rigidify the four edges 30 of the thinned die 10T. The component 16 is thus protected on six sides by polymer layers 36P, 38P and 40. In the illustrative embodiment the planarized circuit side polymer layer 36P and the edge polymer layers 40 are a continuous layer of material, and the planarized back side polymer layer 38P is a separate layer of material. In addition, the edge polymer layers 40 are formed by portions of the polymer filled trenches 28P (
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The terminal contacts 42EC can comprise planar, polygonal pads formed of a relatively hard metal such as copper or nickel. In addition, conductors 45 on the circuit side 20 establish electrical paths between the terminal contacts 42EC and the die contacts 18. The component 16EC can be fabricated substantially as shown in
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Specifically, the polymer film comprises a thermoset polymer film having a Young's modulus of about 4G Pascal, and a coefficient of thermal expansion (CTE) of about 33 parts per million per ° C. In addition, the polymer film preferably cures and planarizes at a temperature and in a time period that are similar to the temperature and time period for a solder reflow process for bonding solder bumps to semiconductor components (e.g., about 200-250° C. for about several minutes). Further, the polymer film preferably has low alpha emission characteristics.
One suitable thermoset polymer film is a wafer level underfill film manufactured by 3M corporation. In addition, this polymer film is self planarizing, such that a mechanical planarization step as previously described is not necessary.
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Polymer filled trenches 28UF are also formed during formation of the circuit side polymer layer 36UF, substantially as previously described for polymer filled trenches 28P (
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One method for forming the vias 74A for the conductive vias 68A combines laser machining and etching processes. Initially, openings 82A are formed in the die contacts 18A using an etch mask (not shown) and an etching process. Depending on the material of the die contacts 18A, a wet etchant can be used to etch the die contacts 18A. For example, for die contacts 18A made of aluminum, one suitable wet etchant is H3PO4. The openings 82A in the die contacts 18A are generally circular, and are smaller in diameter than the width of the die contacts 18A. The die contacts 18A thus have metal around their peripheries, but no metal in the center. In the illustrative embodiment, the openings 82A have a diameter that is about one half the width of the die contacts 18A. In addition, the openings 82A surround a portion of the substrate 14A, such that the die contacts 18A and the openings 82A form targets, or bullseyes, for a subsequent laser drilling step in which a laser beam is directed at the openings 82A and through the substrate 14A. The laser beam initially pierces the substrate 14A on the portions of the substrate 14A surrounded by the openings 82A.
The laser drilling step forms lasered openings through the substrate 14A, which do not touch the metal of the die contacts 18A, as they are located in the middle of the openings 82A in the die contacts 18A. For example, the lasered openings can have diameters that are about one half the diameter of the openings 82A. The laser beam thus initially contacts and pierces the substrate 14A without having to contact and pierce the metal that forms the die contacts 18A. This helps to prevent shorting between the conductive via and the die contacts 18A.
Following the laser drilling step, a cleaning step can be performed in which the lasered openings are cleaned using a suitable wet or dry etchant to form the vias 74A for the conductive vias 68A. One suitable wet etchant for cleaning the lasered openings with the substrate 14A comprising silicon is tetramethylammoniumhydroxide (TMAH). By way of example, the diameters of the vias 74A can be from 10 μm to 2 mils or greater.
A suitable laser system for performing the laser drilling step is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700. A representative laser fluence for forming the vias 74A through a silicon substrate having a thickness of about 28 mils, is from 2 to 10 watts/per opening at a pulse duration of 20-25 ns, and at a repetition rate of up to several thousand per second. The wavelength of the laser beam can be a standard UV wavelength (e.g., 355 nm).
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Alternately, the insulating layers 78A can comprise an electrically insulating material, such as an oxide or a nitride, deposited using a deposition process such as CVD, or a polymer material deposited using a suitable deposition process such as screen printing. In this case, if the insulating material completely fills the vias 74A, a subsequent laser drilling step, substantially as previously described, may be required to re-open the vias 74A.
Following formation of the insulating layers 78A, the conductive members 76A can be formed within the vias 74A. The conductive members 76A can be plugs that completely fill the vias 74A, or alternately, can be layers that cover just the inside surfaces or sidewalls of the vias 74A. The conductive members 76A can comprise a highly conductive metal, such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum, tin, zinc and alloys of these metals. The above metals can be deposited within the openings 76A using a deposition process, such as electroless deposition, CVD, or electrolytic deposition. Alternately a solder metal can be screen printed in the vias 74A and drawn into the vias 74A with capillary action. A solder metal can also be drawn into the vias 74A using a vacuum system and a hot solder wave.
Rather than being a metal, the conductive members 76A can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. Suitable conductive polymers are available from A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. A conductive polymer can be deposited within the vias 74A, as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into the vias 74A.
The conductive vias 68A can also be formed using the laser machining processes disclosed in U.S. Pat. No. 6,107,109 to Akram et al, U.S. Pat. No. 6,114,240 to Akram et al., and U.S. Pat. No. 6,294,837 B1 to Akram et al., all of which are incorporated herein by reference. Rather than a laser machining processes, the conductive vias 68A can be formed by etching the vias 74A using an etch mask and a suitable etchant. As another alternative, the conductive vias 68A can be formed as described in U.S. Pat. No. 6,313,531 B1 to Geusic et al., which is incorporated herein by reference.
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The planarized back side polymer layer 38AP can also comprise a photoimageable polymer material, such as a thick film resist. One such resist comprises a negative tone resist, which is blanket deposited to a desired thickness, exposed, developed and then cured. A suitable resist formulation is sold by Shell Chemical under the trademark “EPON RESIN SU-8”. Such a resist can be deposited to a thickness of from about 0.5-20 mils and then built up using successive layers. A conventional resist coating apparatus, such as a spin coater, or a meniscus coater can be used to deposit the resist. The deposited resist can then be “prebaked” at about 95° C. for about 15 minutes and exposed in a desired pattern using a conventional UV aligner with a dose of about 165 mJ/cm2. Developing can be accomplished with a solution of PGMEA (propylenglycol-monomethylether-acetate). This can be followed by a hard bake at about 200° C. for about 30 minutes.
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In addition, the component 16A includes the planarized circuit side polymer layer 36AP, which covers the circuit side 20A of the thinned die 14AT, and encapsulates the planarized contact bumps 24AP. The component 16A also includes the terminal contacts 42A bonded to the pads 85A in electrical communication with the conductive vias 68A and 70A. The component 16A also includes the planarized back side polymer layer 38AP which covers the thinned back side 22AT of the thinned die 10AT. In addition, the component 16A includes four edge polymer layers 40A which cover the four edges 30A of the thinned die 10AT. The component is thus encapsulated on all six surfaces (6X).
The component 16A can be used to construct systems such as systems in a package and module systems to be hereinafter described. The component 16A can also be used to construct the stacked system 83 shown in
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The circuit side polymer layer 36E can comprise a curable polymer material, such as a silicone, a polyimide or an epoxy, as previously described for the circuit side polymer layer 36 of
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With the dicing tape 26E thereon, the wafer 12E is submerged in a wet etchant, such as a solution of KOH, configured to anisotropically etch the semiconductor substrate 14E. For performing the etch step, the etchant can be contained in a dip tank which circulates the wet etchant around a batch of wafers 12E held in a boat. Such an etch process is described in U.S. Pat. No. 5,904,546 to Wood et al., which is incorporated herein by reference.
During the etch step, the wafer 12E is etched from both the back side 22E and the circuit side 20E at the same time. In particular, grooves 92E are etched in the back side 22E of the wafer 12E in a pattern corresponding to the pattern of the slots 86E in the etch mask 84E. In addition, grooves 94E are etched in the front side 20E of the wafer 12E in a pattern corresponding to the pattern of the slots 88E in the planarized circuit side polymer layer 36EP. The grooves 92E, 94E in the wafer 12E are sloped at an angle of approximately 54° with the horizontal, due to the different etch rates of monocrystalline silicon along the different crystal orientations.
The etch step is performed for a time period sufficient to singulate the dice 10E from the wafer 12E and from one another. In addition, the etch step can be followed by a second etch step in which a less aggressive etchant, such as TMAH, is used to smooth and round the etched surfaces. Following the etch step, the etch mask 84E can be stripped using a suitable stripper. For example, if desired, a solution of H3PO4 can be used to strip a silicon nitride etch mask 84E.
Also following the etch step, a sealing step is performed. During the sealing step, the dicing tape 26E remains on the circuit side 20E, holding the separated dice 10E and covering the planarized contact bumps 24EP. The sealing step can be performed by coating the wafer 12E in with a sealing chemical that coats the exposed surfaces of the dice 10E, and then hardens to form a sealing layer 90E (
One suitable chemical for forming the sealing layer 90E comprises parylene. Parylene polymers can be deposited from the vapor phase by a process similar to vacuum metallization at pressures of about 0.1 torr. Suitable polymers include parylene C, parylene N, and parylene D. Parylene is available from Advanced Coating of Tempe, Ariz.
One suitable deposition apparatus for depositing the parylene comprises a portable parylene deposition system, designated a model PDS 2010 LABCOATER 2, manufactured by Specialty Coating Systems, of Indianapolis, Ind.
The parylene uniformly coats all exposed surfaces of the wafer 12E to form the sealing layer 90E. A thickness range for the sealing layer 90E can be from 0.10 to 76 μm or greater. Although the edges of the singulated dice 10E are faceted by the etching step, the sealing layer 90E essentially seals the five major surfaces of the dice 10E (back side and four edges). The completed components 16E are thus hermetically sealed on five surfaces (5X).
Following the sealing step, the dicing tape 26E is removed, and the terminal contacts 42E are formed on the planarized contact bumps 24EP, substantially as previously described for terminal contacts 42 in
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Although the component 16E is illustrated as having terminal contacts 42E on only the circuit side 20E, it is to be understood that the component 16E can be fabricated with conductive vias substantially as previously described for conductive vias 68A. Accordingly, the component 16E can be configured substantially similar to the component 16A of
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Because the components 16-1X have been tested and burned-in they can be used without further testing to construct packages in a system, module systems and other systems as well.
The components 16-1X can also be fabricated without the back side coat tape 100-1X but with a heat sink attached directly to the thinned back side 22T-1X. As shown in
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Alternately the imageable polymer material 106D can comprise a laser imageable material, such as a Cibatool SL 5530 resin manufactured by Ciba Specialty Chemicals Corporation. In this case, the imageable polymer material 106D can be patterned and developed using a laser beam to provide the exposure energy 104D. A stereo lithography system for performing the process is available from 3D Systems, Inc. of Valencia, Calif. In addition, a stereographic lithographic process (3-D) is described in U.S. application Ser. No. 09/259,142, to Farnworth et al. filed on Feb. 26, 1999, and in U.S. application Ser. No. 09/652,340, to Farnworth et al. filed on Aug. 31, 2000, both of which are incorporated herein by reference.
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The polymer material 110D can comprise a curable polymer such as a silicone, polyimide or epoxy. In addition, these materials can include fillers such as silicates configured to adjust the coefficient of thermal expansion (CTE) and the viscosity of the polymer material. One suitable curable polymer material is manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL” FP4450.
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One advantage of the system in a package (SIP) 48, and the multi chip module system 50, is that the components 16G have optionally been tested and burned-in at the wafer level. If wafer level burn-in has been performed, the components have been certified as known good components (KGC).
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Each die 10PGA also includes a pattern of die contacts 18PGA in the form of bond pads on the circuit side 20PGA, in electrical communication with the integrated circuits thereon. As shown in
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In addition, the component 16PGA includes the circuit side polymer layer 36PGA, which covers the circuit side 20PGA of the thinned die 14T-PGA, and encapsulates the planarized contact bumps 24PGA. The component 16PGA also includes the terminal contacts 42PGA in electrical communication with the conductive vias 68PGA, and configured as pins in a micro pin grid array (MPGA). The component 16PGA also includes the back side polymer layer 38PGA which covers the thinned back side 22T-PGA of the thinned die 10T-PGA. In addition, the component 16PGA includes four edge polymer layers 40PGA which cover the four edges 30PGA of the thinned die 10T-PGA. The component 16PGA is thus encapsulated on all six surfaces (6X). In addition, the component 16PGA is particularly suited to systems that employ pin type sockets.
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In addition, the component 16Z includes the circuit side polymer layer 36Z, which covers the circuit side 20Z of the thinned die 14Z, and encapsulates the planarized contact bumps 24Z. The component 16Z also includes the terminal contacts 42Z in electrical communication with the conductive vias 68Z, and the back side polymer layer 38Z which covers the thinned back side 22Z of the thinned die 10Z. In addition, the component 16Z includes four edge polymer layers 40Z which cover the four edges 30Z of the thinned die 10Z. The component 16Z is thus encapsulated on all six surfaces (6X).
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In addition, a back side insulating layer 38BGA can be formed substantially as previously described for any of the previous embodiment. For example, the insulating layer 38BGA can comprise a very thin layer of parylene deposited using the previously described vapor deposition method.
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In addition, the component 16BGA includes the circuit side polymer layer 36BGA, which covers the circuit side 20BGA of the thinned die 14T-BGA, and encapsulates the planarized contact bumps 24BGA. The component 16BGA also includes the terminal contacts 42BGA in electrical communication with the conductive vias 68BGA, and configured as a ball grid array (BGA) or a micro pin grid array (MPBGA). The component 16BGA also includes the back side polymer layer 38BGA which covers the thinned back side 22T-BGA of the thinned die 10T-BGA. In addition, the component 16BGA includes four edge polymer layers 40BGA which cover the four edges 30BGA of the thinned die 10T-BGA. The component 16BGA is thus encapsulated on all six surfaces (6X).
Thus the invention provides improved encapsulated semiconductor components, methods for fabricating the component, and systems incorporating the component. While the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.
Claims
1-152. (canceled)
153. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a thinned back side and a plurality of peripheral edges;
- a first polymer layer covering the circuit side and the edges; and
- a second polymer layer covering the back side.
154. The semiconductor component of claim 153 further comprising a plurality of die contacts on the die, and a plurality of contact bumps on the die contacts embedded in the first polymer layer.
155. The semiconductor component of claim 154 further comprising a plurality of terminal contacts on the contact bumps.
156. The semiconductor component of claim 154 wherein the terminal contacts comprise bumps or balls in a grid array, or planar pads configured as an edge connector.
157. The semiconductor component of claim 154 wherein the second polymer layer is opaque to radiation at a selected wavelength.
158. The semiconductor component of claim 154 wherein the second polymer layer comprises a wafer level underfill tape.
159. The semiconductor component of claim 154 wherein the second polymer layer comprises parylene.
160. The semiconductor component of claim 154 wherein the second polymer layer comprises a photoresist.
161. The semiconductor component of claim 154 wherein the second polymer layer comprises a tape.
162. The semiconductor component of claim 154 wherein the second polymer layer comprises a stereographic imageable resist.
163. The method of claim 154 further comprising etching the substrate following the thinning step such that the substrate is recessed with respect to the portions of the polymer filled trenches.
164. The method of claim 163 wherein a thickness of the substrate following the etching step is about 10 μm to 250 μm.
165. The semiconductor component of claim 154 further comprising a polymer tape attached to the thinned back side which is opaque to radiation at a selected wavelength, and a laser marking on the polymer tape.
166. The semiconductor component of claim 154 further comprising a conductive via in the thinned substrate.
167. The semiconductor component of claim 166 wherein the conductive via comprises a conductive member exposed with respect to the substrate to provide a pin terminal contact.
168. The semiconductor component of claim 166 wherein the conductive via comprises a conductive member, a conductor on the back side and a terminal contact on the back side in electrical communication with the conductivity region.
169. The semiconductor component of claim 166 wherein the conductive via comprises a reverse bias junction.
170. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a back side, four peripheral edges, and a plurality of die contacts;
- a plurality of contact bumps on the die contacts;
- a first polymer layer covering the circuit side, the contact bumps and the peripheral edges;
- a second polymer layer covering the back side; and
- a plurality of terminal contacts on the contact bumps.
171. The semiconductor component of claim 170 wherein the contact bumps and the first polymer layer are planarized to a same surface.
172. The semiconductor component of claim 170 wherein the contact bumps comprise metal bumps.
173. The semiconductor component of claim 170 wherein the terminal contacts comprise conductive bumps or balls.
174. The semiconductor component of claim 170 wherein the first polymer layer has a planarized first surface.
175. The semiconductor component of claim 170 wherein the second polymer layer has a planarized second surface.
176. The semiconductor component of claim 170 further comprising a plurality of conductive vias in electrical communication with the die contacts and with the terminal contacts.
177. The semiconductor component of claim 176 further comprising a plurality of second die contacts on the second polymer layer in electrical communication with the conductive vias.
178. The semiconductor component of claim 170 wherein the second polymer layer comprises a photopolymer.
179. The semiconductor component of claim 170 wherein the second polymer layer comprises a wafer level underfill.
180. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a back side and four peripheral edges;
- a circuit side polymer layer covering the circuit side;
- a plurality of edge polymer layers covering the four peripheral edges, the edge polymer layers and the circuit side polymer layer comprising a continuous layer of material, the edge polymer layers comprising portions of polymer filled trenches; and
- a back side polymer layer covering the back side.
181. The semiconductor component of claim 180 further comprising a plurality of die contacts on the die, and a plurality of contact bumps on the die contacts embedded in the circuit side polymer layer.
182. The semiconductor component of claim 180 further comprising a plurality of die contacts on the die, and a plurality of planarized contact bumps on the die contacts embedded in the circuit side polymer layer and planarized to a surface thereof.
183. The semiconductor component of claim 180 further comprising a plurality of terminal contacts on the contact bumps.
184. The semiconductor component of claim 180 further comprising a plurality of conductive vias through the die
185. The semiconductor component of claim 180 further comprising a plurality of conductive vias through the die including exposed portions configured as pins.
186. The semiconductor component of claim 180 further comprising a plurality of conductive vias through the die including tip portions, a plurality of conductors on the back side in electrical communication with the conductors, and a plurality of terminal contacts on the back side in electrical communication with the tip portions.
187. The semiconductor component of claim 180 wherein the back side polymer layer is opaque to radiation at a selected wave length.
188. The semiconductor component of claim 180 wherein the back side polymer layer comprises a wafer level underfill.
189. A semiconductor component comprising:
- a semiconductor wafer having a circuit side and a back side, the wafer comprising a thinned substrate and a plurality of semiconductor dice on the thinned substrate separated by streets;
- a plurality of polymer filled trenches in the thinned substrate in the streets;
- a planarized circuit side polymer layer on the circuit side; and
- a planarized back side polymer layer in the back side.
190. The semiconductor component of claim 189 further comprising a plurality of die contacts on the dice, and a plurality of contact bumps on the die contacts embedded in the planarized circuit side polymer layer.
191. The semiconductor component of claim 190 further comprising a plurality of terminal contacts on the contact bumps.
192. The semiconductor component of claim 191 further comprising a plurality of conductive vias in the substrate in electrical communication with the die contacts and with the terminal contacts.
193. The semiconductor component of claim 191 wherein the terminal contacts comprise bumps or balls in a grid array.
194. The semiconductor component of claim 191 wherein the terminal contacts are configured as an edge connector.
195. The semiconductor component of claim 191 further comprising a plurality of second terminal contacts on planarized back side polymer layer in electrical communication with the conductive vias.
196. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a back side, four peripheral edges, and a plurality of die contacts on the circuit side;
- a first polymer layer covering the circuit side and the peripheral edges;
- a plurality of conductive vias in the die in electrical communication with the die contacts;
- a second polymer layer covering the back side;
- and a plurality of terminal contacts in electrical communication with the conductive vias and the die contacts.
197. The semiconductor component of claim 196 wherein the terminal contacts are on the circuit side.
198. The semiconductor component of claim 196 wherein the terminal contacts are on the back side.
199. The semiconductor component of claim 196 wherein the terminal contacts are on both the circuit side and the back side.
200. The semiconductor component of claim 196 wherein the terminal contacts are offset from the conductive vias.
201. The semiconductor component of claim 196 wherein each conductive via comprise a reverse bias junction.
202. The semiconductor component of claim 196 wherein the terminal contacts are configured as an edge connector.
203. The semiconductor component of claim 196 wherein the terminal contacts are bonded to contact bumps on the die contacts.
204. The semiconductor component of claim 196 wherein the terminal contacts are bonded to planarized contact bumps on the die contacts planarized to a surface of the first polymer layer.
205. The semiconductor component of claim 196 wherein the conductive vias comprise openings in the die, insulating layers on the openings, and a conductive material in the openings.
206. The semiconductor component of claim 196 wherein the conductive vias comprise portions of the die implanted with a dopant.
207. The semiconductor component of claim 196 wherein the terminal contacts comprise portions of the conductive vias configured as pin contacts.
208. The semiconductor component of claim 196 wherein the terminal contacts comprise balls or bumps in an area array.
209. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side and a thinned back side;
- a polymer layer covering the circuit side; and
- a heat sink attached to the thinned back side.
210. The semiconductor component of claim 209 further comprising a thermally conductive adhesive attaching the heat sink to the thinned back side.
211. The semiconductor component of claim 209 wherein the die comprise a plurality of edges and the polymer layer covers the edges.
212. The semiconductor component of claim 209 wherein the die comprises a plurality of die contacts on the circuit side, contact bumps on the die contact and terminal contacts on the contact bumps.
213. The semiconductor component of claim 209 wherein the die comprises a plurality of die contacts on the circuit side, planarized contact bumps on the die contact and terminal contacts on the planarized contact bumps.
214. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side and a thinned back side;
- a polymer layer covering the circuit side;
- a polymer tape attached to the thinned back side; and
- a marking in the polymer tape.
215. The semiconductor component of claim 214 wherein the marking comprises a laser marking and the polymer tape is opaque to radiation of a selected wave length.
216. The semiconductor component of claim 214 wherein the die comprise a plurality of edges and the polymer layer covers the edges.
217. The semiconductor component of claim 214 wherein the die comprises a plurality of die contacts on the circuit side, contact bumps on the die contacts, and terminal contacts on the contact bumps.
218. The semiconductor component of claim 214 wherein the die comprises a plurality of die contacts on the circuit side, planarized contact bumps on the die contacts, and terminal contacts on the planarized contact bumps.
219. The semiconductor component of claim 214 wherein the polymer tape comprises a wafer level underfill.
220. A semiconductor component comprising:
- a semiconductor die having a circuit side, a back side, four peripheral edges, and an array of die contacts on the circuit side;
- a polymer layer covering the circuit side;
- a protective coating covering the edges and the back side; and
- a plurality of terminal contacts on the die contacts.
221. The semiconductor component of claim 220 further comprising a plurality of contact bumps on the die contacts.
222. The semiconductor component of claim 220 further comprising a plurality of planarized contact bumps on the die contacts planarized to a surface of the polymer layer.
223. The semiconductor component of claim 220 wherein the protective coating comprises parylene.
224. The semiconductor component of claim 220 wherein the terminal contacts comprise bumps or balls in a grid array.
225. The semiconductor component of claim 220 wherein the terminal contacts are configured as an edge connector.
226. The semiconductor component of claim 220 wherein the peripheral edges comprise etched surfaces.
227. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a back side, four peripheral edges, and a plurality of die contacts;
- a first polymer layer covering the circuit side comprising a first polymer material; and
- a plurality of second polymer layers covering the peripheral edges comprising a second polymer material.
228. The semiconductor component of claim 227 further comprising a plurality of contact bumps on the die contacts embedded in the first polymer layers and a plurality of terminal contacts on the contact bumps.
229. The semiconductor component of claim 228 wherein the contact bumps and the first polymer layer are planarized to a same surface.
230. The semiconductor component of claim 228 wherein the contact bumps comprise conductive bumps or balls.
231. The semiconductor component of claim 228 wherein the second polymer layers comprise a photoimageable resist.
232. The semiconductor component of claim 228 wherein the second polymer layer comprise a stereo lithographic imageable material.
233. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a back side, and a plurality of die contacts on the circuit side;
- a plurality of conductive vias in the die in electrical communication with the die contacts;
- and a plurality of terminal contacts in electrical communication with the conductive vias and the die contacts comprising pin contacts.
234. The semiconductor component of claim 233 wherein the pin contacts comprise conductive portions of the conductive vias.
235. The semiconductor component of claim 233 wherein the pin contacts comprise a pin grid array.
236. The semiconductor component of claim 233 wherein each conductive via comprises a reverse junction bias.
237. The semiconductor component of claim 233 further comprising a second polymer layer covering the back side.
238. The semiconductor component of claim 233 wherein the thinned die has a thickness of from about 10 μm to 250 μm.
239. The semiconductor component of claim 233 further comprising a first polymer layer covering at least the circuit side.
240. The semiconductor component of claim 239 wherein the first polymer layer covers edges of the die.
241. The semiconductor component of claim 239 further comprising a second polymer layer covering the back side.
242. A semiconductor component comprising:
- a thinned semiconductor die having a circuit side, a back side, and a plurality of die contacts on the circuit side;
- a plurality of conductive vias in the die in electrical communication with the die contacts;
- and a plurality of terminal contacts in electrical communication with the conductive vias and the die contacts comprising tip portions projecting from the thinned semiconductor die;
- a plurality of conductors in electrical communication with the tip portions; and
- a plurality of terminal contacts in electrical communication with the conductors.
243. The semiconductor component of claim 242 wherein the tip portions comprise a conductive material.
244. The semiconductor component of claim 242 wherein the terminal contacts comprise ball or bumps in a grid array.
245. The semiconductor component of claim 242 wherein the conductive vias comprise reverse bias junctions.
246. The semiconductor component of claim 242 further comprising a first polymer layer covering at least the circuit side.
247. The semiconductor component of claim 246 wherein the first polymer layer covers edges of the die.
248. The semiconductor component of claim 246 further comprising a second polymer layer covering the back side.
249. A system comprising:
- a substrate; and
- a component on the substrate comprising: a thinned semiconductor die having a circuit side, a back side and a plurality of peripheral edges; a first polymer layer covering the circuit side and the edges; a second polymer layer covering the back side; and a plurality of terminal contacts on the first polymer layer in electrical communication with the die and bonded to the substrate.
250. The system of claim 249 further comprising a plastic body encapsulating the substrate and the component.
251. The system of claim 249 further comprising a plurality of planarized contact bumps on the die embedded in the first polymer layer.
252. The system of claim 249 wherein the substrate comprises a plurality of terminal leads in electrical communication with the terminal contacts.
253. The system of claim 249 wherein the substrate comprises an edge connector in electrical communication with the terminal contacts.
254. The system of claim 249 wherein the system comprises a system in a package.
255. The system of claim 249 wherein the substrate comprises a module substrate and the system comprises a multi chip module.
256. A system in a package comprising:
- a substrate comprising a plurality of terminal leads;
- a component mounted to the substrate, the component comprising: a thinned semiconductor die having a circuit side, a back side, four peripheral edges, and an area array of die contacts; a plurality of contact bumps on the die contacts; a first polymer layer covering the circuit side, the contact bumps and the peripheral edges; a second polymer layer covering the back side; and a plurality of terminal contacts on the contact bumps in electrical communication with the terminal leads; and
- a plastic body encapsulating the substrate and the component.
257. The system of claim 256 wherein the terminal contacts comprise bumps or balls and the component is flip chip mounted to the substrate.
258. The system of claim 256 wherein the terminal contacts comprise an edge connector and the component is edge connector mounted to the substrate.
259. A stacked semiconductor system comprising:
- a first semiconductor component comprising: a thinned semiconductor die having a circuit side, a back side, four peripheral edges, and an array of die contacts on the circuit side; a plurality of contact bumps on the die contacts; a first polymer layer covering the circuit side, the peripheral edges, and portions of the contact bumps; a plurality of conductive vias in the die in electrical communication with the contact bumps; a second polymer layer covering the back side; and a plurality of terminal contacts on the back side in electrical communication with the conductive vias; and
- a second semiconductor component substantially identical to the first semiconductor component comprising a plurality of second terminal contacts bonded to the contact bumps.
260. The stacked semiconductor system of claim 259 wherein the conductive vias comprise openings in the die, insulating layers on the openings, and a conductive material in the openings.
261. The stacked semiconductor system of claim 259 wherein the terminal contacts comprise balls or bumps in a grid array.
Type: Application
Filed: Aug 22, 2003
Publication Date: Jul 7, 2005
Inventors: Warren Farnworth (Nampa, ID), Alan Wood (Boise, ID), Trung Doan (Boise, ID)
Application Number: 10/646,897