Apparatus and method for generating clock signal

Abstract

The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock.

Description

This application claims the benefit of Taiwan application serial no. 93101101, filed on Jan. 16, 2004, the subject matter of which is incorporated herein by reference.

BACKGROUND OF INVENTION

1. Field of the Invention

This invention relates to an apparatus and a method for generating an output clock signal, particularly relates to an apparatus and a method for generating an output clock signal using an internal clock signal.

2. Description of the Prior Art

A Serial interface, such as an I²C interface, PCI Express, and Universal Serial Bus (USB), is a common interface for data transmission. The I²C interface comprises a data line and a clock line. The USB interface comprises two data lines, Data+ and Data−, and two power lines, Vdd and Gnd. These two data lines Data+ and Data− are differential signals.

Please refer to FIG. 1A; FIG. 1A shows a block diagram of the structure of a serial data communication using the serial interface. Please refer to FIG. 1A. The structure of the serial signal communication comprises a master device 110 and a slayer device 120. The master device 110 and the slayer device 120 are reference to a reference clock. The reference clock can be provided by a precise crystal oscillator 150 or be generated by an external crystal oscillator 130 and input into an internal phase-lock loop (PLL) 140. Conventionally, because frequency errors of the reference clocks could not be avoided, the reference clocks of the conventional master device 110 and the conventional slayer device 120 could not be exactly the same and synchronized. In the I²C interface, the I²C interface includes the clock link for transferring the reference clock from the master device 110 to the slave device 120 such that the master device 110 and the slave device 120 can be synchronization. In a USB, the USB signal contains a data signal and a synchronization signal such that the master device and the slave device can be synchronization according to the synchronization signal.

FIG. 1B shows the waveform of a USB signal. The USB signal 160 comprises a synchronization signal 170 and a data signal 180. When the USB receiver, such as the slayer device 120, receives the synchronization signal 170, the USB receiver compensates the sampling frequency of the received data signal 180 to avoid errors. In I²C, the I²C receiver uses the clock signal of the clock line as a reference to determine the sampling frequency of the data signal of the data line.

The conventional serial interface requires an external crystal oscillator. In additions, the reference clock frequencies of the conventional master device 110 and the slayer device 120 are not exactly the same.

Therefore, this invention provides a method and apparatus to generate a clock signal, wherein an external crystal oscillator is not required and the frequency of the clock signal is substantially the same as the frequency of the clock signal generated by a remote serial transmitting device.

SUMMARY OF INVENTION

It is therefore one of the objectives of the claimed invention to provide an apparatus and method for generating an output clock without an external reference clock.

According to the invention, the method for generating an output clock comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronization signal; producing a reference signal according to the synchronization signal; measuring the reference clock according to a second reference clock to generate a measured value; and producing the output clock according to the measured value and the second reference clock.

Preferably, the reference signal is adjusted according to a control signal such that the period of the reference signal is a multiple of that of the synchronization signal or the frequency of the reference signal is a multiple of that of the synchronization signal.

According to the present invention, an apparatus for generating an output clock comprises: a control logic receiving a transmitted signal having at least one data signal and at least one synchronization signal, and generating a reference signal according to the synchronization signal; a measuring unit for counting the reference signal according to a second reference clock to generate a counter signal; and an output unit for generating the output clock according to the counter signal and the second reference clock.

Preferably, the first counter can adjust the reference signal according to a control signal such that the period of the reference signal is a multiple of that of the synchronization signal or the frequency of the reference signal is a multiple of that of the synchronization signal.

These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of the present invention will be more readily understood from a detailed description of the preferred embodiments taken in conjunction with the following figures.

FIG. 1A shows a block diagram of the structure of a serial data communication using the serial interface;

FIG. 1B shows a waveform of a USB signal;

FIG. 2 shows a diagram of an embodiment of a clock generator according to the present invention; and

FIG. 3 shows a flowchart of an embodiment of a method for generating an output clock according to the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 shows an embodiment of a clock generator according to the present invention. The clock generator 300 comprises a control logic 310, a measuring unit 320, an output unit 340, and a free-run clock generator 330. The control logic 310 can receive a transmitting signal and generate a reference signal 360 according to the synchronization signal 350 of the transmitting signal. The ratio of the period of the reference signal 360 to the period of the synchronization signal 350 can be 1 or any other integers. The ratio of the period of the reference signal 360 and the synchronization signal 350 can also be a non-integer value such as 0.5 or 1.5.

The free-run clock generator 330 generates a free-run clock 370. Through counting the reference signal 360 by the measuring unit 320, (in other words, through measuring the period of the reference signal 360 according to the period of the free-run clock 370), a measured value 380 is obtained. The measured value K can be an integer or a non-integer. The output unit 340 receives the free-run clock 370 and the measured value 380 and generates an output clock 395. The ratio of the period of the output clock 395 to the period of the free-run clock 370 is equal to the measured value K. For example, if the period of the free-run clock 370 is Tx and the measured value 380 is K, thus the period of the output clock 395 is K×Tx. K can be represented as N.f whereas N and f are integers. In an embodiment, the measuring unit 320 can be implemented by a counter and the measured value is a counter value. In an embodiment, the output unit 340 can be a second counter.

The frequency of the free-run clock 370 generated by the free-run generator 330 is independent on that of the synchronization signal 350. Through the mechanism illustrated previously, the output clock 395 generated by the clock generator 300 of the present invention is corresponding to the synchronization signal 350. The synchronization signal 350 can be the synchronization signal for the USB interface or the clock signal for the I2C interface.

In another embodiment, the control logic 310 or the measuring unit 320 can receive a control signal 390 and adjust the period of the reference signal 360 according to the control signal 390. For example, if the value of the control signal 390 is M, the measured value 380 should be equal to K/M to match the counting range of the measuring unit 320. The value M of the control signal 390 can be a positive integer or a positive fraction.

In a preferred embodiment, the output unit 340 includes a storage unit for storing the measured value 380.

Please refer to FIG. 3; FIG. 3 shows a flowchart of generating an output clock of an embodiment of the present invention. The method comprises the step of:

In step 201, a reference signal 360 is generated according to a synchronization signal 350. The ratio of the period of the reference signal 360 to that of the synchronization signal 350 is a positive value, such as 2 or 2.5.

In step 202, the reference signal 360 is adjusted according to the control signal 390. Users can adjust the period of the reference signal 360 by controlling the control signal 390. Of course, this step 202 can be omitted.

In step 203, a counter value K (the measured value 380) is obtained by measuring (counting) the reference signal 360 according to the free-run clock 370. The free-run clock 370 is generated by the free-run clock generator 330. The counter value K can be a non-integer.

In step 204, an output clock 395 is outputted according to the measured value 380 and the free-run clock 370.

In other words, the period of the output clock 395 is K times of that of the free-run clock 370 generated by the free-run clock generator 330.

Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A method for generating an output clock, comprising:

producing a reference signal according to a synchronization signal of a received signal;

measuring the reference clock according to a clock signal to generate a measured value; and

producing the output clock according to the measured value and the clock signal.

2. The method of claim 1, wherein the measuring step comprises:

counting the reference clock according to the clock signal to generate the measured value.

3. The method of claim 1, wherein the period of the reference signal is a multiple of the period of the synchronization signal.

4. The method of claim 1, wherein the reference signal is generated according to the synchronization signal and a control signal.

5. The method of claim 1, wherein the frequencies of the reference signal and the synchronization signal are substantially the same.

6. The method of claim 1, wherein the reference signal is corresponding to the synchronization signal.

7. The method of claim 1, wherein the clock signal and the synchronization signal are independent.

8. An apparatus for generating an output clock, comprising:

a control logic utilized for receiving a transmitted signal having at least one data segment and at least one synchronization signal, and generating a reference signal according to the synchronization signal;

a measuring unit, coupled to the control logic, for generating a measured signal according to the reference signal and a clock signal; and

an output unit, coupled to the measuring unit, for generating the output clock according to the measured signal and the clock signal.

9. The apparatus of claim 8, further comprising: a free-run clock generator for generating the clock signal.

10. The apparatus of claim 8, wherein the period of the synchronization signal is a multiple of the period of the reference signal.

11. The apparatus of claim 8, wherein the output circuit comprises a storage unit for storing the measured signal.

12. The apparatus of claim 8, wherein the control logic modifies the period of the reference signal according to a control signal.

13. The apparatus of claim 8, wherein the measured signal is a non-integer.

14. The apparatus of claim 8, wherein the clock signal and the synchronization signal are independent.

15. An apparatus for generating an output signal, comprising:

a measuring unit utilized for measuring a serial signal according to a clock signal to generate a measured signal; and

an output circuit, coupled to the first counter, for receiving the measured signal and the clock signal and producing the output signal according to the measured signal and the clock signal, wherein the serial signal is corresponding to the output signal.

16. The apparatus of claim 15, wherein the measuring unit comprises a first counter.

17. The apparatus of claim 16, wherein the output unit comprises a second counter.

18. The apparatus of claim 15, wherein the output circuit comprising a storage unit for storing the measured signal.

19. The apparatus of the claim 15, wherein the measured signal is a non-integer.

20. The apparatus of claim 15, wherein the clock signal and the serial signal are independent.