Inspection condition setting program, inspection device and inspection system
A program is provided for setting efficiently, and with precision, the inspection conditions of an inspection device that detects particles and deformed patterns in or on products such as semiconductor integrated circuits that are manufactured by simultaneously forming a plurality of products on a single substrate. In particular, the system achieves greater efficiency of the setting of cell comparison regions and the setting of non-inspection regions. Input processing of a product type code, input processing of chip size and configuration information, reading processing of circuit layout data, extraction processing of repeated pattern region coordinates, extraction processing of sparse region coordinates and circuit pattern condition registration processing are sequentially executed.
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1. Field of the Invention
The present invention relates to an inspection condition setting programs that are executed by inspection devices or inspection systems for products such as semiconductor integrated circuits.
2. Description of the Related Art
The related art is described below using manufacture of semiconductor integrated circuits as an example. The manufacturing processes for integrated circuits are typically divided into wafer patterning processes and packaging processes. In wafer patterning processes, chips are manufactured with formation of multiple layers, such as circuit and interconnection pattern layers, usually on a silicon wafer. In packaging processes, the chips are separated and packaged.
In the wafer pattering processes, disconnections or short-circuits of the circuit patterns may arise because of such defects as particles or deformed patterns generated during manufacture. Un-patterned or patterned wafer inspection devices are employed to monitor defects. An un-patterned wafer inspection device directs a laser beam onto the wafer in inclined fashion from above and the scattered light is detected. The device is sometimes referred to as a “dark field” inspection device. A patterned wafer inspection device detects abnormal locations by picking up images of the circuit patterns and performing image processing thereon. Patterned wafer inspection devices are categorized into “bright field” inspection devices or SEM (Scanning Electron Microscope) inspection devices depending on the detector employed. The article “Inspection System Supporting Improved Semiconductor Yields” in the October 1999 issue of the Hitachi Journal describes these devices. However, there is no clear distinction between the un-patterned and patterned wafer inspection devices except the principle of inspection. In the present application, both devices are referred to generally as defect inspection devices.
Defect inspection devices play an important role in high-sensitivity detection of defects on circuit patterns formed on wafers. To make full use of the defect inspection device, it is necessary to set suitable inspection conditions in accordance with the method of deposition onto the wafer and the method of formation of the circuit patterns. Typically, a defect inspection device requires inspection conditions set beforehand to execute inspection programs. Two of the conditions to be set are circuit pattern conditions and optical/image processing conditions.
The circuit pattern conditions include parameters such as the size of the chips that are formed on the wafer, the arrangement information, and region information within the inspection algorithm can be changed accordingly. In addition, the optical/image processing conditions determine the inspection sensitivity and include parameters such as the amount of laser illumination that depends on deposition conditions and the wiring material, the contrast condition of images picked up by the detectors, and threshold values in image processing, etc. The circuit pattern conditions and optical/image processing conditions are interrelated.
In the circuit pattern conditions, parameters such as size and arrangement of the chips formed on the wafer are the same parameters used in exposure conditions. Since the inspection algorithms can be changed depending on the circuit pattern of the integrated circuit, regions within a chip need to be set for executing the respective algorithms. The inspection algorithms include, for example, chip comparison methods (also called die comparison methods), cell comparison methods and mixed comparisons methods combining chip comparison and cell comparison. Japanese Patent No. 3187827 discloses these methods. Note that in some cases detection sensitivity can be increased by excluding some regions from the defect inspection area. The regions to be excluded are, for example, a region in which no circuit pattern is present, such as the region between one chip and another on the wafer (called the “scribe lines”), or the region between one circuit block and another in a chip. In setting the circuit pattern conditions, such regions are registered as non-inspection regions.
Conventionally, circuit pattern conditions, except the parameters of the size and the arrangement of chips on the wafer, must be determined while observing the surface of the real wafer. To observe the surface of the real wafer, the wafer must be set into the defect inspection device and moved with an XY stage that holds the wafer.
BRIEF SUMMARY OF THE INVENTIONThe present invention provides a program whereby the circuit pattern conditions of the defect inspection device can be set rapidly and with high precision. Conventionally, the operator sets up the conditions by mounting an actual wafer in the defect inspection device; the following problems are therefore experienced. (1) Considerable time is taken to set the inspection conditions. In particular, in a production line in which a large number of different types of products were produced in small quantities, the task of setting the inspection conditions must be performed frequently. (2) Differences between operators can affect inspection conditions. In setting non-inspection regions or cell comparison regions using actual wafers, differences between individuals may result in inappropriate inspection conditions being set.
The present invention provides a program to set the circuit pattern conditions of a defect inspection device rapidly and with high precision using circuit layout data prepared by a CAD (Computer Aided Design) system. The program, according to the invention, may be an embodiment in which the program is stored in a secondary storage device of the defect inspection device and read and executed by a primary storage device of the defect inspection device, or an embodiment in which the program is stored in a secondary storage device of another computer separate from the defect inspection device and read and executed by this primary storage device, the output file being utilized by downloading the file to defect inspection devices through a network or removable storage medium.
Specifically, according to the present invention, in a program executed to set inspection conditions of an inspection device that detects the positions of particles and deformed patterns present in the subject of inspection, an inspection condition setting program is provided whereby there is executed circuit layout reading processing in which layout data of a circuit formed on the subject of inspection is read; repeated pattern region coordinate extraction processing in which the coordinates of repeated pattern regions in the circuit layout are extracted from circuit layout data read by this reading processing; and inspection region registration processing in which the coordinates of repeated pattern regions extracted by this extraction processing are registered as inspection regions of the inspection device.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the present invention is described with reference to the drawings.
In step 13, circuit layout data of an integrated circuit corresponding to the product type code is read. The circuit layout data is, for example, the data that is provided for forming the integrated circuits on the wafer by using exposure devices. An integrated circuit has a multilayer structure formed by a plurality of exposures. The circuit layout data therefore includes data for a plurality of layers. In step 14, the coordinates of repeated pattern regions present in the circuit layout data are extracted. Repeated pattern regions are regions in which a large number of transistors of the same shape, contact holes of the same shape, capacitors of the same shape or wiring of the same shape, etc., are provided in matrix fashion. Typical examples are static random access memory sections, flash memory sections, dynamic random access memory sections or read-only memory sections in an integrated circuit chip.
In step 15, the coordinates of sparse regions are extracted. Sparse regions are regions in which the circuit patterns are not densely integrated, such as scribe line regions between one chip and another or the regions between one circuit block and another within a chip where, even if particles or small scratches are produced, there is minimal effect on the viability of the integrated circuits. They are usually designated as non-inspection regions. In step 16, the circuit pattern conditions are registered using the information input or extracted in steps 11 to 15.
Element 41 is a wafer map display button. Elements 51 and 52 (described below) are drawn by clicking this button with the mouse after inputting product type code 21, chip pitch in the transverse direction 24, chip pitch in the longitudinal direction 25, number of chip rows 26 and number of chip columns 27. Element 51 displays the outer periphery of the wafer and element 52 displays a chip as a single rectangle. In this example the number of chip rows is input as “6” and the number of chip columns is input as “6”. The chip arrangement is determined by a change of color 53, by using the mouse to click on chips that are not actually formed or chips that, although formed, are not designated as subjects of inspection. Processing up to this point is that of steps 11 and 12 of
The coordinates of non-inspection regions are automatically extracted from the circuit layout data by using the mouse to click on an execute button for processing to automatically extract the coordinates of non-inspection regions 31. In this example, scribe line region 73 between outer frame 71 of the chip pitch and outer frame 72 of the chip size is automatically extracted. Scribe line region 73 is an area where the circuit pattern is sparse. Then, a region within the chip, indicated by shading is automatically extracted. The region, which does not belong to any of the SRAM circuit blocks 61 and 62 or CPU circuit block 63, ROM circuit block 64 or logic circuit block 65, is a region where the circuit pattern is sparse. Elements 66 and 67 are areas that are extracted as sparse regions within a circuit block (the method of extraction is described later). Regions that are extracted as non-inspection regions are displayed in a different color.
After execution of the above automatic extraction processing, the setting on the screen can be altered by using the mouse to click button 33 to change to the mode for manually altering the coordinates of a non-inspection regions. For example, regions that were automatically extracted as non-inspection regions owing to their circuit pattern being sparse can be changed to inspection regions. Regions that were not automatically designated as non-inspection regions owing to their circuit patterns being dense can be changed to non-inspection regions.
The coordinates of repeated pattern regions are automatically extracted by using a mouse to click on execute button 32 for automatically extracting the coordinates of repeated pattern regions. The repeated pattern regions are calculated and set for each layer. The repeated pattern regions for each layer are displayed in a different color. The layer that is displayed is changed using a plurality of buttons 81. The coordinates of the repeated pattern regions that are thus extracted are used as the coordinates for executing cell comparison processing.
After execution of the above automatic extraction processing, the setting on the screen can be changed by using a mouse to click on button 34 for changing to a mode for manually altering the coordinates of repeated pattern regions. In this way, a region that was automatically extracted as a repeated pattern region can be changed to a different pattern region.
By using the mouse to click button 82, the product type code, chip size, chip pitch, arrangement information, repeated pattern region coordinates and sparse region coordinates, are registered as circuit pattern conditions of the inspection conditions. This is step 16 of
Although, in this example, a case where short circuits were geometrically generated was illustrated, there is no restriction to this and a case of disconnections could also be calculated. In
where (p, q) indicates the coordinates of a divided region.
In step 140, if the value of TKR (p, q) calculated by (math 4) for each divided region is smaller than a predetermined threshold value, it is concluded that the circuit patterns constitutes sparse regions and the patterns are therefore designated non-examination regions. If the value is above the threshold value, the region is designated as an inspection region. As a result, on-chip inspection regions and non-inspection regions of the integrated circuits can be determined.
Although, in this example (math 4) was employed as step 139, there is no restriction to this and, for example, instead of (math 4), (math 5) could be employed. According to the present invention, when the circuit patterns are dense in a region in one or more layers, the region in question is designated an inspection region; when the circuit patterns are sparse in a region through all the layers, the region is designated anon-inspection regions.
TKR(p,q)=max(KR(1, p, q), KR(2, p, q), KR(3, p, q), . . . ,KR(L, p, q)) (5)
where max ( ) indicates a maximum value.
The example described above illustrates a method of registering circuit pattern conditions. The method has the following processes: the coordinates of repeated pattern regions are extracted from circuit layout data constituting the output of a CAD system, and the regions are designated as cell comparison regions in the inspection device; the coordinates of regions in which the circuit patterns are sparse are extracted and the regions are designated as non-inspection regions; scribe line regions at the chip periphery are designated as non-inspection regions. Setting of the cell comparison regions, setting of the inspection regions and setting of the non-inspection regions can be achieved by executing. programs designed for each setting; or each program can be executed independently.
As described above, a program is provided that is executed for setting circuit pattern conditions efficiently and with high precision. The conditions are required to inspect defects such as particles or deformed patterns using a defect inspection device such as a patterned or an unpatterned wafer inspection device. By executing the program according to the present invention, the setting of coordinates of repeated pattern regions or the coordinates of non-inspection regions, can be achieved faster and more precisely than by conventional methods.
Claims
1. A program for setting inspection conditions that is executed for setting inspection conditions of an inspection device that detects the positions of particles or deformed patterns present in or on a subject of inspection, wherein the program executes:
- circuit layout reading processing of reading circuit layout data formed on the subject of inspection;
- repeated pattern region coordinates extraction processing in which the coordinates of repeated pattern regions in the circuit layout are extracted from the circuit layout data that has thus been read in the circuit layout reading processing; and
- inspection region registration processing in which the coordinates of repeated pattern regions that have thus been extracted by the repeated pattern region coordinates extraction processing are registered as inspection regions of the inspection device.
2. A program for setting inspection conditions that-is executed for setting inspection conditions of an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection, wherein the program executes:
- circuit layout reading processing of reading circuit layout data formed on the subject of inspection;
- designated circuit block region coordinates extraction processing in which the coordinates of designated circuit block regions are extracted from the circuit layout data that has thus been read in the circuit layout reading processing; and
- inspection region registration processing in which the coordinates of circuit block regions that have thus been extracted by the designated circuit block region coordinates extraction processing are registered as inspection regions of the inspection device.
3. A program for setting inspection conditions that is executed for setting inspection conditions of an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection, wherein the program executes:
- circuit layout reading processing of reading circuit layout data formed on the subject of inspection;
- sparse region coordinates extraction processing in which the coordinates of regions where the circuit pattern is sparse are extracted from the circuit layout data that has thus been read in the circuit layout reading processing; and
- non-inspection region coordinates registration processing in which the coordinates of the sparse regions that have thus been extracted by the sparse region coordinates extraction processing are registered as non-inspection regions of the inspection device.
4. The program for setting inspection conditions according to claim 1 wherein the circuit layout data that is read in said circuit layout reading processing is the output data of a CAD system.
5. The program for setting inspection conditions according to claim 2 wherein the circuit layout data that is read in said circuit layout reading processing is the output data of a CAD system.
6. The program for setting inspection conditions according to claim 3 wherein the circuit layout data that is read in said circuit layout reading processing is the output data of a CAD system.
7. The program for setting inspection conditions according to claim 1 wherein array sections are extracted from the circuit layout data in said repeated pattern region coordinates extraction processing.
8. The program for setting inspection conditions according to claim 1 wherein the same processing as in cell comparison inspection provided by the inspection device is executed with respect to the circuit layout data in said repeated pattern region coordinates extraction processing.
9. The program for setting inspection conditions according to claim 3 wherein, in said sparse region coordinates extraction processing, the probability of occurrence of short-circuiting or disconnection is calculated with respect to the circuit layout data and the coordinates of regions where the probability of occurrence of short-circuiting or disconnection has a value smaller than the threshold value which is given beforehand are extracted.
10. The program for setting inspection conditions according to claim 3 wherein, in said sparse region coordinates extraction processing, the density of the circuit patterns are calculated with respect to the circuit layout data and the coordinates of regions where the density is less than a previously given value are extracted.
11. The program for setting inspection conditions according to claim 3 wherein, in said sparse region coordinates extraction processing, the coordinates of scribe line regions between one chip and another chip of the integrated circuits are extracted as sparse regions.
12. The program for setting inspection conditions according to claim 1 wherein, in order to execute said repeated pattern region coordinates extraction processing and said inspection region coordinates registration processing, a graphical user interface is provided, and repeated pattern regions are output to this graphical user interface.
13. The program for setting inspection conditions according to claim 2 wherein, in order to execute said designated circuit block region coordinates extraction processing and said inspection region coordinates registration processing, a graphical user interface is provided, and circuit block regions are output to this graphical user interface.
14. The program for setting inspection conditions according to claim 3 wherein, in order to execute said sparse region coordinates extraction processing and said non-inspection region coordinates registration processing, a graphical user interface is provided, and sparse regions are output to this graphical user interface.
15. An inspection device comprising:
- a calculation unit that extracts the coordinates of repeated pattern regions in a circuit layout from circuit layout data formed on the subject of inspection;
- a storage unit that registers as inspection regions the coordinates of this extracted repeated pattern regions; and
- an inspection unit that reads this inspection regions that have been registered in the storage section and detects the position of particles or deformed patterns present in or on the inspection subject.
16. An inspection system comprising:
- an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection; and
- a device management unit comprising calculation means that extracts the coordinates of a repeated pattern regions in the circuit layout from circuit layout data formed on the subject of inspection, storage means that registers as inspection regions the coordinates of these extracted repeated pattern regions, and output means that provides these inspection regions registered in the storage means to this inspection device, which is connected through a network.
17. An inspection device comprising:
- a calculation unit that extracts the coordinates of a designated circuit block regions from circuit layout data formed on a subject of inspection;
- a storage unit that registers as an inspection region the coordinates of these extracted circuit block regions; and
- an inspection unit that reads these inspection regions registered in the storage section and detects the positions of particles or deformed patterns present in or on the subject of inspection.
18. An inspection system comprising:
- an inspection device that detects the positions of particles or deformed patterns present in or on a subject of inspection; and
- a device management unit comprising calculation means that extracts the coordinates of a designated circuit block regions from circuit layout data formed on the subject of inspection, storage means that registers as inspection regions the coordinates of this extracted circuit block regions, and output means that provides this inspection region registered in the storage means to this inspection device, which is connected through a network.
19. An inspection device comprising:
- a calculation unit that extracts the coordinates of regions where the circuit patterns are sparse from circuit layout data formed on a subject of inspection;
- a storage unit that registers as a non-inspection regions the coordinates of this extracted sparse regions; and
- an inspection unit that reads this non-inspection regions registered in the storage section and detects the position of particles or deformed patterns present in or on the subject of inspection.
20. An inspection system comprising:
- an inspection device that detects the position of particles or deformed patterns present in or on a subject of inspection; and
- a device management unit comprising calculation means that extracts the coordinates of a regions where the circuit patterns are sparse from circuit layout data formed on the subject of inspection, storage means that registers as a non-inspection regions the coordinates of this extracted sparse regions, and output means that presents this non-inspection regions registered in the storage means to this inspection device, which is connected through a network.
Type: Application
Filed: Feb 24, 2005
Publication Date: Sep 8, 2005
Applicant: Hitachi High-Technologies Corporation (Tokyo)
Inventors: Makoto Ono (Yokohama), Yohei Asakawa (Yokohama), Hisafumi Iwata (Hayama), Kanako Harada (Yokohama)
Application Number: 11/066,121