Method of manufacturing nonvolatile memory cell
The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.
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1. Field Of the Invention
The invention relates generally to a method of manufacturing a nonvolatile memory cell, and more particularly to, a method of manufacturing a nonvolatile memory cell capable of enhancing a retention characteristic of the nonvolatile memory using selective oxidation.
2. Description of the Prior Art
Semiconductor memory device can be classified into RAM (random access memory) products such as DRAM (dynamic random access memory) and SRAM (static random access memory), and ROM (read only memory). RAM is volatile since the data in RAM is lost in time but ROM is nonvolatile since the data in ROM is not lost. Also, the input/output speed of data in RAM is fast but the input/output speed of data in ROM is low. This ROM product family may include ROM, PROM (programmable ROM), EPROM (erasable programmable ROM) and EEPROM (electrically erasable programmable read-only memory). Among them, a demand for EEPROM from which data is electrically programmable and erasable has been increased. The EEPROM or a flash EEPROM has a stack type gate structure in which a floating gate electrode and a control gate electrode are stacked.
The memory cell of the stack type gate structure programs/erases data by means of Fowler-Nordheim (F-N) tunneling and has a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode stacked on a semiconductor substrate. The gate electrodes have a stack structure in which a polysilicon layer into which an impurity having a strong heat-Resistance is doped or a polysilicon layer and a tungsten silicide (WSix) are stacked.
Generally, after the gate electrodes are formed, a high temperature annealing process for compensating for etching damage generated when a pattern of the gate electrode is formed is performed. At this time, however, there occurs a GGO (graded gate oxide) phenomenon in which a silicon substrate at an edge portion of the tunnel oxide film is oxidized/grown due to the annealing process. The GGO phenomenon is generated between the floating gate electrode and the semiconductor substrate to keep them by a given distance, thus solving a retention problem that is most important in the nonvolatile memory.
There was proposed “In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WNx on polycrystalline Si, LG, SEMICONDUCTOR CO. LTD., issued by Byung-Hak Lee etc. (IEEE, 1998). This paper proposes a resistance variation ratio to the width of the gate electrode formed of tungsten silicide (WSix) or tungsten (W).
Seeing a characteristic graph relating to the resistance variation ratio to the width of the gate electrode shown in .this paper, if the width of the gate electrode is reduced to below 0.2 μm, the resistance of the gate electrode formed of tungsten suicide (WSix) is abruptly increased while the resistance of the gate electrode formed of tungsten (W) is almost constant with no regard to reduced width. In other words, as the wired of the gate electrode formed of tungsten silicide (WSix) is reduced to below 0.2 mL, the resistance is abruptly increased while the resistance of the gate electrode formed of tungsten (W) is almost constant with no regard to reduced width.
Therefore, when the gate electrode is formed of tungsten silicide (WSix), there is a problem that a RC delay time is delayed since the resistance is increased as the memory cell is higher integrated. Due to this, there is a need for a method for forming a gate electrode using tungsten (W) in order to implement higher integrated memory cell.
However, tungsten (W) is abnormally oxidized since it easily reacts with oxygen at a high temperature. Therefore, there occurs a problem that an upper surface characteristic of the gate electrode is degraded since tungsten (W) is abnormally oxidized at a high temperature annealing process.
Recently, in order to solve this problem, there has been proposed a selective oxidation process instead of the high temperature annealing process. Though the selective oxidation process can prevent abnormal oxidization of tungsten (W), it does not sufficiently oxidize the upper surface of the semiconductor substrate at an edge portion of the tunnel oxide film. Thus, there is a problem that it does not solve a retention problem of the nonvolatile memory cell.
Therefore, there is a need for a method capable of solving a retention problem in a nonvolatile memory cell when a gate electrode is formed using tungsten (W).
SUMMARY OF THE INVENTIONIt is therefore an object of the present invention to provide a method of manufacturing a nonvolatile memory cell capable of solving a high temperature annealing problem occurring when a gate electrode is used, in a way that the gate electrode is formed using tungsten (W) in order to implement integration of the nonvolatile memory cell.
In order to accomplish the above object, a method of manufacturing a nonvolatile memory cell according to the present invention, is characterized in that it comprises the steps of forming a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode on a semiconductor substrate; forming source and drain region by means of source/drain ion implantation process; forming an oxide layer on the source and drain region by means of selective oxidization process; and forming spacers on both sides of the floating gate electrode and the control gate electrode.
Also, a method of manufacturing a nonvolatile memory cell according to the present invention, is characterized in that it comprises the steps of sequentially forming a tunnel oxide film, a first polysilicon layer, a dielectric film, a second polysilicon layer, a tungsten layer and a hard mask layer a semiconductor substrate; etching the hard mask layer, the tungsten layer, the second polysilicon layer and the dielectric film in one direction to form a control gate electrode; performing a first selective oxidization process to form a first oxide layer on both sides of the second polysilicon layer and the dielectric film; forming a first spacer on both sides of the control gate electrode; etching the first polysilicon layer and the tunnel oxide film to form a floating gate electrode; performing source/drain ion implantation process to form a source and drain region; performing a selective oxidization process to form a second oxide film on the source and drain region; and forming a second spacer on both sides of the floating gate electrode and the control gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGSThe aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein:
FIGS. 4A˜9A and FIGS. 10˜12 are cross-sectional views for explaining a process of manufacturing the nonvolatile memory cell shown in
FIGS. 4B˜9B are cross-sectional views for explaining a process of manufacturing of the nonvolatile memory cell shown in
FIGS. 14˜19 are cross-sectional views for explaining a process of manufacturing of the nonvolatile memory cell shown in
The present invention will be described in detail by way of a preferred embodiment with reference to accompanying drawings.
Referring now to FIGS. 1˜3, a control gate electrode 8 shown in the drawings functions as a control gate line of a plurality of memory cells MC. A floating gate electrode 4a is positioned in each of the memory cell MC and is electrically floated.
A semiconductor substrate 1 is provided and a device isolation film 2 for separating active regions and a plurality of device isolation regions for separating the active regions is formed in the semiconductor substrate 1. A source region 10 and a drain region 11 are formed in the active region. A tunnel oxide film 3, a floating gate electrode 4a, a dielectric film (ONO) 5, a control gate electrode 8 and a hard mask layer 9 are sequentially stacked on the active region in the semiconductor substrate 1. At this time, the first polysilicon layer 4 is formed and is then etched to form the floating gate electrode 4a. The control gate electrode 8 has a stack structure in which the second polysilicon layer 6 as an lower layer and the tungsten nitride film (WN)/tungsten (W) 7 as an upper layer are stacked.
Generally, in a NOR type flash memory, bit lines (not shown) being a common line of the plurality of the memory cells MC are connected to the drain region 11 of the memory cell MC and the source region 10 being a diffusion layer line is formed in parallel to the direction. along which the control gate electrode 8 extends. At this time, the diffusion layer line functions as a common line (common source region) between the plurality of the memory cells MC.
The major characteristics of the nonvolatile memory cell in the first embodiment lies in that it forms the control gate electrode 8 having. a stack structure of polysilicon 6 and tungsten (W) 7 and forms an oxide layer 12 on the source region 10 and the drain region 11 at an edge portion of the tunnel oxide film 3, in order to prevent a retention problem of the memory cells.
In order to implement the above characteristics, in the first embodiment, a pattern of the control gate electrode 8 and the floating gate electrode 4a are formed and an ion implantation for the source region 10 and the drain region 11 is then formed before the selective oxidization process that is performed for the entire surface of the semiconductor substrate 1. As a result, abnormal oxidization of tungsten (W) 7 can be prevented and the oxide layer 12 can be formed on the source region 10 and the drain region 11 at the edge portion of the tunnel oxide film 3.
A method of manufacturing the memory cell of the first embodiment will be described by reference to FIGS. 4A˜12.
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In the present invention, a subsequent process of manufacturing the device isolation region is the same to the conventional process. Thus, a detailed description on the process of manufacturing the device isolation region will be omitted and only the active region will be explained.
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As mentioned above, the selective oxidization process is performed under the same process to a common selective oxidization process (for example, a process time of about 2˜7 minutes). Even with this oxidization process, the oxide layer 12 is formed in thickness of about 50Ř400Å. This thickness is much thicker than that of the oxide film formed under the same conventional selective oxidization process (for example, about 20 Ř50 Å). The reason why the thickness of the oxide film 12 according to the first embodiment of the present invention is much thicker than that formed under the same conventional selective oxidization process is that the ion implantation process for forming the source region 10 and the drain region 11 is performed before the selective oxidization process. In other words, this is because that a region of the semiconductor substrate 1 into which impurity is implanted, for example, the source region 10 and the drain region 11 are much faster oxidized than a region of the semiconductor substrate 1 into which impurity is not implanted.
The nonvolatile memory cell according to the second embodiment of the present invention will be below described.
A structure of the memory cell according to the second embodiment of the present invention is almost same to the structure of the memory cell shown in
Also, the second embodiment of the present invention secures an effective channel length margin of the memory cell by forming the width of the floating gate electrode 24a wider than the width of the control gate electrode 28.
FIGS. 14˜18 are cross-sectional views for explaining a process of manufacturing of the flash memory cell according to the second embodiment of the present invention, which show cross-sectional views taken along lines ‘X1-X1’ in Fig.l. In this paragraph, the active region only will be explained. As the step of forming the hard mask layer is same to the first embodiment, the explanation thereof will be omitted and subsequent processes thereof will be explained below.
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Then, a photoresist pattern (not shown) is formed by exposure process using the photo mask. Thereafter, the hard mask layer 29, the tungsten nitride film (WN)/tungsten (W) 27, the second polysilicon layer 26 and the dielectric film 25 are etched in one direction by means of the etch process using the photoresist pattern, thus forming a control gate electrode 28. In this process, both sides of the second polysilicon layer 26 being a lower layer in the control gate electrode 28 and the dielectric film 25 are over-etched. This is because that the etch rat of the second polysilicon layer 26 and the dielectric film 25 is higher than that of the tungsten nitride film (WN)/tungsten (W) 27 being an upper layer in the control gate electrode 28.
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As can be understood from the above description, the present invention has an advantage that is can reduce a RC delay time of word lines depending on integration of the memory cell by forming a gate electrode using tungsten (W).
Also, as a control gate is pattern/formed and spacers are formed on both sides, of the control gate, the present invention can prevent a lift of a dielectric film by a subsequent selective oxidization process.
Further, the present invention forms a floating gate electrode using the spacer as a mask. Thus, the present invention can flexibly change the length of the floating gate electrode to obtain a channel length margin.
In addition, the present invention first performs a source/drain ion implantation process for forming source and drain region before the selective oxidization process in order to promote the speed of oxidization an edge portion of the tunnel oxide film. Therefore, a given distance between the semiconductor substrate and the tunnel oxide film can be secured to solve a data retention problem of the flash memory cell.
The present invention has been described with reference to a particular embodiment in connection_with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof.
It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the present invention.
Claims
1-18. (canceled)
19. A method of manufacturing a nonvolatile memory cell, comprising the steps of:
- forming a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode on a semiconductor substrate;
- performing a first selective oxidization process;
- forming a source and drain region utilizing a source/drain ion implantation process;
- forming an oxide layer on sides of the floating gate electrode and the source and drain region utilizing a second selective oxidization process;
- forming an insulation film covering the oxide layer and the control gate electrode; and
- performing an etching process to form a first spacer which is formed by the insulating film on at least one side of the dielectric film and the control gate electrode and to form a second spacer which is formed by the oxide layer on at least one side of the floating gate electrode.
20. The claim 19, wherein the control gate electrode is formed by stacking a polysilicon layer and a tungsten nitride film (WN)/tungsten (W).
21. The method of claim 19, wherein the oxide layer is formed in a thickness of about 50 Ř400 Å.
22. The method of claim 19, wherein the dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film.
23. The method of claim 19, wherein the second selective oxidization process uses hydrogen gas.
24. The method of claim 19, wherein the control gate electrode is formed by stacking a polysilicon layer and a tungsten nitride film (WN)/tungsten (W), and the source/drain ion implantation process is performed in a single step using an ion implantation energy of about 5 KeV-30 KeV or about 15 KeV-45 KeV.
25. The method of claim 19, wherein the control gate electrode is formed by stacking a polysilicon layer and a tungsten nitride film (WN)/tungsten (W), and the oxide layer is formed in a thickness of about 50Ř400 Å.
26. The method of claim 19, wherein the control gate electrode is formed by stacking a polysilicon layer and a tungsten nitride film (WN)/tungsten (W), and the dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film.
27. The method of claim 19, wherein the control gate electrode is formed by stacking a polysilicon layer and a tungsten nitride film (WN)/tungsten (W), and the second selective oxidization process uses hydrogen gas.
28. The method of claim 19, wherein the source/drain ion implantation process is performed in a single step using an ion implantation energy of about 5 KeV-30 KeV or about 15 KeV-45 KeV, and the oxide layer is formed in a thickness of about 50 Ř400 Å.
29. The method of claim 19, wherein the source/drain ion implantation process is performed in a single step using an ion implantation energy of about 5 KeV-30 KeV or about 15 KeV-45 KeV, and the dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film.
30. The method of claim 19, wherein the source/drain ion implantation process is performed in a single step using an ion implantation energy of about 5 Kev˜30 KeV or about 15 KeV˜45 KeV, and the second selective oxidization process uses hydrogen gas.
31. The method of claim 19, wherein the oxide layer is formed in a thickness of about 50 Ř400 Å, and the dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film.
32. The method of claim 19, wherein the oxide layer is formed in a thickness of about 50 Ř400 Å, and the second selective oxidization process uses hydrogen gas.
33. The method of claim 19, wherein the dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film, and the second selective oxidization process uses hydrogen gas.
34. The method of claim 19, wherein the first selective oxidization process uses hydrogen gas.