METHOD AND APPARATUS FOR GENERATING ABSOLUTE TIME IN PREGROOVE DATA
An apparatus and a method for generating an ATIP data are provided. The apparatus, based on a wobble signal generated by reading a re-writable compact disc, generates an ATIP data; the apparatus includes: a frequency demodulator for demodulating the wobble signal to generate an original ATIP data signal; an ATIP clock generating circuit for generating an ATIP clock signal based on the wobble signal; and a data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating the ATIP data based on the number of the original ATIP data signal at a first logic level during one period of the ATIP clock signal. This apparatus uses the number of the original ATIP data signal at a first logic level during one period of the ATIP clock signal and the bi-phase rule to precisely generate the ATIP data.
This application claims the priority benefit of Taiwan application Ser. No. 93108817, filed on Mar. 31, 2005. All disclosure of the Taiwan application is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention generally relates to a method of generating absolute time in pregroove (ATIP) data, and more particularly to a method of generating ATIP data based on an original ATIP data signal generated by a wobble signal and an ATIP clock signal.
2. Description of Related Art
During the manufacture of the re-writable compact disk (CD), a shallow groove will be made from the center of the CD toward the outer circumference in spiral way. This groove is so-called pregroove. This pregroove is not a perfect spiral but a little wobbling. Generally, in a CD made by die-casting, each sector includes the timing-related data to control the spin speed of the CD-ROM drive in order to accurately read the data on the CD. A CD-RW drive must have some ways to introduce the laser for recording the data toward the outer circumference in proper sequence and to control the spin speed. That is what the wobbling pregroove is for—to provide the tracking and timing data, which are so-called ATIP data.
The wobbling shape of the pregroove is similar to a sinusoid. The track excursion ranges within 0.03 um deviation of the tracking center. This range is 1/1000 of the wavelength of the pregroove. That's why it is called “wobbling”. Although the pregroove is almost invisible, the optical driving device of the CD-RW drive can detect it. This pregroove will introduce the laser beam of the CD-RW drive and provide the timing-related data, which are so-called ATIP data. The ATIP data can make the speed of the CD-RW stable during the writing process. That is, the optical driving device of the CD-RW drive can detect the pregroove and receive a wobble signal, then generates ATIP data to obtain the timing-related information.
Therefore, how to effectively read the wobble signal from the CD-RW and to effectively obtain the ATIP data from the wobble signal is an important issue in CD-RW application.
SUMMARY OF THE INVENTIONThe present invention is directed to an apparatus for generating ATIP data by generating the ATIP clock signal to precisely generate the ATIP data.
The present invention is also directed to a method of generating ATIP data by generating the ATIP clock signal to precisely generate the ATIP data.
The present invention is directed to a method of generating ATIP data by using the bi-phase rule to generate the ATIP data when the ATIP data matches a synchronization pattern.
According to an embodiment of the present invention, the apparatus for generating an ATIP data is based on a wobble signal generated by reading a re-writable compact disc for generating an ATIP data. The apparatus comprises a frequency demodulator for demodulating the wobble signal to generate an original ATIP data signal (ATIPORG signal); an ATIP clock generating circuit for generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; and an ATIP data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating the ATIP data based on the number of the ATIPORG signal at a first logic level during one period of the ATIPCLK signal.
In an embodiment of the present invention, the ATIP clock generating circuit includes: a counter for counting the wobble signal to generate the ATIPCLK signal to the ATIP data generating circuit and setting the period of the ATIPCLK signal to be 3.5 periods of the wobble signal; and an alignment signal generating circuit for detecting the ATIPORG signal, when the ATIPORG signal is kept at a same status within a predetermined period of time, the alignment signal generating circuit generates an alignment signal to align the ATIPCLK to the wobble signal with a status transition.
In an embodiment of the present invention, the frequency demodulator further comprises: a high frequency (HF) counter, for receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal; and a low pass filter (LPF), for receiving the FMPRD data and filtering an average of half-period of the wobble signal; wherein the frequency demodulator subtracts the average of half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data), and the ATIPORG signal is determined by the PRDDIFF data in each half-period of the wobble signal: the ATIPORG signal is asserted to the first logic level when the PRDDIFF data in half-period of the wobble signal is positive or zero; and the ATIPORG signal is de-asserting to a second logic level when the PRDDIFF data in half-period of the wobble signal is negative.
In an embodiment of the present invention, the step of generating the ATIP data signal includes: demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data), wherein the wobble signal is generated by reading a re-writable compact disc; generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; and counting the number of the ATIPORG signal at a first logic level during one period of the ATIPCLK signal.
In an embodiment of the present invention, the step of generating the ATIP data signal by using one predetermined threshold further includes: comparing the number of the ATIPORG signal at the first logic level with a predetermined threshold; asserting the ATIP data to the first logic level when the number of the ATIPORG signal at the first logic level is larger than or equal to the predetermined threshold; and de-asserting the ATIP data to a second logic level when the number of the ATIPORG signal at the first logic level is smaller than the predetermined threshold.
In an embodiment of the present invention, the step of generating the ATIP data signal by using two predetermined threshold further includes: adding all PRDDIFF data within the period of the ATIPCLK signal to obtain the adding data; comparing the number of the ATIPORG signal at the first logic level with a first predetermined threshold and a second predetermined threshold, and the first predetermined threshold is larger than the second predetermined threshold; asserting the ATIP data to the first logic level when the number of the ATIPORG signal at the first logic level is larger than the first predetermined threshold; and de-asserting the ATIP data to a second logic level when the number of the ATIPORG signal at the first logic level is smaller than the second predetermined threshold; when the number of the ATIPORG signal at the first logic level is between the first and the second predetermined thresholds: asserting the ATIP data to the first logic level when the adding data is positive; and de-asserting the ATIP data to the second logic level when the adding data is negative.
In an embodiment of the present invention, the step of demodulating the wobble signal to generate the ATIPORG signal further comprises: receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal; filtering an average of half-period of the wobble signal from the FMPRD data; subtracting an average of a half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data) in each half-period of the wobble signal; and generating the ATIPORG signal based on the PRDDIFF data.
In an embodiment of the present invention, the step of generating the ATIPORG signal based on the PRDDIFF data comprises: asserting the ATIPORG signal at the first logic level when the PRDDIFF data is positive or zero; and asserting the ATIPORG signal at the second logic level when the PRDDIFF data is negative.
In an embodiment of the present invention, the step of generating the ATIPCLK signal based on the wobble signal comprises: counting the wobble signal to generate the ATIPCLK signal, the period of the ATIPCLK signal being 3.5 periods of the wobble signal; and aligning the ATIPCLK signal to the wobble signal with a status transition when the ATIPORG signal is kept at a same status within a predetermined period of time; wherein the predetermined period of time is an integral multiple of 3.5 periods of the wobble signal.
In an embodiment of the present invention, wherein the wobble signal is digitalized and processed by a de-glitch process.
In an embodiment of the present invention, the step of generating the ATIP data by using the bi-phase rule to generate the ATIP data when the ATIP data matches a synchronization pattern comprises: demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data), wherein the wobble signal is generated by reading a re-writable compact disc; generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; defining the next period of the ATIPCLK signal to be a first period when a portion of the generated ATIP data matches a synchronization pattern (sync pattern); and generating an ATIP data based on the number of the ATIPORG signal at the first logic level corresponding to a 2Nth period of the ATIPCLK signal and the number of the ATIPORG signal at the first logic level corresponding to a 2N+1st period of the ATIPCLK signal, wherein N is a positive integer.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: counting the number W1 of the ATIPORG signal at the first logic level, corresponding to the 2Nth period of the ATIPCLK signal; counting the number W2 of the ATIPORG signal at the first logic level, corresponding to the 2N+1st period of the ATIPCLK signal; adding the PRDDIFF data in the 2Nth period of the ATIPCLK signal to obtain an adding data S1; adding the PRDDIFF data in the 2N+1st period of the ATIPCLK signal to obtain an adding data S2; and determining the period of the ATIPCLK signal of the ATIP data is 2Nth period or 2N+1st period.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: making the ATIP data be inverse of preceding period of the ATIPCLK signal when the period of the ATIPCLK signal is 2N+1st period; and comparing the number W1 and W2 when the period of the ATIPCLK signal is 2Nth period.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: asserting the ATIP data to the first logic level when W1>W2; de-asserting the ATIP data to a second logic level when W1<W2; and comparing the adding data S1 and S2 when W1=W2.
In an embodiment of the present invention, the step of generating the ATIP data further comprises: asserting the ATIP data to the first logic level when S1>=S2; and de-asserting the ATIP data to the second logic level when S1<S2.
In light of the above, the present invention uses the status of the ATIPORG signal corresponding to the ATIPCLK signal and the bi-phase rule to precisely generate the ATIP data.
The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
Please reference to
Since the wobble signal is a frequency-modulated signal, so it needs to be de-modulated by a frequency modulator. Please reference to
The apparatus in
Referring to
Method 1
Referring to
Two thresholds are provided to be used in the present invention. Please reference to
Method 2
The step S710 further includes the following steps. Counting the number W1 of the ATIPORG signal at high logic level (low logic level) corresponding to a 2Nth period of the ATIPCLK signal (S712) and counting the number W2 of the ATIPORG signal at high logic level (low logic level) corresponding to a 2N+1st period of the ATIPCLK signal (S714). Then, adding the PRDDIFF data in the 2Nth period of the ATIPCLK signal to obtain an adding data S1 (S721) and adding the PRDDIFF data in the 2N+1st period of the ATIPCLK signal to obtain an adding data S2 (S723). Next, determining the period of the ATIPCLK signal of the ATIP data is 2Nth period or 2N+1st period (S725). If the period of the ATIPCLK signal is 2N+1st period, make the ATIP data be inverse of preceding period of the ATIPCLK signal (S727). If the period of the ATIPCLK signal is 2Nth period, comparing the number W1 and W2 (S731). If W1>W2, the ATIP data is asserted to high logic level (S733). If W1<W2, the ATIP data is de-asserted to low logic level (S735). If W1=W2, comparing the adding data S1 and S2 (S737). If S1>=S2, the ATIP data is asserted to high logic level (S739). If S1<S2, the ATIP data is de-asserted to low logic level (S741).
If the condition W1=W2 happens, comparing the adding data S1 and S2. Assume the W1 and W2 is equal in
In light of the above, the present invention uses the status of the ATIPORG signal corresponding to the ATIPCLK signal and the bi-phase rule to precisely generate the ATIP data.
The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.
Claims
1. A method of generating an ATIP data, comprising:
- demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data), wherein the wobble signal is generated by reading a re-writable compact disc;
- generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal; and
- counting the number of the ATIPORG signal at a first logic level during one period of the ATIPCLK signal.
2. The method of claim 1, further comprising:
- comparing the number of the ATIPORG signal at the first logic level with a predetermined threshold;
- asserting the ATIP data to the first logic level when the number of the ATIPORG signal at the first logic level is larger than or equal to the predetermined threshold; and
- de-asserting the ATIP data to a second logic level when the number of the ATIPORG signal at the first logic level is smaller than the predetermined threshold.
3. The method of claim 1, further comprising:
- adding all PRDDIFF data within the period of the ATIPCLK signal to obtain the adding data;
- comparing the number of the ATIPORG signal at the first logic level with a first predetermined threshold and a second predetermined threshold, and the first predetermined threshold is larger than the second predetermined threshold;
- asserting the ATIP data to the first logic level when the number of the ATIPORG signal at the first logic level is larger than the first predetermined threshold; and
- de-asserting the ATIP data to a second logic level when the number of the ATIPORG signal at the first logic level is smaller than the second predetermined threshold;
- when the number of the ATIPORG signal at the first logic level is between the first and the second predetermined thresholds:
- asserting the ATIP data to the first logic level when the adding data is positive; and
- de-asserting the ATIP data to the second logic level when the adding data is negative.
4. The method of claim 1, wherein the step of demodulating the wobble signal to generate the ATIPORG signal further comprises:
- receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal;
- filtering an average of half-period of the wobble signal from the FMPRD data;
- subtracting an average of a half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data) in each half-period of the wobble signal; and
- generating the ATIPORG signal based on the PRDDIFF data.
5. The method of claim 4, wherein the step of generating the ATIPORG signal based on the PRDDIFF data comprises:
- asserting the ATIPORG signal at the first logic level when the PRDDIFF data is positive or zero; and
- asserting the ATIPORG signal at the second logic level when the PRDDIFF data is negative.
6. The method of claim 1, wherein the step of generating the ATIPCLK signal based on the wobble signal comprises:
- counting the wobble signal to generate the ATIPCLK signal, the period of the ATIPCLK signal being 3.5 periods of the wobble signal; and
- aligning the ATIPCLK signal to the wobble signal with a status transition when the ATIPORG signal is kept at a same status within a predetermined period of time;
- wherein the predetermined period of time is an integral multiple of 3.5 periods of the wobble signal.
7. The method of claim 1, wherein the wobble signal is digitalized and processed by a de-glitch process.
8. A method for generating an ATIP data, comprising:
- demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal) and a plurality of differential data (PRDDIFF data), wherein the wobble signal is generated by reading a re-writable compact disc;
- generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal;
- defining the next period of the ATIPCLK signal to be a first period when a portion of the generated ATIP data matches a synchronization pattern (sync pattern); and
- generating an ATIP data based on the number of the ATIPORG signal at the first logic level corresponding to a 2Nth period of the ATIPCLK signal and the number of the ATIPORG signal at the first logic level corresponding to a 2N+1st period of the ATIPCLK signal, wherein N is a positive integer.
9. The method of claim 8, wherein the step of generating the ATIP data further comprises:
- counting the number W1 of the ATIPORG signal at the first logic level, corresponding to the 2Nth period of the ATIPCLK signal;
- counting the number W2 of the ATIPORG signal at the first logic level, corresponding to the 2N+1st period of the ATIPCLK signal;
- adding the PRDDIFF data in the 2Nth period of the ATIPCLK signal to obtain an adding data S1;
- adding the PRDDIFF data in the 2N+1st period of the ATIPCLK signal to obtain an adding data S2; and
- determining the period of the ATIPCLK signal of the ATIP data is 2Nth period or 2N+1st period.
10. The method of claim 9, further comprises:
- making the ATIP data be inverse of preceding period of the ATIPCLK signal when the period of the ATIPCLK signal is 2N+1st period; and
- comparing the number W1 and W2 when the period of the ATIPCLK signal is 2Nth period.
11. The method of claim 10, further comprises:
- asserting the ATIP data to the first logic level when W1>W2;
- de-asserting the ATIP data to a second logic level when W1<W2; and
- comparing the adding data S1 and S2 when W1=W2.
12. The method of claim 10, further comprises:
- asserting the ATIP data to the first logic level when S1>=S2; and
- de-asserting the ATIP data to the second logic level when S1<S2.
13. The method of claim 8, wherein the step of demodulating the wobble signal to generate the ATIPORG signal comprises:
- receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal;
- filtering an average of half-period of the wobble signal from the FMPRD data;
- subtracting an average of a half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data) in each half-period of the wobble signal; and
- generating the ATIPORG signal based on the PRDDIFF data.
14. The method of claim 13, wherein the step of generating the ATIPORG signal based on the PRDDIFF data comprises:
- asserting the ATIPORG signal at the first logic level when the PRDDIFF data is positive or zero; and;
- asserting the ATIPORG signal at the second logic level when the PRDDIFF data is negative.
15. The method of claim 8, wherein the step of generating the ATIPCLK signal based on the wobble signal comprises:
- counting the wobble signal to generate the ATIPCLK signal, the period of the ATIPCLK signal being 3.5 periods of the wobble signal; and
- aligning the ATIPCLK signal to the wobble signal with a status transition when the ATIPORG signal is kept at a same status within a predetermined period of time;
- wherein the predetermined period of time is an integral multiple of 3.5 periods of the wobble signal.
16. The method of claim 8, wherein the wobble signal is digitalized and processed by a de-glitch process.
17. An apparatus for generating an ATIP data, comprising:
- a frequency demodulator, for demodulating a wobble signal to generate an original ATIP data signal (ATIPORG signal);
- an ATIP clock generating circuit, for generating an ATIP clock signal (ATIPCLK signal) based on the wobble signal, wherein the wobble signal is generated by reading a re-writable compact disc; and
- an ATIP data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating an ATIP data based on the number of the ATIPORG signal at a first logic level during one period of the ATIPCLK signal.
18. The apparatus of claim 17, wherein the ATIP clock generating circuit comprises:
- a counter, for counting the wobble signal to generate the ATIPCLK signal to the ATIP data generating circuit and setting the period of the ATIPCLK signal to be 3.5 period of the wobble signal; and
- an alignment signal generating circuit, for detecting the ATIPORG signal, wherein when the ATIPORG signal is kept at a same status within a predetermined period of time, the alignment signal generating circuit generates an alignment signal to align the ATIPCLK to the wobble signal with a status transition.
19. The apparatus of claim 17, wherein the frequency demodulator further comprises:
- a high frequency (HF) counter, for receiving the wobble signal and generating a plurality of counting data (FMPRD data) in each half-period of the wobble signal; and
- a low pass filter (LPF), for receiving the FMPRD data and filtering an average of half-period of the wobble signal;
- wherein the frequency demodulator subtracts the average of half-period of the wobble signal from the FMPRD data to obtain a plurality of differential data (PRDDIFF data), and the ATIPORG signal is determined by the PRDDIFF data in each half-period of the wobble signal:
- the ATIPORG signal is asserted to the first logic level when the PRDDIFF data in half-period of the wobble signal is positive or zero; and
- the ATIPORG signal is de-asserting to a second logic level when the PRDDIFF data in half-period of the wobble signal is negative.
Type: Application
Filed: Mar 31, 2005
Publication Date: Oct 13, 2005
Inventors: Stanley Liow (Taipei Hsien), Kobe Chou (Taipei Hsien)
Application Number: 10/907,399