Abstract: An apparatus and a method for generating ATIP data is provided. The apparatus generates ATIP data from a wobble signal of a re-writable compact disc. The apparatus includes a frequency demodulator for demodulating the wobble signal to generate an original ATIP data signal; an ATIP clock generating circuit for generating an ATIP clock signal based on the wobble signal; and a data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating the ATIP data based on the number of measurement periods for which the original ATIP data signal is at a first logic level during one period of the ATIP clock signal. This apparatus uses this number and the bi-phase rule to precisely generate ATIP data.

Abstract: An apparatus and a method for generating an ATIP data are provided. The apparatus, based on a wobble signal generated by reading a re-writable compact disc, generates an ATIP data; the apparatus includes: a frequency demodulator for demodulating the wobble signal to generate an original ATIP data signal; an ATIP clock generating circuit for generating an ATIP clock signal based on the wobble signal; and a data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating the ATIP data based on the number of the original ATIP data signal at a first logic level during one period of the ATIP clock signal. This apparatus uses the number of the original ATIP data signal at a first logic level during one period of the ATIP clock signal and the bi-phase rule to precisely generate the ATIP data.

Abstract: A method for generating a wobble clock signal. When the wobble signal becomes deformed or a defect on the optical disc is found, the present invention provides a stable wobble clock signal, which is used to maintain a stable rotation speed when the optical disc is processed. In addition, the present invention also determines whether the wobble signal is deformed according to the result of comparing the width of the wobble signal at different status with the average of the half cycle width of the wobble signal.

Abstract: A read only memory circuit for debugging and updating, the circuit includes read only memory, debug program memory, program counter, and compare and load unit. In the circuit, the compare and load unit detects instruction-read-memory-address from the program counter. If the instruction-read-memory-address is a predetermined main program address, the compare and load unit serves to transmit a debug address in the debug program memory to the program counter to update the original instruction-read-memory-address for debugging.

Abstract: A method for generating a wobble clock signal. When the wobble signal becomes deformed or a defect on the optical disc is found, the present invention provides a stable wobble clock signal, which is used to maintain a stable rotation speed when the optical disc is processed. In addition, the present invention also determines whether the wobble signal is deformed according to the result of comparing the width of the wobble signal at different status with the average of the half cycle width of the wobble signal.

Abstract: A tracking control method controls an optical disk drive to access an optical disk having a plurality of groove tracks and land tracks, which are alternately interlaced with each other. The tracking control method includes the following steps. First, detecting a track position of the optical disk where the optical disk drive accesses. Then, predicting at least one distance count according to the track position. Finally, generating a switch signal for controlling the optical disk drive to use different accessing powers to access the groove/land tracks according to the distance count. Wherein the track position is located at a current track of the tracks and the distance count represents a length between a start point of the current track and a start point of a following track next to the current track.

Abstract: A power-saving control circuitry of an electronic device is provided. The power-saving control circuitry comprises a power control circuit, an oscillator, a clock pulse generator, a reserve circuit and a multi-enable module. When the electronic device enters a power saving mode, the oscillator stops generating oscillatory timing signals and the clock pulse generator stops generating operational clock signals. Because digital timing signals are generated by either the oscillatory timing signals or the operational clock signals, digital timing signals also stop. Furthermore, power to the flash ROM of the electronic device could be cut off by the signals sent to the oscillator, the clock pulse generator or the multi-enable module from the power control circuit as well.

Abstract: An apparatus and a method for generating an ATIP data are provided. The apparatus, based on a wobble signal generated by reading a re-writable compact disc, generates an ATIP data; the apparatus includes: a frequency demodulator for demodulating the wobble signal to generate an original ATIP data signal; an ATIP clock generating circuit for generating an ATIP clock signal based on the wobble signal; and a data generating circuit, coupled to the frequency demodulator and the ATIP clock generating circuit, for generating the ATIP data based on the number of the original ATIP data signal at a first logic level during one period of the ATIP clock signal. This apparatus uses the number of the original ATIP data signal at a first logic level during one period of the ATIP clock signal and the bi-phase rule to precisely generate the ATIP data.

Abstract: A read only memory circuit for debugging and updating, the circuit includes read only memory, debug program memory, program counter, and compare and load unit. In the circuit, the compare and load unit detects instruction-read-memory-address from the program counter. If the instruction-read-memory-address is a predetermined main program address, the compare and load unit serves to transmit a debug address in the debug program memory to the program counter to update the original instruction-read-memory-address for debugging.

Abstract: A method for generating a wobble clock signal. When the wobble signal becomes deformed or a defect on the optical disc is found, the present invention provides a stable wobble clock signal, which is used to maintain a stable rotation speed when the optical disc is processed. In addition, the present invention also determines whether the wobble signal is deformed according to the result of comparing the width of the wobble signal at different status with the average of the half cycle width of the wobble signal.

Abstract: A power-saving control circuitry of an electronic device is provided. The power-saving control circuitry comprises a power control circuit, an oscillator, a clock pulse generator, a reserve circuit and a multi-enable module. When the electronic device enters a power saving mode, the oscillator stops generating oscillatory timing signals and the clock pulse generator stops generating operational clock signals. Because digital timing signals are generated by either the oscillatory timing signals or the operational clock signals, digital timing signals also stop. Furthermore, power to the flash ROM of the electronic device could be cut off by the signals sent to the oscillator, the clock pulse generator or the multi-enable module from the power control circuit as well.