Layout structure for providing stable power source to a main bridge chip substrate and a motherboard
This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.
This application claims the priority benefits of U.S. provisional application titled” “BALLOUT AND SUBSTRATE DESIGN SCHEME FOR CHIPSETS” filed on Aug. 28, 2001, Ser. No. 60/315,521. All disclosure of this application is incorporated herein by reference. This application also claims the priority benefit of Taiwan application serial no. 91103102, filed Feb. 22, 2002.
BACKGROUND OF THE INVENTION1. Field of Invention
This invention relates to a layout structure for providing a stable power source. More particularly, this invention relates to a layout structure for providing stable power source to a main bridge chip substrate and a motherboard.
2. Description of Related Art
With fast developing technology, the operation speed of computers is getting faster and faster. Taking Intel Pentium 4 as an example, the CPU bus speed can reach 532 MHz (133 MHz×4). This means that the main bridge chip is required to provide higher bus speed on other buses to work with the peripheral components connected to it. The buses include the memory bus with the speed of 333 MHz (166 MHz×2), the AGP bus with the speed of 528 MHz (66 MHz×8) and the main-subalternate connecting bus with the speed of 66 MHz×8. In addition to the high operation speed in requirement, the layout of the main bridge chip substrate as well as the motherboard have to be well designed in order to achieve stable operations for the above devices. Normally, certain design sequences have to be followed during designing the layout of the main bridge chip and motherboard. For example, in order to stabilize a good signal quality on the signal layer, a ground layer has to be provided on the main bridge chip substrate or the motherboard, close to the signal layer, so that all the signals on the signal layer can be referenced to the ground layer.
However, the existing signal-referencing method mentioned above often has some problems depending on how the layout is designed for the main bridge chip substrate and the motherboard.
In
Even though the conventional power layer 13 is partitioned in plane according to the layout in
The invention is to provide a layout structure of a motherboard by using a layout of decoupling capacitors to achieve stable power supply for chips operating under high speeds.
In the preferred embodiments of the motherboard in this invention, on the power ring and power path of the top signal layer as well as the bottom soldering layer where the main bridge chip is placed, decoupling capacitors are cross-connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. Each power path bonding pad/solder ball connected through the decoupling capacitor to the ground bonding pad/solder ball can be the closest power path bonding pad/solder ball to the ground bonding pad/solder ball, and each decoupling capacitor can be connected with multiple power path bonding pads/solder balls with multiple ground bonding pads/solder balls.
Furthermore, on the main bridge chip substrate of this invention, the decoupling capacitors can be placed at the four corners of the circuit layout region, and at the same time, avoid bonding wires. In addition, the decoupling capacitors can be placed underneath the substrate and bonding wires, or they can be packaged together with the main bridge chip into the molding compound, according to the actual design.
BRIEF DESCRIPTION OF DRAWINGSThe invention can be more fully understood by reading the following detailed description of the preferred embodiments. With reference made to the accompanying drawings, wherein:
Referring to
In
According to the power path layout in
It should be noted that, in the preferred embodiments of this invention, the power path is located at both sides of the memory working connection region 302, unlike the CPU and AGP working connection regions 301, 304 where the power path 301B and 304B are at the center of all the working connection regions. This is because the memory working connection region 302 is where the bonding pads/solder balls are disposed for connecting the main bridge to the memory, and the memory (for example SDRAM) usually has two power ports. Therefore, the power paths 302B and 302C are specially designed according to the two power ports respectively, thereby assuring the inductance level of the memory working connection region 302 does not have large variation.
In another preferred embodiment of the invention, in order to provide a stable motherboard operation voltage to the related interfaces, decoupling capacitors are properly connected between the power layouts and the ground bonding pads.
Practically, the location of the decoupling capacitors can vary according to the actual practice. For instance, the decoupling capacitors can be arranged under the bonding wires, or can be packaged into the molding compound. Referring to the cross section in
In summary, this invention discloses a layout structure for a four-layers of a motherboard and a main bridge chip substrate. The decoupling capacitors, which are located on the motherboard at the top signal layer for arranging the main bridge chip substrate, and at the power rings and the power paths of the bottom solder layer, are connected between the power bonding pads/solder balls and the closest one of the ground bonding pads/solder balls. Thereby, the invention provides stable operation power source for the interfaced devices and dies. Furthermore, the decoupling capacitors in one preferred embodiment can be disposed, according to real practice, at the four corners of the power ring, or underneath the bonding wires, or even packaged inside the molding compound together with the main bridge chip. This allows a great flexibility for the layout structure design.
Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims
1. A layout structure for a main bridge chip on a motherboard for providing a stable power source to the main bridge chip substrate and the motherboard, the layout structure comprising:
- a plurality of reference bonding pads;
- a plurality of decoupling capacitors, wherein each of the decoupling capacitors is coupled with at least one of the reference bonding pads; and
- a plurality of operation working connection regions, wherein each of the operation working connection regions further comprises at least one power layout layer, wherein the power layout layer at least comprises a power bonding pad, which is coupled with at least one of the decoupling capacitors.
2. A layout structure according to claim 1, wherein the power layout layer comprises:
- at least one power path, wherein each of the power bonding pads include a power bonding pad, which is coupled with at least one of the decoupling capacitors; and
- a power ring which is coupled with the power path, wherein each the power ring includes at least a power bonding pad that is coupled with at least one of the decoupling capacitors.
3. A layout structure according to claim 2, wherein each of the reference bonding pads connected through the decoupling capacitors to the power bonding pads is a closest one of the reference bonding pads on a side of the power path to the power bonding pad, wherein each one of the reference bonding pads connected through the decoupling capacitors to the power bonding pads is a closest one of the reference bonding pads on a side of the power ring to the power bonding pads.
4. A layout structure according to claim 2, wherein the decoupling capacitors are disposed at outside of corners of a ring shaped structure formed by a plurality of the power rings.
5. A layout structure according to claim 2, further comprising a voltage referencing bonding pad region residing about at the center of the structure, such that the ring shaped structure is at outside of the voltage referencing bonding pad region.
6. A layout structure according to claim 1, wherein a part of the decoupling capacitors are disposed underneath bonding wires of the main bridge chip.
7-14. (canceled)
15. A power layout structure of a main bridge chip on a motherboard for providing a stable power source to the main bridge chip substrate and the motherboard, comprising:
- a first signal layer which is on top of the layout structure of the main bridge chip, wherein the first signal layer includes at least one power layout layer, wherein the power layout layer further includes at least one decoupling capacitor which is connected between the power layout layer and one of reference bonding pads on a side of the power layout layer;
- a bottom solder layer which is at bottom of the layout structure of the main bridge chip, wherein the bottom solder layer includes at least one power layout layer, wherein the power layout layer further includes at least one decoupling capacitor which is connected between the power layout layer and at least one of reference solder balls on a side of the power layout layer, where the reference bonding pads and the reference solder balls are coupled with a reference voltage source;
- a first voltage reference layer located underneath the first signal layer, wherein the first voltage reference layer is coupled with the reference voltage source to provide a reference voltage to the first signal layer; and
- a second voltage reference layer located on top of the bottom solder layer, wherein the second voltage reference layer is coupled with the reference voltage source to provide a reference voltage to the bottom solder layer.
16. A power layout structure according to claim 15, wherein the first signal layer comprises a plurality of operation working connection regions, and each of the operation working connection regions include a power path.
17. A power layout structure according to claim 16, wherein the decoupling capacitors are connected between the power bonding pads of the power path and the reference bonding pads located on a side of the power path.
18. A power layout structure according to claim 17, wherein each of the reference bonding pads connected through the decoupling capacitors to the power bonding pads is a closest one of the reference bonding pads on a side of the power path to the power bonding pad.
19. A power layout structure according to claim 16, wherein the bottom solder layer is symmetrically configured according to the first signal layer, and a power layout of the first signal layer is symmetric to that of the bottom solder layer.
20. A power layout structure according to claim 19, wherein the decoupling capacitors are connected between the power solder balls of the power path in the bottom solder layer and the reference solder balls located on the sides of the power path.
21. A power layout structure according to claim 19, wherein each of the reference solder balls connected through the decoupling capacitor to the power solder ball is a closest one of the reference solder balls on aside of the power path to the power solder balls.
22. A power layout structure according to claim 16, wherein the first signal layer further includes a voltage reference bonding pad region for coupling with the reference voltage source, and each power path is connected with a power ring, wherein the power rings are disposed about at a center of the power layout structure of the main bridge chip, and all the power rings form a ring-shaped structure surrounding at outside of the reference voltage bonding pad region.
23. A power layout structure according to claim 22, wherein the decoupling capacitors and connected between the power bonding pads of the power ring and the reference bonding pads located on the sides of the power ring.
24. A power layout structure according to claim 22, wherein a voltage reference solder ball region is disposed on the bottom solder layer, according to the voltage reference bonding pad region of the first signal layer, where the voltage reference solder ball region is coupled with the reference voltage source, and each power path of the bottom solder layer is connected with a power ring, where the power ring of the bottom solder layer is placed close to the center of the power layout structure of the main bridge chip, and all the power rings of the bottom solder layer form a ring-shaped structure surrounding at the outside of the reference voltage solder ball region.
25. A power layout structure according to claim 24, wherein the decoupling capacitors are connected between the power solder balls of the power ring in the bottom solder layer and the reference solder balls which are located on a side of the power ring.
Type: Application
Filed: Aug 2, 2005
Publication Date: Dec 1, 2005
Inventors: Nai-Shung Chang (Taipei Hsien), Shu-Hui Chen (Taipei Hsien), Tsai-Sheng Chen (Taipei Hsien), Chia-Hsing Yu (Taipei Hsien)
Application Number: 11/196,039