Semiconductor devices with high voltage tolerance
The present invention provides improve device designs for high voltage tolerance and methods for making the same. In one embodiment, a low doped drain extension (LDD) region is extended to sustain higher voltages with minimal extra space and processing. In another example, a trench isolation barrier is placed between the gate and an active region in a well. In another example, an additional trench isolation barrier is placed under the middle of the gate. The trench is filled with dielectric such as oxides, with a small upper portion replaced with recrystallized silicon. These disclosed transistor devices can have parameters controlled so that predetermined performances of the transistor devices can be achieved.
The present application claims the benefits of U.S. Provisional Application No. 60/579,044, which was filed on Jun. 12, 2004, and entitled “Edge-triggered flip-flop design and semiconductor devices with high voltage tolerance”, the entirety of which is hereby incorporated by reference herein.
BACKGROUNDThe present disclosure relates generally to semiconductor device designs, and more particularly to semiconductor devices with high voltage tolerance.
Semiconductor devices such as integrated circuits (IC) operate at a variety of voltages. Since a given IC may be subjected to two or more voltages, the manufacturer is faced with the challenge of economically producing ICs with parts that can withstand different voltages. High voltage typically requires extra space for extra structures and extra process steps. In addition, processing requirements may be incompatible with those of standard voltage devices.
One issue with respect to high voltage operation is that high voltage may change the performance and operational parameters of metal-oxide-semiconductor field-effect-transistors (MOSFETs) contained in the IC. Specifically, high voltage junctions have steep electric fields which can accelerate electrons to such energy levels that, as hot electrons, they may be injected into the gate oxide where they may cause damage directly, or they may reside and change the effective charge on the gate. The net effect is that the threshold voltage of the MOSFET may be changed, thereby changing the performance and operational parameters of the IC. Another issue in high voltage MOS devices is the drain junction that needs to sustain high voltage applied to the drain without breaking down the drain junction or punching through the channel.
One partial solution is to use drain extended transistors, which are specifically designed to withstand higher voltages. In such a device, the heavily doped region for drain contact is placed at a distance from the gate and within a well of the same type doping. The well distributes the high voltage over a greater distance. Another partial solution is to use thicker gate oxide, which are specifically designed to withstand higher voltages. However, extra and incompatible processing steps may be required to yield thicker gate oxide, thereby increasing processing complexity and cost. If a long channel is used, space and speed are sacrificed.
Desirable in the art of semiconductor designs are additional designs that yield a more space-efficient and more process-compatible high voltage tolerant MOS structure.
SUMMARYIn view of the foregoing, this disclosure provides circuits and methods to improve device designs for high voltage tolerance. In one embodiment, a low doped drain extension (LDD) region is extended to sustain higher voltages with minimal extra space and processing. In another example, the drain of an NMOS is placed inside an N-well and the drain contact is separated from the channel by a trench isolation. In yet another example, an additional trench isolation barrier is placed under the mid of the gate. The trench is filled with dielectric such as oxides, with a small upper portion replaced with recrystallized silicon. These disclosed transistor devices can have parameters controlled so that predetermined performances of the transistor devices can be achieved.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
This present disclosure provides a detailed description of more space-efficient and more process-compatible MOS structures that may withstand a high operating voltage without a significant increase in processing or material cost. In one example, a low doped drain (LDD) region is extended to sustain higher voltages with minimal extra space and processing. In another example, the drain of a PMOS is placed inside an N-well and the drain contact is separated from the channel by a trench isolation. Some relationships between device parameters are needed to improve the performance of the device. In yet another example, an additional trench isolation barrier is placed under the middle of the gate. The trench is filled with dielectric such as oxides, with a small upper portion replaced with recrystallized silicon which acts as a pseudo silicon-on-insulator (SOI) structure. These disclosed transistor devices can have parameters controlled so that predetermined performances (such as with certain tolerance of high voltage) of the transistor devices can be achieved.
As shown in
It is understood that the same configuration can be applied to a typical P-channel MOSFET with an uneven LLD for the source and drain structures. Similar to what is illustrated in
Three parameters can be used to adjust voltage sustaining capability and other device performance. In this example, the gate width is referred to as d0. The distance between the gate edge to the N+ drain edge, d1, determines the extrinsic drain resistance. This resistance further depends on the N-well concentration and also on the STI depth. The length of the side diffusion of the N-well into the channel, d2 (which is between the edge of the gate within the N-well to the edge of the channel outside of the N-well), affects the intrinsic drain resistance. This resistance also depends on the N-well concentration. The actual channel length, d3, determines the active channel region. It is noted that this device behaves like a drain with a junction as deep as the N-well. Therefore, the channel length d3 may not be shorter than a necessary minimum length to induce punch through. As it is known in the art, such a minimum length can be determined through simulation. These three parameters can appropriately adjust the performance of the formed device. To ensure proper operation, the preferred relationship among three parameters are that d1 is no shorter than 0, and d3 is no shorter than d2.
Similar to what is illustrated in
A further enhancement of these devices may be realized with the addition of a third STI structure in the middle, in accordance with an example of the present disclosure. This oxide barrier will be constructed across the middle of the channel. The advantages in high voltage applications will become apparent in the following discussion.
In
This short section of the recrystallized silicon material 502 is part of the MOS channel. It functions as a pseudo SOI structure. The depletion region of the drain that is formed by the LDD 812 and the P+ drain 808, when reverse biased, may be blocked from reaching the source 806 by the STI 404. Thus, this device can sustain higher voltage. The containment of the depletion region means less junction surface area and therefore less electrical leakage. This structure allows shorter channel lengths to be formed with good control and with less chance of punch through.
The same structure may also be constructed as an N-channel MOSFET with certain changes. One option is to reverse all P-type and N-type labels, including changes from N-type well to P-type well, and from P-type substrate to N-type substrate. A preferred option would retain the P-type substrate. Also, the P-type LDD and P+ source and drain would change to N-type LDD and N+ source and drain. In addition, the N-well may no longer be necessary.
The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and processes are described to help clarify the disclosure. These are, of course, merely examples and are not intended to limit the disclosure from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the disclosure, as set forth in the following claims.
Claims
1. A high voltage transistor comprising:
- a first active region on a first side of a gate in a substrate;
- a second active region on a second side of the gate in the substrate;
- a first low doped region formed between the gate and the first active region; and
- a second low doped region formed between the gate and the second active region with a length substantially longer than that of the first low doped region.
2. The transistor of claim 1 the second active region is a drain of the transistor.
3. The transistor of claim 1 wherein the first low doped region is substantially under the gate and a spacer on the first side of the gate, while the second low doped region is partially under the gate and a spacer on the second side of the gate.
4. The transistor of claim 1 wherein the second low doped region is at least 0.2 um longer than the first low doped region.
5. The transistor of claim 1 wherein the first low doped region has a lateral length less than about 0.3 um.
6. The transistor of claim 1 wherein the second low doped region has a lateral length less than about 0.7 um.
7. A high voltage transistor comprising:
- a first active region formed on a first side of a gate and in a well of a predetermined type within a substrate;
- a second active region on a second side of the gate; and
- a trench isolation (TI) of a predetermined depth formed within the well between the first active region and the gate,
- wherein the well containing the first active region functions as a drain of the transistor.
8. The transistor of claim 7 wherein the well is an N well if the transistor is an NMOS transistor.
9. The transistor of claim 7 wherein the well is a P well if the transistor is a PMOS transistor.
10. The transistor of claim 7 wherein a performance of the transistor is determined by a distance (d1) between an edge of the gate to an edge of the first active region, which affects a drain resistance.
11. The transistor of claim 10 wherein the drain resistance is further affected by an electron or hole concentration of the well.
12. The transistor of claim 10 wherein the performance of the transistor is further affected by a distance (d2) between an edge of the gate in the well and the edge of the channel outside of the well.
13. The transistor of claim 12 wherein a channel length of the transistor is larger than d2.
14. A semiconductor transistor comprising:
- a gate;
- a source region formed in a substrate on a first side of the gate;
- a drain region formed in the substrate on a second side of the gate; and
- a trench isolation placed in the substrate between the source and drain regions underneath the gate with a predetermined top portion thereof forming a portion of a channel between the source and drain region.
15. The transistor of claim 14 wherein the top portion of the trench isolation includes a crystallized silicon material.
16. The transistor of claim 14 further comprising a first and second shallow trench isolations (STI) on the first and second sides of the gate respectively for defining a boundary of the transistor.
17. The transistor of claim 14 further comprising a first and second low doped drain extension regions overlapping at least a portion of the drain and source regions respectively.
18. A method for forming a transistor comprising:
- forming at least three trenches in a substrate with a center trench surrounded by two boundary trenches;
- filling the three trenches with a predetermined dielectric material;
- placing a predetermined silicon material in a predetermined top portion of the center trench;
- crystallizing the placed silicon material;
- forming a gate over the substrate and substantially centered around the center trench; and
- forming a source and a drain regions on both sides of the gate and next to the respective boundary trench.
19. The method of claim 18 wherein the placing further includes removing the dielectric material from the predetermined top portion of the center trench.
20. The method of claim 18 further comprising forming a first and second low doped drain extension regions overlapping at least a portion of the drain and source regions respectively.
21. The method of claim 18 further wherein forming the gate comprising forming two spacers on two sides of the gate.
22. The method of claim 18 further comprising forming a well around the three trenches.
Type: Application
Filed: Mar 11, 2005
Publication Date: Dec 15, 2005
Inventor: Shine Chung (San Jose, CA)
Application Number: 11/077,606