Stepped gate configuration for non-volatile memory
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.
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The present invention relates generally to memory devices and in particular, the present invention relates to field effect transistors having a stepped gate dielectric.
BACKGROUND OF THE INVENTIONMemory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. One type of flash memory is a nitride read only memory (NROM). NROM has some of the characteristics of flash memory but does not require the special fabrication processes of flash memory. NROM integrated circuits can be implemented using a standard CMOS process.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
As the size of memory devices shrinks, so too does the charge trapping capacity of those devices. And, as the charge trapping capacity shrinks, so does the threshold voltage difference that differentiates the programmed states of the device. Because variations in the operational characteristics of these ever-shrinking memory devices can have serious effects on the ability of the memory devices to perform reliably, it is important to enhance the charge trapping ability of these memory devices. In this way, the effect of variations in the operational characteristics of a memory device can be more easily accommodated and it will be possible to more reliably discriminate between the programmed states of the device. Accordingly, there is a need for an improved memory device having an enhanced charge trapping ability.
BRIEF SUMMARY OF THE INVENTIONA memory device of the present invention may be realized in the provision of a field effect transistor that has a stepped gate dielectric. One embodiment of the present invention has a gate dielectric layer that is disposed between two charge trapping layers on a semiconductor substrate. The gate dielectric layer is generally thinner than the charge trapping layers that border it. A control gate overlies the gate dielectric and charge trapping layers.
One embodiment of the memory device of the present invention may be made by first forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed in the charge trapping dielectric layer and a gate dielectric is formed therein. A gate conductor is then formed to overlie the charge trapping dielectric layer and the gate dielectric. The charge trapping layer is then trimmed back to the edge of the gate conductor.
The invention further provides methods and apparatus of varying scope.
DESCRIPTION OF THE DRAWINGS
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms substrate or substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a substrate or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms substrate or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.
Once the charge trapping dielectric layer 12 has been formed, an etch stop layer 14 will preferably be deposited onto the charge trapping dielectric layer 12. Note that the etch stop layer 14 is itself optional in that careful selection of subsequent etching processes may obviate the need for a distinct etch stop layer 14. In some instances, however, if it is found that the etch stop layer 14 is beneficial to the operation of the transistor 10, this layer, or some portion thereof, may remain part of the structure of the transistor 10. Examples of some suitable materials that may form the etch stop layer 14 include, but are not limited to, titanium nitride and Al2O3. A sacrificial layer 16, preferably of silicon nitride, is applied over the etch stop layer 14 to act as a hard mask. To the extent that the etch stop layer 14 is later removed, the total thickness of the sacrificial layer 16 and any remaining portion of the etch stop layer 14, taken together, can define the height of the control gate 30.
After the remaining photoresist layer 18 has been removed, a layer of silicon dioxide or another suitable sacrificial material such as, for example TEOS oxide, is deposited over the sacrificial layer 16 to form spacers 24. As one example, a spacer layer 17 could be blanket deposited over layers 12, 14, and 16 as shown in
Following the formation of the spacers 24, an ion, plasma, or other directional removal process may then be employed to form a groove 26 through the charge trapping layer 12 as shown in
Once the gate dielectric 28 is formed and the spacers 24 removed, a gate conductor 30 is formed in the groove 22 as shown in
As described above, one or more intervening layers may be formed over the gate dielectric 28 and/or the charge trapping layers 12. Such intervening layers may or may not, depending on the application, remain in place after the gate conductor 30 is formed overlying the gate dielectric 28 and/or charge trapping layers 12. These intervening layers may include adhesion layers or barrier layers that provide or promote compatibility between device layers, protect against the migration of reactive materials, improve reliability of the device, etc.
Once the sacrificial layer 16 has been removed, a final removal step may be undertaken to trim the charge trapping layers 12a and 12b and any remaining portions of the etch stop layer 14, if present, flush with the sides of the gate conductor 30. This etching step is preferably carried out using a suitable directional dry etching process. Where appropriate, the gate conductor 30 may itself be used as the mask for this etching step, or a photoresist layer (not shown) may be applied and developed to provide a suitable mask for the etch. Once the structure of the field effect transistor 10 has been completed, source 34 and drain 36 may be formed by doping the substrate 11 with a suitable dopant such as boron, for a p-type transistor, or phosphorus or arsenic, for an n-type transistor.
Non-volatile memory cells in accordance with the invention are suitable for use in a variety of memory array types. One example is a NAND memory array.
Memory array 200 includes NAND strings 2061 to 206M. Each NAND string includes field effect transistors 101 to 10N, each located at an intersection of a word line 202 and a local bit line 204. The field effect transistors 10 represent non-volatile memory cells for storage of data. The field effect transistors 10 of each NAND string 206 are connected in series source to drain between a source select gate 210 and a drain select gate 212. The source and drain select gates 210, 212 may be field effect transistors constructed according to an embodiment of the present invention or may be another suitable device. Each source select gate 210 is located at an intersection of a local bit line 204 and a source select line 214, while each drain select gate 212 is located at an intersection of a local bit line 204 and a drain select line 215.
A source of each source select gate 210 is connected to a common source line 216. The drain of each source select gate 210 is connected to the source of the first field effect transistor 10 of the corresponding NAND string 206. For example, the drain of source select gate 2101 is connected to the source of field effect transistor 101 of the corresponding NAND string 2061. A control gate 220 of each source select gate 210 is connected to source select line 214.
The drain of each drain select gate 212 is connected to a local bit line 204 for the corresponding NAND string at a drain contact 228. For example, the drain of drain select gate 2121 is connected to the local bit line 2041 for the corresponding NAND string 2061 at drain contact 2281. The source of each drain select gate 212 is connected to the drain of the last field effect transistor 10 of the corresponding NAND string 206. For example, the source of drain select gate 2121 is connected to the drain of field effect transistor 10N of the corresponding NAND string 2061.
As described above in conjunction with
Another example of an array type suitable for use with memory cells in accordance with the invention is a NOR memory array.
Field effect transistors 10 are in this embodiment located at each intersection of a word line 302 and a local bit line 304. The field effect transistors 10 represent non-volatile memory cells for storage of data. As described above, typical construction of such field effect transistors 10 includes a source 34 and a drain 36, and a control gate 30.
Field effect transistors 10 having their control gates 30 coupled to a word line 302 typically share a common source depicted as array source 318. As shown in
To reduce problems associated with high resistance levels in the array source 318, the array source 318 is regularly coupled to a metal or other highly conductive line to provide a low-resistance path to ground. The array ground 320 serves as this low-resistance path.
It is to be noted that the memory cells of memory arrays 200, 300 may be programmed to correspond to single bit or multi-bit operation. Programming and sensing of charge-trapping memory cells is well understood in the art and will not be detailed herein.
CONCLUSIONThe formation of memory cells having a stepped gate have been described herein to facilitate increases in charge trapping capacity generally independent of gating characteristics. Although specific embodiments have been illustrated and described herein it is manifestly intended that this invention be limited only by the following claims and equivalents thereof.
Claims
1. A non-volatile memory cell, comprising:
- a stepped gate dielectric disposed on a semiconductor substrate, the stepped gate dielectric comprising: two charge trapping dielectrics disposed on the semiconductor substrate, the charge trapping dielectrics being spaced apart from one another; and, a distinct gate dielectric disposed on the semiconductor substrate between the charge trapping dielectrics so as to entirely separate the charge trapping dielectrics;
- a gate conductor disposed over the stepped gate dielectric; and,
- source/drain regions formed in the semiconductor substrate at opposing ends of the stepped dielectric.
2. The non-volatile memory cell of claim 1 wherein the charge trapping dielectrics comprise multiple component layers of dielectric material.
3. The non-volatile memory cell of claim 2 wherein the charge trapping dielectrics comprise a first component layer of silicon dioxide and a second component layer of silicon nitride.
4. The non-volatile memory cell of claim 1 wherein the gate dielectric is at most the same thickness as the charge trapping dielectrics.
5. The non-volatile memory cell of claim 1 wherein the gate dielectric and the charge trapping dielectrics are fashioned of different materials.
6. The non-volatile memory cell of claim 1 wherein the gate dielectric and the charge trapping dielectrics are fashioned of the same materials and wherein the thickness of the gate dielectric and charge trapping dielectrics are different.
7. The non-volatile memory cell of claim 1 further comprising an etch stop layer disposed between the charge trapping dielectrics and the gate conductor.
8. The non-volatile memory cell of claim 1 wherein the non-volatile memory cell is adapted to store a single bit of data.
9. The non-volatile memory cell of claim 1 wherein the non-volatile memory cell is adapted to store multiple bits of data.
10. The non-volatile memory cell of claim 1 wherein the non-volatile memory cell is part of a NOR memory array.
11. The non-volatile memory cell of claim 1 wherein the non-volatile memory cell is part of a NAND memory array.
12. A method of fabricating a non-volatile memory cell, comprising:
- forming a charge trapping dielectric layer on a semiconductor substrate;
- forming a first sacrificial layer over the charge trapping dielectric layer;
- applying a mask to the sacrificial layer to define the lateral boundaries of a groove;
- removing that portion of the first sacrificial layer within the lateral boundaries defined by the mask to form the groove, the groove having a lower boundary that is substantially the upper surface of the charge trapping dielectric layer;
- forming a second sacrificial layer over the first sacrificial layer and the exposed charge trapping dielectric layer;
- forming a pair of spacers within the groove by anisotropically removing a portion of the second sacrificial layer, the pair of spacers being positioned against the respective lateral edges of the groove and defining therebetween the lateral boundaries of a trench within the groove;
- removing the material of the charge trapping layer between the lateral boundaries defined by the spacers to form a trench, the trench having a lower boundary that is substantially the upper surface of the semiconductor substrate;
- depositing a gate dielectric layer in the trench;
- removing the spacers from the groove;
- forming a control gate layer overlying the charge trapping dielectric layer and the gate dielectric layer within the groove formed in the first sacrificial layer; and,
- patterning the control gate layer and the remainder of the charge trapping control layers that extend beyond the lateral edges of the control gate layer.
13. The method of fabricating a non-volatile memory cell of claim 12 further comprising the step of forming an etch stop layer over the charge trapping dielectric layer.
14. The method of fabricating a non-volatile memory cell of claim 13 wherein the etch stop layer is substantially removed during the formation of the groove in the first sacrificial layer.
15. The method of fabricating a non-volatile memory cell of claim 13 wherein at least a portion of the etch stop layer remains after the formation of the groove in the first sacrificial layer.
16. The method of fabricating a non-volatile memory cell of claim 12 wherein the charge trapping dielectric layer is comprised of a first component layer and a second component layer.
17. The method of fabricating a non-volatile memory cell of claim 16 wherein the first component layer of the charge trapping dielectric layer is of silicon dioxide and the second component layer of the charge trapping dielectric layer is of silicon nitride.
18. The method of fabricating a non-volatile memory cell of claim 12 wherein the gate dielectric layer is no thicker than the charge trapping dielectric layer.
19. A memory device, comprising:
- an array of non-volatile memory cells; and
- circuitry for control and/or access of the array of non-volatile memory cells;
- wherein the at least one memory cell of the array of non-volatile memory cells comprises:
- a stepped gate dielectric disposed on a semiconductor substrate, the stepped gate dielectric comprising: two charge trapping dielectrics disposed on the semiconductor substrate, the charge trapping dielectrics being spaced apart from one another; and, a distinct gate dielectric disposed on the semiconductor substrate between the charge trapping dielectrics so as to entirely separate the charge trapping dielectrics;
- a gate conductor disposed over the stepped gate dielectric; and,
- source/drain regions formed in the substrate at opposing ends of the stepped dielectric, the respective source/drain regions being in conductive contact with the respective charge trapping dielectrics.
20. An electronic system, comprising:
- a processor; and
- an array of non-volatile memory cells; and
- circuitry for control and/or access of the array of non-volatile memory cells;
- wherein the at least one memory cell of the array of non-volatile memory cells comprises: a stepped gate dielectric disposed on a semiconductor substrate, the stepped gate dielectric comprising: two charge trapping dielectrics disposed on the semiconductor substrate, the charge trapping dielectrics being spaced apart from one another; and, a distinct gate dielectric disposed on the semiconductor substrate between the charge trapping dielectrics so as to entirely separate the charge trapping dielectrics; a gate conductor disposed over the stepped gate dielectric; and, source/drain regions formed in the substrate at opposing ends of the stepped dielectric, the respective source/drain regions being in conductive contact with the respective charge trapping dielectrics; and,
- circuitry for control and/or access of the array of non-volatile memory cells.
21. A memory cell, comprising:
- first and second charge trapping layers overlying a semiconductor substrate;
- a gate dielectric layer overlying the semiconductor substrate and interposed between the first and second charge trapping layers, wherein the first and second charge trapping layers each extend above the gate dielectric layer; and
- a control gate layer overlying the gate dielectric layer and the first and second charge trapping layers.
22. The memory cell of claim 21, wherein the first and second charge trapping layers comprise a dielectric material.
23. The memory cell of claim 22, wherein the dielectric material is selected from the group consisting of silicon dioxide, silicon nitride, Al2O3, HfO2, HfON, HfOSiN, and Ta2O5.
24. The memory cell of claim 21, wherein the control gate layer comprises one or more layers of conductive material.
25. The memory cell of claim 21, further comprising one or more adhesion or barrier layers between the gate dielectric layer and the control gate layer.
26. The memory cell of claim 21, wherein the gate dielectric layer and the first and second charge trapping layers are overlying and adjoining the semiconductor substrate.
27. The memory cell of claim 21, wherein the control gate layer is overlying and adjoining the gate dielectric layer and the first and second charge trapping layers.
28. A memory cell, comprising:
- first and second charge trapping layers overlying a semiconductor substrate;
- a gate dielectric layer overlying the semiconductor substrate and interposed between the first and second charge trapping layers; and
- a control gate layer overlying and adjoining the gate dielectric layer and the first and second charge trapping layers.
29. A method of forming a memory cell, comprising:
- forming a first dielectric layer overlying a semiconductor substrate;
- forming and patterning a hard mask layer overlying the first dielectric layer, thereby exposing a first portion of the first dielectric layer bounded by sidewalls of the hard mask layer;
- forming spacers on the sidewalls of the hard mask layer, leaving a central portion of the first portion of the first dielectric layer exposed between the spacers;
- removing the central portion of the first portion of the first dielectric layer, thereby exposing a portion of the substrate;
- forming a second dielectric layer on the exposed portion of the substrate;
- removing the spacers from the sidewalls of the hard mask layer;
- forming a control gate layer overlying the first and second dielectric layers;
- removing the hard mask layer; and,
- forming source and drain regions in the substrate on opposing sides of the control gate layer.
30. The method of claim 29, wherein the method is performed in the order presented.
31. The method of claim 29, wherein forming the first dielectric layer further comprises:
- forming a first layer of dielectric material overlying and adjoining the substrate; and
- forming a second layer of dielectric material overlying and adjoining the first layer of dielectric material.
Type: Application
Filed: Aug 27, 2004
Publication Date: Mar 2, 2006
Applicant:
Inventors: H. Manning (Eagle, ID), Kunal Parekh (Boise, ID)
Application Number: 10/928,082
International Classification: H01L 29/788 (20060101);