Semiconductor device and method for fabricating the same
The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.
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This application is related to Japanese Patent Application No. 2004-279076 filed on Sep. 27, 2004, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTIONThe present invention relates to semiconductor devices and methods for fabricating the devices, and more particularly relates to a MIS semiconductor device which can be reduced in size and has a doped layer having a shallow junction depth and a low resistance, and to a method for fabricating the semiconductor device.
As the number of devices included in a semiconductor integrated circuit continues to increase, MIS transistors are required to be further reduced in size. To that end, MIS transistors need to have a channel doped layer having a shallow junction depth and a low resistance (see Japanese Laid-Open Publication No. 2002-33477, for example.)
Hereinafter, with reference to the accompanying figures, it will be described how to fabricate a semiconductor device including a conventional MIS transistor.
First, as shown in
Next, as shown in
Subsequently, as shown in
Then, as shown in
Next, as shown in
As described above, in order to reduce the size of the transistor without causing short channel effects to be exhibited, the conventional semiconductor-device fabrication method tends to use indium-ion implantation in forming the P-type channel doped layer 103 so as to obtain a channel structure having steep concentration profiles.
SUMMARY OF THE INVENTIONHowever, in the conventional semiconductor-device fabrication method, if indium ions are used as a dopant for forming doped layers such as the P-type channel doped layer 103 or the P-type pocket doped layers 107, a problem occurs in that the activation rate of the indium ions is low and hence sufficient activation concentration cannot be obtained.
If the implantation dose of the indium ions is increased in order to raise the activation concentration of the indium ions, the ion-implanted regions in the semiconductor substrate 100 easily become amorphous, because indium atoms have a high mass number. As a result, transient enhanced diffusion (hereinafter simply referred to as “TED”) occurs, which also produces a problem in that abnormal diffusion of the indium is caused during the TED. Note that TED is an enhanced abnormal diffusion phenomenon, which is caused by interaction between excess point defects existing in the silicon substrate, such as interstitial silicon, vacancies, etc., and dopant atoms. In many cases, those excess point defects are introduced due mainly to implantation damages resulting from ion implantation. Therefore, even if indium ions having a relatively high mass number are implanted in order to obtain a shallower and steeper doped layer, the activation of the implanted indium ions serving as the dopant will be insufficient.
Therefore, with the conventional semiconductor-device fabrication method, it is difficult to form a shallow steep channel doped layer, which is required to reduce the transistor size, in such a manner that the channel doped layer has a sufficient activation concentration.
To address the problems described above, it is therefore an object of the present invention to form a channel doped layer having steep dopant-concentration profiles having a shallow junction, thereby suppressing short channel effects, and also to enable the channel doped layer to be formed having a sufficient activation concentration and a low resistance, thereby realizing a miniaturized device capable of maintaining large driving force.
In order to achieve the above object, according to the present invention, carbon is added to a channel doped layer or pocket doped layers in a semiconductor device so as to increase the activation concentration of the dopant introduced into the channel doped layer or the pocket doped layers.
Specifically, a first inventive semiconductor device includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type, containing carbon as an impurity and formed in the semiconductor region beneath the gate electrode.
In the first inventive semiconductor device, the carbon added to the channel doped layer suppresses transient enhanced diffusion of a dopant in the channel doped layer, while increasing the activation rate of the introduced dopant. Thus, steep dopant-concentration profiles having a shallow junction, which are necessary to reduce the device size, are realized in the channel doped layer, while the sufficiently increased activation concentration permits the channel doped layer to have a low resistance, thereby allowing the semiconductor device to maintain a large driving force.
The first inventive device preferably further includes: sidewalls formed on lateral faces of the gate electrode, and source/drain doped layers of a second conductivity type formed in the semiconductor region alongside the respective sidewalls. The source/drain doped layers preferably do not contain the carbon. Then, the carbon is contained only in the region where the addition of the carbon is necessary, thereby preventing the semiconductor device from being contaminated by the carbon.
In this case, the source/drain doped layers are preferably formed spaced from the channel doped layer.
The inventive first device preferably further includes extended doped layers of a second conductivity type formed in the semiconductor region below the sides of the gate electrode.
In this case, the first inventive device preferably further includes pocket doped layers of the first conductivity type formed in the semiconductor region under and in contact with the extended doped layers.
In the first inventive device, dopant ions introduced into the channel doped layer are preferably heavy ions having a relatively high mass number.
In this case, the heavy ions are preferably indium ions.
A second inventive semiconductor device includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; extended doped layers of a second conductivity type formed in the semiconductor region below the sides of the gate electrode; and pocket doped layers of the first conductivity type, containing carbon as an impurity and formed in the semiconductor region under and in contact with the extended doped layers.
In the second inventive semiconductor device, the carbon added to the pocket doped layers formed below the sides of the gate electrode suppresses transient enhanced diffusion of a dopant in the pocket doped layers, while increasing the activation rate of the introduced dopant. Thus, steep dopant-concentration profiles having a shallow junction, which are necessary to reduce the device size, are realized in the pocket doped layers, while the sufficiently increased activation concentration in the pocket doped layers suppresses depletion in the channel doped layer, thereby making it possible to suppress short channel effects.
The second inventive device preferably further includes: sidewalls formed on lateral faces of the gate electrode, and source/drain doped layers of the second conductivity type formed in the semiconductor region alongside the respective sidewalls. In the source/drain doped layers, regions away from the pocket doped layers preferably do not contain the carbon. Then, the carbon is contained only in the regions where the addition of the carbon is necessary, thereby preventing the semiconductor device from being contaminated by the carbon.
In the second inventive device, dopant ions introduced into the pocket doped layers are preferably heavy ions having a relatively high mass number.
In this case, the heavy ions are preferably indium ions.
In the first or second inventive device, the semiconductor region is preferably made of silicon.
A first inventive method for fabricating a semiconductor device includes the steps of: (a) implanting first dopant ions of a first conductivity type into a semiconductor region of the first conductivity type, thereby forming a channel implantation layer; (b) selectively implanting second dopant ions, which are made of carbon or made of molecules containing carbon, into a channel formation region in the semiconductor region, thereby forming a carbon implantation layer in the channel implantation layer; (c) subjecting, after the steps (a) and (b), the semiconductor region to a first heat treatment so as to cause diffusion of the first dopant ions from the channel implantation layer and the carbon implantation layer, thereby forming a channel doped layer in the semiconductor region; (d) forming a gate insulating film on the channel doped layer in the semiconductor region; and (e) forming a gate electrode on the gate insulating film, wherein the channel doped layer contains the carbon of the second dopant ions.
According to the first inventive semiconductor device fabrication method, the second dopant ions, made of carbon or made of molecules containing carbon, are selectively implanted into the channel formation region in the semiconductor region to form the carbon implantation layer in the channel implantation layer. Therefore, when the channel doped layer is formed through the later heat treatment, the carbon implanted as the impurity into the channel implantation layer suppresses transient enhanced diffusion of the first dopant in the channel doped layer, while increasing the activation rate of the implanted first dopant. As a result, steep dopant-concentration profiles having a shallow junction, which are necessary to reduce the device size, are realized in the channel doped layer, while the sufficiently increased activation concentration permits the channel doped layer to have a low resistance, thereby realizing a miniaturized device capable of maintaining a large driving force.
The first inventive method preferably further includes, between the steps (a) and (b), the step of forming, on the semiconductor region, a mask pattern having an opening that exposes the channel formation region. In the step (b), the second dopant ions are preferably selectively implanted into the channel formation region by using the mask pattern, thereby forming the carbon implantation layer.
The first inventive method preferably further includes, before the step (a), the step of forming, on the semiconductor region, a mask pattern having an opening that exposes the channel formation region. In the step (a), the first dopant ions are preferably selectively implanted into the channel formation region by using the mask pattern, thereby forming the channel implantation layer, and in the step (b), the second dopant ions are preferably selectively implanted into the channel formation region by using the mask pattern, thereby forming the carbon implantation layer.
The first inventive method preferably further includes, after the step (e), the step (f) of forming extended implantation layers by implanting third dopant ions of a second conductivity type into the semiconductor region with the gate electrode used as a mask; and after the step (f), the step (g) of subjecting the semiconductor region to a second heat treatment, thereby forming extended doped layers by diffusion of the third dopant ions from the extended implantation layers.
In this case, the first inventive method preferably further includes, between the steps (e) and (g), the step of implanting fourth dopant ions of the first conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming pocket implantation layers. In the step (g), the second heat treatment preferably causes diffusion of the fourth dopant ions from the pocket implantation layers, thereby forming pocket doped layers under the extended doped layers.
The first inventive method preferably further includes, after the step (e), the step (h) of forming sidewalls on lateral faces of the gate electrode; after the step (h), the step (i) of implanting fifth dopant ions of a second conductivity type into the semiconductor region with the sidewalls used as a mask, thereby forming source/drain implantation layers; and after the step (i), the step (j) of subjecting the semiconductor region to a third heat treatment to cause diffusion of the fifth dopant ions from the source/drain implantation layers, thereby forming source/drain doped layers.
The first inventive method preferably further includes, before the step (a), the steps of: (1) forming a dummy gate electrode on the semiconductor region; (2) forming sidewalls on both lateral faces of the dummy gate electrode; (3) forming, after the step (2), on the semiconductor region, an insulating film from which the upper surface of the dummy gate electrode is exposed; and (4) selectively removing the dummy gate electrode after the step (3), thereby exposing a part of the semiconductor region between the sidewalls. In the step (a), the first dopant ions are preferably implanted into the exposed part of the semiconductor region with the insulating film used as a mask, thereby forming the channel implantation layer; and in the step (b), the second dopant ions are preferably implanted into the exposed part of the semiconductor region with the insulating film used as a mask, thereby forming the carbon implantation layer.
In the first inventive method, the first dopant ions are preferably heavy ions having a relatively high mass number.
In this case, the heavy ions are preferably indium ions.
In the first inventive method, in the step (a), the channel implantation layer preferably does not become amorphous due to the implantation of the first dopant ions.
A second inventive method for fabricating a semiconductor device includes the steps of: (a) forming a gate insulating film on a semiconductor region of a first conductivity type; (b) forming a gate electrode on the gate insulating film; (c) implanting first dopant ions of a second conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming extended implantation layers; (d) implanting second dopant ions of the first conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming pocket implantation layers; (e) selectively implanting third dopant ions, which are made of carbon or made of molecules containing carbon, into pocket formation regions in the semiconductor region, thereby forming carbon implantation layers; and (f) subjecting the semiconductor region to a first heat treatment after the steps (c), (d), and (e) have been performed, whereby diffusion of the first dopant ions from the extended implantation layers is caused to form extended doped layers in the semiconductor region below the sides of the gate electrode, and diffusion of the second dopant ions from the pocket implantation layers is caused to form pocket doped layers under the extended doped layers, wherein the pocket doped layers contain the carbon of the third dopant ions.
According to the second inventive semiconductor device fabrication method, the third dopant ions, made of carbon or made of molecules containing carbon, are selectively implanted into the pocket formation regions in the semiconductor region to form the pocket implantation layers. Therefore, when the pocket doped layers are formed through the subsequent heat treatment, the carbon implanted as the impurity into the pocket implantation layers suppresses transient enhanced diffusion of the second dopant in the channel doped layer, while increasing the activation rate of the implanted second dopant. Thus, steep dopant-concentration profiles having a shallow junction, which are necessary to reduce the device size, are realized in the pocket doped layers, while the sufficiently increased activation concentration in the pocket doped layers suppresses depletion more reliably. As a result, it is possible to suppress short channel effects and hence realize a miniaturized device capable of maintaining a large driving force.
The second inventive method preferably further includes, after the step (f), the step (g) of forming sidewalls on lateral faces of the gate electrode; after the step (g), the step (h) of implanting fourth dopant ions of the second conductivity type into the semiconductor region with the sidewalls used as a mask, thereby forming source/drain implantation layers; and after the step (h), the step (i) of subjecting the semiconductor region to a second heat treatment to cause diffusion of the fourth dopant ions from the source/drain implantation layers, thereby forming source/drain doped layers.
In the second inventive method, the second dopant ions are preferably heavy ions having a relatively high mass number.
In this case, the heavy ions are preferably indium ions.
In the first or second inventive method, the semiconductor region is preferably made of silicon.
BRIEF DESCRIPTION OF THE DRAWINGS
A first embodiment of the present invention will be described with reference to the accompanying drawings.
Sidewalls 108 made of, e.g., silicon nitride (SiNx, for example, Si3N4) are formed on the semiconductor substrate 100 on both lateral faces of the gate insulating film 101 and gate electrode 102.
A P-type channel doped layer 103 is formed in the semiconductor substrate 100 under the gate insulating film 101 and the sidewalls 108, while N-type heavily doped source/drain layers 105 are formed in the semiconductor substrate 100 alongside the respective sidewalls 108.
In the P-type channel doped layer 103, N-type extended doped layers 106 are formed under the respective sidewalls 108, and P-type pocket doped layers 107 are formed under the respective N-type extended doped layers 106.
The first embodiment is characterized in that a carbon-containing region 110, in which carbon (C) is selectively introduced, is formed in the P-type channel doped layer 103 under the gate insulating film 101. The carbon introduced in the P-type channel doped layer 103 suppresses transient enhanced diffusion of the P-type dopant in the P-type channel doped layer 103. In addition, in order to increase the activation rate of the introduced P-type dopant, steep dopant-concentration profiles having a shallow junction are realized in the P-type channel doped layer 103, which is necessary to reduce the transistor size. If the activation rate of the P-type dopant is increased, the P-type channel doped layer 103 has a low resistance, which allows the MIS semiconductor device to maintain a large driving force.
Hereinafter, with reference to the accompanying figures, it will be described how to fabricate a semiconductor device having the above structure.
First, as shown in
Next, as shown in
Subsequently, as shown in
Then, as shown in
Then, as shown in
Next, as shown in
Next, as shown in
Then, as shown in
As described above, according to the first embodiment, indium ions are implanted into the semiconductor substrate 100 to form the P-type channel implantation layer 103A and then carbon ions are selectively implanted into the channel formation region to form the carbon implantation layer 110A in the process steps shown in
In this way, in the first embodiment, after the carbon ions are implanted into the channel formation region in the semiconductor substrate 100, the activation annealing for activating the indium ions contained in the P-type channel implantation layer 103A is performed, whereby the activation rate of the indium ions is increased. Therefore, it is possible to overcome the decrease in the activation of the indium ions caused when the indium ions are used for the P-type channel doped layer 103. In addition, since the carbon ions are selectively implanted into the channel formation region, the carbon is not contained in regions in the semiconductor device where no carbon is necessary, thereby preventing the semiconductor device from being contaminated by the carbon and suppressing junction leakage due to the residual carbon.
Accordingly, it is possible to reliably form the P-type channel doped layer 103 in which a steep shallow junction, a feature of the P-type channel doped layer 103 formed by the indium-ion implantation, is obtained, while a low resistance is achieved by the increased activation of the indium ions.
Second EmbodimentHereinafter, a second embodiment of the present invention will be described with reference to the accompanying figures.
As shown in
Hereinafter, with reference to the accompanying figures, it will be described how to fabricate a semiconductor device having the above structure.
First, as shown in
Next, as shown in
Subsequently, as shown in
In the second embodiment, the series of process steps, consisting of the indium-ion and carbon-ion implantation steps shown in
Next, as shown in
Subsequently, as shown in
Subsequently, as shown in
Next, as shown in
Next, as shown in
As described above, according to the second embodiment, in the process steps shown in
In this way, in the second embodiment, after the carbon ions are implanted into the channel formation region, the activation annealing for activating the indium ions contained in the P-type channel implantation layer 103B is performed, whereby the activation rate of the indium ions is increased. Therefore, it is possible to overcome the decrease in the activation rate of the indium ions caused when the indium ions are used for the P-type channel doped layer 103. In addition, since the carbon ions are selectively implanted into the channel formation region, the carbon is not contained in regions in the semiconductor device where no carbon is necessary, thereby preventing the semiconductor device from being contaminated by the carbon and suppressing junction leakage due to the residual carbon.
Moreover, in the second embodiment, the indium ions and the carbon ions are each implanted in several times so that they are implanted at such doses that do not cause the semiconductor substrate 100 to be amorphized, while the first rapid thermal annealing process is performed for each ion implantation so as to activate the indium ions and restore the crystallinity of the semiconductor substrate 100. Therefore, the ion implantation processes do not cause the semiconductor substrate 100 to become amorphous, and hence problems occurring due to amorphization can be avoided. For example, the present inventor has found that diffusion of indium ions caused with an amorphous-crystal interface being present produces an abnormal diffusion phenomenon, in which segregation of the indium ions occurs in crystal defect layers formed during an annealing process. Nevertheless, in the second embodiment, since the semiconductor substrate 100 does not become amorphous, it is possible to avoid abnormal indium-ion diffusion, even if the total dose of indium ions is increased by implanting the indium ions multiple times.
In cases where the indium ions and the carbon ions are implanted in multiple times, rotation implantation, in which the angle of ion implantation, e.g., the twist angle, is changed for each implantation, may be performed. Also, if the total indium-ion implantation dose is sufficiently smaller than the dose that will cause amorphization, only the carbon ions may be implanted in multiple times.
Accordingly, if the carbon-ion implantation is performed in such a manner as to satisfy the above conditions, it is possible to reliably form the P-type channel doped layer 103 in which a steep shallow junction, a feature of a P-type doped layer formed by indium-ion implantation, is obtained, while a low resistance is achieved by the increased activation of the indium ions.
Third EmbodimentHereinafter, a third embodiment of the present invention will be described with reference to the accompanying figures.
As shown in
Hereinafter, with reference to the accompanying figures, it will be described how to fabricate a semiconductor device having the above structure.
First, as shown in
Next, as shown in
Subsequently, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Subsequently, as shown in
Next, as shown in
Then, as shown in
As described above, according to the third embodiment, in the steps shown in
In this manner, in the third embodiment, the carbon ions are implanted into the channel formation region and then the activation annealing for activating the indium ions contained in the P-type channel implantation layer 103C is performed, whereby the activation of the indium ions is increased even in the fabrication method in which the dummy gate electrode is replaced with the metal gate electrode. Therefore, it is possible to overcome the decrease in the activation rate of the indium ions caused when the indium ions are used for the P-type channel doped layer 103. In addition, since the carbon ions are selectively implanted into the channel formation region, the carbon is not contained in regions in the semiconductor device where no carbon is necessary, thereby preventing the semiconductor device from being contaminated by the carbon and suppressing junction leakage due to the residual carbon.
Accordingly, it is possible to reliably form the P-type channel doped layer 103 in which a steep shallow junction, a feature of a P-type doped layer formed by indium-ion implantation, is obtained, while a low resistance is achieved by the increased activation of the indium ions.
Fourth EmbodimentHereinafter, a fourth embodiment of the present invention will be described with reference to the accompanying figures.
As shown in
Hereinafter, with reference to the accompanying figures, it will be described how to fabricate a semiconductor device having the above structure.
First, as shown in
Next, as shown in
Then, as shown in
Then, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
As described above, according to the fourth embodiment, in the steps shown in
In this manner, in the fourth embodiment, the carbon ions are implanted into the pocket formation regions and then the activation annealing for activating the indium ions contained in the P-type pocket implantation layers 107A is performed, whereby the activation of the indium ions is increased. Therefore, it is possible to overcome the decrease in the activation rate of the indium ions caused when the indium ions are used for the P-type pocket doped layers 107. In addition, since the carbon atoms are selectively implanted into the pocket formation regions, the carbon is not contained in regions in the semiconductor device where no carbon is necessary, thereby preventing the semiconductor device from being contaminated by the carbon and suppressing junction leakage due to the residual carbon.
Accordingly, it is possible to reliably form the P-type pocket doped layers 107 in which a steep shallow junction, a feature of a P-type doped layer formed by indium-ion implantation, is obtained, while a low resistance is achieved by the increased activation of the indium ions.
In the first through fourth embodiments of the present invention, indium ions are used as the dopant ions for the P-type channel doped layer 103. However, instead of the indium ions, ions of boron or ions of an element that is heavier than boron and makes the channel doped layer 103 P-type may be used, or boron ions and ions of such an element may both be used.
Similarly, in each of the foregoing embodiments, indium ions are used as the dopant ions for the P-type pocket doped layers 107. However, instead of the indium ions, ions of boron or ions of an element that is heavier than boron and makes the pocket doped layers 107 P-type may be used, or boron ions and ions of such an element may both be used.
Furthermore, in each embodiment, an N-channel MIS transistor is used as the semiconductor device. Instead of this, however, a P-channel MIS transistor may be used. In the case of using a p-channel MIS transistor, arsenic (As) ions or ions of a Group VB element heavier than arsenic, such as antimony (Sb) ions or bismuth (Bi) ions, for example, may be used as the N-type dopant ions for forming the channel doped layer.
Also, in each embodiment, the carbon implantation layer is formed by implanting ions of carbon. However, carbon may be introduced by changing methane gas or the like to plasma and then by the plasma damage due to the carbon contained in the methane gas in the form of plasma. Also, heavily doped source/drain layers made of strained silicon layers may be formed alongside the sidewalls.
Moreover, in each embodiment, the carbon ions implanted are not limited to carbon atoms, but ions of carbon molecules that contain carbon (for example, CO2) may also be used.
In the structures described in the foregoing embodiments, carbon is added to the channel doped layer or the pocket doped layers. However, in cases in which heavy ions such as indium ions are used for the extended doped layers, carbon may be likewise added to the extended doped layers. Then, during a heat treatment for forming the extended doped layers, the carbon suppresses transient enhanced diffusion of a dopant, while increasing the activation of the dopant. Therefore, the extended doped layers are allowed to have steep dopant profiles having a shallow junction, which is necessary to reduce the device size, while the activation concentration is increased sufficiently, thereby realizing the extended doped layers having a low resistance. As a result, a miniaturized device capable of maintaining a large driving force is realized.
As described above, the semiconductor devices and their fabrication methods according to the present invention allow the channel doped layer or the pocket doped layers to have steep dopant profiles having a shallow junction, which are necessary to reduce the device size, while permitting the activation concentration to be increased sufficiently, thereby realizing a miniaturized device capable of maintaining a large driving force. Therefore, the inventive semiconductor devices and their fabrication methods are particularly applicable, e.g., to MIS semiconductor devices which can be miniaturized and have a low-resistance doped-layer having a shallow junction depth, and to their fabrication methods.
Claims
1. A semiconductor device comprising:
- a gate insulating film formed on a semiconductor region of a first conductivity type;
- a gate electrode formed on the gate insulating film; and
- a channel doped layer of the first conductivity type, containing carbon as an impurity and formed in the semiconductor region beneath the gate electrode.
2. The device of claim 1, further comprising:
- sidewalls formed on lateral faces of the gate electrode, and
- source/drain doped layers of a second conductivity type formed in the semiconductor region alongside the respective sidewalls,
- wherein the source/drain doped layers do not contain the carbon.
3. The device of claim 2, wherein the source/drain doped layers are formed spaced from the channel doped layer.
4. The device of claim 1, further comprising extended doped layers of a second conductivity type formed in the semiconductor region below the sides of the gate electrode.
5. The device of claim 4, further comprising pocket doped layers of the first conductivity type formed in the semiconductor region under and in contact with the extended doped layers.
6. The device of claim 1, wherein dopant ions introduced into the channel doped layer are heavy ions having a relatively high mass number.
7. The device of claim 6, wherein the heavy ions are indium ions.
8. The device of claim 1, wherein the semiconductor region is made of silicon.
9. A semiconductor device comprising:
- a gate insulating film formed on a semiconductor region of a first conductivity type;
- a gate electrode formed on the gate insulating film;
- extended doped layers of a second conductivity type formed in the semiconductor region below the sides of the gate electrode; and
- pocket doped layers of the first conductivity type, containing carbon as an impurity and formed in the semiconductor region under and in contact with the extended doped layers.
10. The device of claim 9, further comprising:
- sidewalls formed on lateral faces of the gate electrode, and
- source/drain doped layers of the second conductivity type formed in the semiconductor region alongside the respective sidewalls,
- wherein in the source/drain doped layers, regions away from the pocket doped layers do not contain the carbon.
11. The device of claim 9, wherein dopant ions introduced into the pocket doped layers are heavy ions having a relatively high mass number.
12. The device of claim 11, wherein the heavy ions are indium ions.
13. The device of claim 9, wherein the semiconductor region is made of silicon.
14. A method for fabricating a semiconductor device, comprising the steps of:
- (a) implanting first dopant ions of a first conductivity type into a semiconductor region of the first conductivity type, thereby forming a channel implantation layer;
- (b) selectively implanting second dopant ions, which are made of carbon or made of molecules containing carbon, into a channel formation region in the semiconductor region, thereby forming a carbon implantation layer in the channel implantation layer;
- (c) subjecting, after the steps (a) and (b), the semiconductor region to a first heat treatment so as to cause diffusion of the first dopant ions from the channel implantation layer and the carbon implantation layer, thereby forming a channel doped layer in the semiconductor region;
- (d) forming a gate insulating film on the channel doped layer in the semiconductor region; and
- (e) forming a gate electrode on the gate insulating film,
- wherein the channel doped layer contains the carbon of the second dopant ions.
15. The method of claim 14, further comprising, between the steps (a) and (b), the step of forming, on the semiconductor region, a mask pattern having an opening that exposes the channel formation region,
- wherein in the step (b), the second dopant ions are selectively implanted into the channel formation region by using the mask pattern, thereby forming the carbon implantation layer.
16. The method of claim 14, further comprising, before the step (a), the step of forming, on the semiconductor region, a mask pattern having an opening that exposes the channel formation region,
- wherein in the step (a), the first dopant ions are selectively implanted into the channel formation region by using the mask pattern, thereby forming the channel implantation layer, and
- in the step (b), the second dopant ions are selectively implanted into the channel formation region by using the mask pattern, thereby forming the carbon implantation layer.
17. The method of claim 14, further comprising, after the step (e), the step (f) of forming extended implantation layers by implanting third dopant ions of a second conductivity type into the semiconductor region with the gate electrode used as a mask; and
- after the step (f), the step (g) of subjecting the semiconductor region to a second heat treatment, thereby forming extended doped layers by diffusion of the third dopant ions from the extended implantation layers.
18. The method of claim 17, further comprising, between the steps (e) and (g), the step of implanting fourth dopant ions of the first conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming pocket implantation layers,
- wherein in the step (g), the second heat treatment causes diffusion of the fourth dopant ions from the pocket implantation layers, thereby forming pocket doped layers under the extended doped layers.
19. The method of claim 14, further comprising, after the step (e), the step (h) of forming sidewalls on lateral faces of the gate electrode;
- after the step (h), the step (i) of implanting fifth dopant ions of a second conductivity type into the semiconductor region with the sidewalls used as a mask, thereby forming source/drain implantation layers; and
- after the step (i), the step (j) of subjecting the semiconductor region to a third heat treatment to cause diffusion of the fifth dopant ions from the source/drain implantation layers, thereby forming source/drain doped layers.
20. The method of claim 14, further comprising, before the step (a), the steps of:
- (1) forming a dummy gate electrode on the semiconductor region;
- (2) forming sidewalls on both lateral faces of the dummy gate electrode;
- (3) forming, after the step (2), on the semiconductor region, an insulating film from which the upper surface of the dummy gate electrode is exposed; and
- (4) selectively removing the dummy gate electrode after the step (3), thereby exposing a part of the semiconductor region between the sidewalls,
- wherein in the step (a), the first dopant ions are implanted into the exposed part of the semiconductor region with the insulating film used as a mask, thereby forming the channel implantation layer; and
- in the step (b), the second dopant ions are implanted into the exposed part of the semiconductor region with the insulating film used as a mask, thereby forming the carbon implantation layer.
21. The method of claim 14, wherein the first dopant ions are heavy ions having a relatively high mass number.
22. The method of claim 21, wherein in the step (a), the channel implantation layer does not become amorphous due to the implantation of the first dopant ions.
23. The method of claim 21, wherein the heavy ions are indium ions.
24. The method of claim 14, wherein the semiconductor region is made of silicon.
25. A method for fabricating a semiconductor device, comprising the steps of:
- (a) forming a gate insulating film on a semiconductor region of a first conductivity type;
- (b) forming a gate electrode on the gate insulating film;
- (c) implanting first dopant ions of a second conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming extended implantation layers;
- (d) implanting second dopant ions of the first conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming pocket implantation layers;
- (e) selectively implanting third dopant ions, which are made of carbon or made of molecules containing carbon, into pocket formation regions in the semiconductor region, thereby forming carbon implantation layers; and
- (f) subjecting the semiconductor region to a first heat treatment after the steps (c), (d), and (e) have been performed, whereby diffusion of the first dopant ions from the extended implantation layers is caused to form extended doped layers in the semiconductor region below the sides of the gate electrode, and diffusion of the second dopant ions from the pocket implantation layers is caused to form pocket doped layers under the extended doped layers,
- wherein the pocket doped layers contain the carbon of the third dopant ions.
26. The method of claim 25, further comprising, after the step (f), the step (g) of forming sidewalls on lateral faces of the gate electrode;
- after the step (g), the step (h) of implanting fourth dopant ions of the second conductivity type into the semiconductor region with the sidewalls used as a mask, thereby forming source/drain implantation layers; and
- after the step (h), the step (i) of subjecting the semiconductor region to a second heat treatment to cause diffusion of the fourth dopant ions from the source/drain implantation layers, thereby forming source/drain doped layers.
27. The method of claim 25, wherein the second dopant ions are heavy ions having a relatively high mass number.
28. The method of claim 27, wherein the heavy ions are indium ions.
29. The method of claim 25, wherein the semiconductor region is made of silicon.
Type: Application
Filed: Jul 19, 2005
Publication Date: Mar 30, 2006
Applicant:
Inventor: Taiji Noda (Osaka)
Application Number: 11/183,822
International Classification: H01L 21/336 (20060101);