Three-dimensional stack manufacture for integrated circuit devices and method of manufacture
An integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack. Solder pads on the interconnect substrates are reflowed to form a solder connection to the exposed vias, allowing complex interconnection between diverse points along the edge connectors of each substrate. In one embodiment, solder balls are reflowed on ball-grid-array pads at the top of the stack to provide external electrical connections.
1. Field of the Invention
The present invention relates in general to integrated circuit packages and assemblies, and in particular is directed to stacking of a plurality of integrated circuit devices within a three-dimensional integrated circuit package manufacture.
2. Description of the Related Art
Integrated circuits are typically packaged in a single chip or ‘monolithic’ configuration which, in turn, is soldered or plugged into a printed circuit board, or other type of interconnect support substrate. In a multi-chip ‘hybrid’ package, several devices are assembled into a single package, having the advantages of reduced weight, size and, occasionally, circuit performance. In an effort to further enhance packaging density, edge-wise or vertically stacked multi-chip packaging assemblies have been proposed. In such configurations, rather than array a plurality of devices in what is essentially a two dimensional or planar layout, the devices are arranged on top of one another in a ‘stack’ or ‘layered’ manufacture and interconnected along the edges thereof utilizing wire bonds or flexible metallic wires connected to a common substrate.
SUMMARY OF THE INVENTIONIn accordance with the present invention, improved methods and articles of manufacture of a three-dimensional integrated circuit assembly are disclosed. One preferred embodiment of the present invention is an integrated circuit package assembly formed by stacking flip-chip mounted substrates interleaved with precisely dimensioned spacers and then bonded by injection molding the stack. The sides of the stack are sawed off to expose vias in the substrates, and multilevel-interconnect substrates are precisely aligned on the sides of the stack. Solder pads on the interconnect substrates are reflowed to form a solder connection to the exposed vias, allowing complex interconnection between diverse points along the edge connectors of each substrate. In one embodiment, solder balls at the top of the stack are reflowed on ball-grid-array pads to provide external electrical connections.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
BRIEF DESCRIPTION OF THE DRAWINGSThis invention is described in a preferred embodiment in the following description with reference to the drawings, in which like numbers represent the same or similar elements and one or a plurality of such elements, as follows:
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PCB 200 includes a plurality of pads 202 electrically connected to a plurality of metal traces 204 ending at pads 206 (not all elements are explicitly referenced, but all similar elements are intended to be referred). PCB 200 is adapted for mounting integrated circuit semiconductor devices, preferably “flip-chips,” as is well known in the art, having solder bumps or pins distributed over the face of the chip, usually around the periphery. This array of solder bumps is soldered to pads 206 on PCB 200. When a flip-chip integrated circuit is properly aligned and mounted on PCB 200, pads 202, 206 and traces 204 create digital and analog signal, power and ground connections to the integrated circuit chip. PCB 200 further has encapsulant flow holes 208, 210 and alignment holes 212, 214. These holes 208-214 are formed using highly accurate tooling, which place alignment holes 212, 214 to within a relative positional accuracy of pads 205 of no greater than ±1 mils.
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During the manufacture of 3-D integrated circuit package 100, each of the x-y interconnect substrates and spacers 304-319 are stacked on top of each other, with the spacers interleaved in between each of the x-y interconnect substrates to form a stacked interconnect substrates 320. The stacked interconnect substrates 320 is stacked on alignment block 330. Interleaved between each of the x-y interconnect substrates 304-310 are spacers 312-319, formed of a non-thermal conducting but electrically non-conducting materials such as fiberglass reinforced epoxy. At the bottom of stacked interconnect, mounted on pins 332, 336, is BGA substrate 311, which is created in the same manner as BGA substrate 216. In an alternative embodiment, BGA substrate 311 and spacer 319 is not used and x-y interconnect substrate is a multi-layered PCB, with a bottom surface 218, a middle layer configured as surface 220 and a top surface 201.
X-y interconnect substrates 304-310, BGA interconnect substrate 311, and spacers 312-319 have been formed to an extremely precise thickness to insure a desired substrate-to-substrate dimensioning for the subsequent z-axis interconnect substrate attachment to be described below. For example, interconnect substrates and spacers 304-319 have a thickness of 12 mils to within a tolerance of +/−1 mil. Each of the spacers 312-319 contain precisely aligned alignment holes 322, 326 that are precisely formed to match the alignment holes 334 (corresponding to alignment holes 212, 214) on the corresponding x-y interconnect substrates 304-310.
The stacked interconnect substrates 320 is aligned utilizing the alignment block 330, which includes alignment pins 332 and 336. Alignment pins 332 and 336 are precisely machined pins having precise dimensions and being precisely mounted on alignment plate 330 so that the distance between the alignment pins 332 and 336 is precisely equal to the distance between the alignment holes in stacked interconnect substrates 320. For example, alignment pins 332, 336 are of a diameter precisely matched to the diameter of alignment holes 322, 334, 326 (and alignment holes 212, 214, as seen in
With molding plates 330, 402 securely held together, the stacked interconnect substrates 320 are then encapsulated. Thermal cure epoxy encapsulates are injected into either or both of injection holes 422, 424 on molding plate 402 using industry standard molding techniques as are well known in the electronics packaging industry. Injection hole 422 is precisely aligned with injection holes 212 and 222 and 324 such that liquefied encapsulant flows freely there between. Similarly, injection hole 424 is precisely aligned with injection holes 214 and 224 and 328 such that liquefied encapsulant flows freely there between. As the encapsulant is injected into the molding manufacture, encapsulant will flow freely in between the layers of substrates and spacers until the entire stacked interconnect substrates 320 are immersed in encapsulant. The encapsulate is then thermally cured by subjecting the encapsulate to high temperatures appropriate to cure the encapsulate and completely surround the stacked interconnect substrates 320. Once the stacked interconnect substrates 320 is encapsulated, it is removed from molding plate 330, 402.
The next step in the manufacture process uses a wafer saw to precisely cut the stacked interconnect substrates 320 through a center axis (for example, center axis 207) of vias 205 (see
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With stacked integrated circuit module 520 mounted in place on surface 912 and with each of the z-axis interconnect substrates 702 mounted within insets 924, each of the side alignment plates 904-910 are brought together at base 902 to mate machined holes 920, 922 on receiving pins 914, 916, respectively. BGA alignment solder plate 926 is then placed on surface 502 of (z-axis stacked) integrated circuit module 520 and solder balls 928 are positioned in each of the holes 930 on solder ball alignment plate 926. Each of the side alignment plates 904-910 are held in place by machine screws, for example, machine screws 932 are threaded through holes 934 in side alignment plates 904, 906 and screwed into threaded holes 936. Machine screws are similarly mounted into side alignment plates 908 and 910.
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The manufacturing process then proceeds to step 1116, where the stack of BGA interconnect substrate 311, x-y interconnect substrates 304-310 and spacers 314-319 are precisely aligned and organized into stacked interconnect substrates 320. At step 1118, stacked interconnect substrates 320 is precisely located on alignment pins 332, 336 between molding plates 330 and 402, which are then secured together by screws 404. At step 1120, an epoxy encapsulate is dispensed throughout the stack 320 by injecting the epoxy encapsulate into holes 406, 408 in molding plate 402 and down through injection holes 324, 328 in each of the spacers 312-319 and injection holes 208, 210 in each of the x-y interconnect substrates 304-310. Encapsulant may be injected into only one hole 406, 408 to permit the other hole 406,408 to act as an exit for the out-flow of encapsulant when the molding has filled. Further at step 1120, the entire mold is then placed in an oven and cured at approximately 150° C. The process then proceeds to step 1122, where the stack 320 is sawed along each edge, for example along axis 207, to expose each via 205 along all four edges of each of the x-y interconnect substrates 304-310 and BGA interconnect 311, and thereby forming module 520. At step 1124, a coat of flux paste is placed on the BGA surface 502 of the module 520.
Thereafter, at step 1126, a solder paste is printed on four z-axis interconnect substrates 702. At step 1128, the module 520 and each of the z-axis interconnect substrates 702 are placed on the manufacturing tool comprising base 902, and sides 904-910. The process then proceeds to step 1130, where solder ball alignment plate 930 is placed on top of BGA surface 502. At step 1132, each of the side alignment plates 904-910 are located on pins 914, 916 and bolted into place by bolts 932. At step 1134, solder balls 928 are placed on solder ball alignment plate 926. At step 1136, the solder pads 806 of z-axis interconnect substrates 702 and BGA solder balls 928 are reflowed using a heating process on the manufacturing tool. Thereafter, at step 1138, the flux residue produced by step 1136 is removed using hot water spray and drying process. At step 1140, an under-fill is dispensed beneath each of the x-axis interconnect substrates 702 and is cured. Thereafter, the completed 3-D integrated circuit package 100 is tested by plugging it into a BGA electrical test socket and performing standard diagnostic testing of the integrated circuit system. One advantage to the 3-D integrated circuit package 100 is that the z-axis interconnect substrate can allow for controlled impedance transmission line interconnects for very high speed signals. Further, when comparing bond wires to printed traces, printed traces as used in the preferred embodiment present a much lower inductance load on the signal, a distinct advantage in high speed systems.
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After placing module 520 within inset 1202, the z-axis substrates 702 are placed flush against the side of stacked integrated circuit module 520 between columns 1204, 1206 and 1208. Spacer bars 1228, 1230 are placed against each of the z-axis substrates 702. Z-axis substrate holding wedges 1232, 1234 are then slid in between the side columns 1212-1218 in each of the spacer bars 1228, 1230. Each of the z-axis substrate holding wedges 1232, 1234 are slowly slid in between the spacer bars and side columns. As will be appreciated, the complimentary angles 1224, 1236 and 1222 and 1238 cause z-axis substrate holding wedges 1234, 1232 to be pushed away from side columns 1212-1218 as holding wedges 1234, 1232 are slid in the direction from column 1204 toward and then past column 1206, and in the direction from column 1206 toward and then past column 1208, respectively. This force causes a force to slowly exert pressure on spacer bars 1228, 1230 in the direction of z-axis substrates 702 until the proper pressure to allow solder reflow is placed upon the z-axis substrate 702 in alignment with stacked integrated circuit module 520. Thereafter, the stacked integrated circuit module 520 is reflowed by the application of heat to z-axis assembly reflow solder tool 1200 to allow the aligned z-axis substrate 702 to be solder bonded to the edges of stacked integrated circuit module 520, in accordance with the same process as described in conjunction with
In the above detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration, specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that logical, mechanical, electrical and other changes may be made without departing from the spirit or scope of the present invention. The detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. While the invention has been particularly shown and described with reference to one or more preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims
1. A semiconductor package assembly comprising:
- a first substrate having a first top surface comprising a first integrated circuit, a first bottom surface and a first edge surface substantially perpendicular to the first top surface, wherein the edge surface includes a first plurality of pads electrically coupled to the first integrated circuit;
- a second substrate having a second top surface comprising a second integrated circuit, a second bottom surface and a second edge surface substantially perpendicular to the second top surface, wherein the second edge surface includes a second plurality of pads electrically coupled to the second integrated circuit, and wherein the second substrate is stacked together with the first substrate such that the first top surface is mechanically coupled to the second bottom surface and the first and second edge surfaces are aligned along a plane of space; and
- an interconnect substrate having a interconnect top surface aligned along the plane of space and a interconnect bottom surface, wherein the interconnect top surface includes a third plurality of pads disposed on the interconnect top surface to electrically couple at least two of the third plurality of pads with at least one of the first plurality of pads on the first edge surface and at least one of the second plurality of pads on the second edge surface, and further wherein the interconnect substrate electrically couples a plurality of the third plurality of pads such that the first integrated circuit is electrically coupled to the second integrated circuit.
2. The assembly according to claim 1, further comprising:
- a third substrate having a third top surface comprising a third integrated circuit, a third bottom surface and a third edge surface substantially perpendicular to the third top surface, wherein the third edge surface includes a fourth plurality of pads electrically coupled to the third integrated circuit, and wherein the third substrate is stacked together with the second substrate such that the second top surface is mechanically coupled to the third bottom surface and the third and second edge surfaces are aligned along a plane of space; and
- wherein the third plurality of pads are disposed on the interconnect top surface to electrically couple at least one of the third plurality of pads with at least one of the fourth plurality of pads on the third edge surface, and further wherein the interconnect substrate electrically couples at least one of the fourth plurality of pads with one or more of the first and second plurality of pads such that the third integrated circuit is electrically coupled to one or both of the first and second integrated circuits.
3. The assembly according to claim 1, wherein the first bottom surface includes a plurality of external contacts electrically coupled to the first plurality of pads.
4. The assembly according to claim 1, further comprising:
- a base substrate having a base top surface, a base bottom surface having a first base plurality of pads disposed thereon, and a base edge surface substantially perpendicular to the base bottom surface, wherein the base edge surface includes a second base plurality of pads electrically coupled to the first base plurality of pads, and wherein the first substrate is stacked together with the base substrate such that the first bottom surface is mechanically coupled to the base top surface and the first and base edge surfaces are aligned along the plane of space; and
- wherein the third plurality of pads are disposed on the interconnect top surface to electrically couple at least one of the third plurality of pads with at least one of the second base plurality of pads on the base edge surface, and further wherein the interconnect substrate electrically couples the first base plurality of pads with one or more of the first and second plurality of pads such that the first base plurality of pads are electrically coupled to one or both of the first and second integrated circuits.
5. A three-dimensional semiconductor package assembly comprising:
- a plurality of substrates, each having an integrated circuit chip mounted thereon, fixedly disposed in a vertical stack such that an edge of each of the plurality of substrates forms a side of the vertical stack, wherein electrical contacts on each edge of the plurality of substrates are electrically coupled to the integrated circuit chip mounted thereon;
- an interconnect substrate having a plurality of pads dispersed on a surface and mounted on the side of the vertical stack such that the plurality of pads are electrically connected to the electrical contacts on the plurality of substrates permitting electrical signals to be transmitted between the integrated circuit chips.
6. The assembly according to claim 5, further comprising a plurality of spacers interleaved between the plurality of substrates.
7. The assembly according to claim 5, wherein the interconnect substrate is a printed circuit board.
8. The assembly according to claim 5, wherein one of the plurality of substrates is at a bottom of the vertical stack and has electrical pads on its bottom surface electrically coupled to the interconnect substrate.
9. The assembly according to claim 5, wherein the electrical contacts are electrically conducting vias in the plurality of substrates.
10. The assembly according to claim 5, wherein the interconnect substrate provides a plurality of electrical interconnections between the plurality of pads.
11. The assembly according to claim 5, wherein the vertical stack is formed by molding the plurality of substrates together.
12. A method of manufacturing a semiconductor assembly comprising the steps of:
- mounting a first semiconductor element on a first substrate including first electrical connections between the first semiconductor element and an edge of the first substrate;
- mounting a second semiconductor element on a second substrate including second electrical connections between the second semiconductor element and an edge of the second substrate;
- positioning and stacking the first substrate on the second substrate to form a substrate stack having a top, bottom and side;
- forming an interconnect substrate having interconnect pads precisely aligned relative to each other as a function of the dimensions of the first and second substrates, relative positions of the first electrical connections on the first substrate, relative positions of the second electrical connections on the second substrate, and relative position of the first and second substrates in the substrate stack; and
- aligning and mounting the interconnect substrate on the side of the substrate stack to connect the interconnect pads and the first and second electrical connections, thereby forming an integrated circuit assembly.
13. The method of claim 12, further comprising the step of securing the first substrate on the second substrate.
14. The method of claim 13, further comprising securing the first substrate on the second substrate by injection molding the first and second substrates together.
15. The method of claim 12, wherein the step of forming an interconnect substrate comprises forming four interconnect substrates and the step of aligning and mounting comprises aligning and mounting the four interconnect substrates.
16. The method of claim 12, wherein the step of positioning and stacking comprises positioning and stacking a spacer between the first substrate and second substrate to form the substrate stack and further wherein the step of forming the interconnect substrate comprises forming an interconnect substrate having interconnect pads precisely aligned relative to each other as a function of the dimensions of the spacer, first and second substrates and relative positions of the first and second electrical connections and substrate stack.
17. The method of claim 12, further comprising the step of bonding the first and second electrical connections to the interconnect pads to form the electrical connection thereof by placing the integrated circuit assembly in a heated environment to reflow solder on the interconnect pads and connect with the first and second electrical connections.
18. The method of claim 12, further comprising the step of, prior to aligning and mounting the interconnect substrate on the side of the substrate stack, removing a portion of the first and second substrates to expose the first and second electrical connections at the side of the substrate stack.
19. The method of claim 18, wherein the step of removing a portion of the first and second substrates to expose the first and second electrical connections at the side of the substrate stack comprises sawing the substrate stack through a center axis of a plurality of vias within each of the first and second substrates and electrically coupled to the electrical connections.
20. The method of claim 12, further comprising the step of forming a ball-grid-array on the top of the substrate stack, wherein the ball-grid-array is electrically coupled to the first and second electrical connections.
21. A three dimensional integrated circuit package comprising:
- a plurality of integrated circuit devices each mounted to a substrate having a plurality of electrical connections about the periphery thereof;
- means for bonding each of the substrates in vertical alignment;
- at least one multilevel z-axis interconnect substrate having electrical pads along at least one surface thereof, the electrical pads spaced to be matingly engaged with the plurality of electrical connections about the periphery of each of the vertically aligned substrates;
- a plurality of conductive traces within the multilevel z-axis interconnect substrate for interconnecting selected ones of the electrical pads in a non-serial order; and
- means for bonding the at least one multilevel z-axis interconnect substrate to an edge of the vertically aligned substrates.
22. The package according to claim 21, further comprising a plurality of spacers interleaved between the vertically aligned substrates.
23. The package according to claim 21, wherein the at least one multilevel z-axis interconnect substrate is a printed circuit board.
24. The package according to claim 21, wherein the electrical contacts are electrically conducting vias in the vertically aligned substrates.
25. The package according to claim 21, wherein the interconnect substrate provides a plurality of electrical interconnections between the plurality of integrated circuit devices.
26. The package according to claim 21, wherein the vertical stack is formed by molding the plurality of substrates together.
Type: Application
Filed: Sep 24, 2004
Publication Date: Apr 6, 2006
Inventor: Emory Garth (Austin, TX)
Application Number: 10/949,770
International Classification: H01L 23/02 (20060101);