Method to form etch and/or CMP stop layers
In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over the gate and over the substrate than it is on the side of the gate. A second non-conformal oxide is provided over the first non-conformal oxide. The second oxide is annealed in a boron-containing atmosphere, and the first oxide prevents boron diffusion from the second oxide into the gate and substrate. The second oxide may then serve as an etch stop, a CMP stop, or both.
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This application is a divisional of application Ser. No. 09/531,680, filed Mar. 20, 2000.
TECHNICAL FIELDThe present invention relates generally to a doped non-conformal layer in a semiconductor device. More specifically, the present invention relates to a boron-doped oxide that can be used as a stopping layer for etching or chemical-mechanical planarization (CMP), among other uses.
BACKGROUND OF THE INVENTIONThe formation of semiconductor devices (which may actually include conductive and insulative materials as well as semiconductive elements) often involves removing amounts of material included as part of the device. Occasionally, the desired result of removing material is a planarized surface. Other times, the desired result is an opening extending at least partway into the material. Examples of both results occur in the manufacture of dynamic random access memory (DRAM) devices, wherein transistor gates are formed over a semiconductor substrate. Once the gates are formed, an insulator can be deposited between and over them. The surface of this insulator is lowered to the general level of the gate top and planarized through etching or CMP. After that, a contact opening is etched through the insulator to a doped region of the semiconductor substrate that forms a transistor source or drain. This opening will subsequently be filled with conductive material, thereby allowing electrical communication with the doped substrate.
This process of forming a hole within an insulation layer and filling that hole with a conductive material is generally known as a damascene process. Damascene processes offer an alternative to etching away undesired portions of a continuous conductive layer and surrounding the remaining portions with insulation. Damascene processes used at various fabrication stages provide additional examples of where material removal is desired in the context of DRAM devices. For example, initially providing the damascene insulation layer may involve CMP before the hole is formed therein, and forming the hole usually involves an etching step.
During CMP or etching steps such as those described above, it is often preferable to provide some sort of CMP stop or etch stop at a location defining the extent of the removal process. Oftentimes this CMP/etch stop will be some sort of material that is more resistant if not completely immune to the CMP/etch process than is the material that is to be removed. For example, U.S. Pat. No. 5,485,035 by Lin et al. discloses using a first boron-doped oxide layer in carrying out a planarizing etch back (see Lin's
Such oxides can be deposited by growing them from a surface in an oxidizing atmosphere or by conventional deposition methods, such as chemical vapor deposition (CVD). Another method of providing oxide is a process known as Flowfill. Flowfill involves reacting silane with vaporized hydrogen peroxide. The reaction results in a gas which condenses as a liquid on a substrate cooled to about 0° C. A subsequent heat treatment dries the liquid to form SiO2.
As for the application of Flowfill-created oxides, prior art discloses a CMP process that stops within a Flowfill layer, although it is unclear from one particular reference whether this is a matter of properly timing the CMP or due to some property of the oxide itself. See Sabine Penka, Integration Aspects of Flowfill and Spin-on-Glass Process for Sub-0.35 μm Interconnects, P
Concerning altering the properties of Flowfill layers, U.S. Pat. No. 5,985,770, also assigned to Micron Technology Inc., discloses gas phase doping of a Flowfill layer before or during the heat treatment that ultimately solidifies the Flowfill liquid into SiO2.
Given the state of the prior art in terms of CMP and etch stops, there is a constant need in the art to find a new etch stop or CMP stop and new ways of making them. Moreover, there is also a need in the art to find new applications for and modifications of the Flowfill process.
SUMMARY OF THE INVENTIONAccordingly, exemplary embodiments of the current invention provide a doped non-conformal oxide. In a preferred exemplary embodiment, a non-conformal oxide that resists doping is initially provided by way of a Flowfill process. Next is provided a second non-conformal oxide that is configured to accept dopant more readily. Subsequently the second oxide is annealed in an atmosphere containing boron. Alternative method embodiments include other ways of flowing at least one of the oxides. Still other alternatives address other ways of providing non-conformal oxides, such as through a high-density plasma CVD. Yet other alternative exemplary embodiments address the use of a doped non-conformal oxide as an etch stop and/or a CMP stop.
BRIEF DESCRIPTION OF THE DRAWINGS
Unlike the first oxide 28, this second oxide 30 is porous and will readily accept dopant. Without limiting the current invention, it is believed that this second oxide 30 will do so because of its porous nature. As for the creation of these pores, it is thought that the formation process described above results in gaps within the second oxide 30 that are bigger than the lattice constant defined by the Si—O bonds of that layer. These gaps, which may define lengths of 10 to 20 Angstroms and greater, may accommodate a dopant that is supplied in a later step. Accordingly, the term “pore” as used in this application, including the claims, is defined as a gap in a material, wherein the gap is bigger than the lattice constant of that material.
Accordingly, the second oxide 30 is subsequently doped with boron 32, the result of which is seen in
Next, an insulation layer 34 seen in
Moreover, the lower portions of the second oxide 30 may also serve to stop another removal process. For example, it may be desired to provide a contact between the transistor gates 20. To do so,
The subsequent processing steps, however, may lead to other exemplary embodiments involving a non-conformal boron-doped oxide.
The current invention also includes within its scope exemplary embodiments wherein the doped non-conformal oxide is used for purposes other than stopping etching or CMP. In
Alternatively, if it is not desired to dope the surface of material 58, a barrier layer 64 such as a nitride may be deposited before etching the trench 59. The result after annealing the boron-doped non-conformal oxide 56 is depicted in
Still another alternative is to provide process parameters such that the deposition of the non-conformal oxide on the top of the material 58 is reduced or perhaps even eliminated. For example, if methylsilane is reacted with hydrogen peroxide at room temperature (about 20° C.), then the non-conformal oxide 56 will be thicker at the bottom of trench 59 than amounts, if any, at the top, as seen in
In other cases, it may simply be desired to fill a trench 65 with a doped oxide, and embodiments of the current invention can accommodate such cases. A non-conformal oxide 66 can be deposited and subsequently doped, using, for example, the methylsilane deposition/diborane anneal steps discussed above. The result is seen in
In addition, while it is preferred to deposit the oxide by heating the product of a methylsilane/hydrogen peroxide reaction, the current invention includes within its scope exemplary embodiments that provide a non-conformal oxide by other ways. For example, another way to flow the oxide onto the underlying layer is through a spin-on-glass (SOG) process. The SOG process involves depositing a suspension of glass particles in an inorganic carrier onto a spinning substrate. Conventional photoresist tools can be used to achieve such a deposition. The organic carrier is then driven off of the substrate using a thermal process, and the remaining glass is reflowed to fill spaces in the underlying topography and to planarize the glass surface.
Another way of providing a non-conformal oxide is through the use of a high-density plasma (HDP) CVD process. In such a process, plasma gases including silicon-containing, oxygen-containing, and nonreactive gasses (e.g. a noble gas) are used to deposit an oxide while simultaneously etching the oxide to prevent gaps from forming in the oxide material. The density of the plasma is greater than 1010 ions per cm3. Exemplary parameters include an ambient of O2 (flowed at a rate of 120-500 sccm), SiH4 (flowed at a rate of 80-250 sccm), and Ar (flowed at a rate of 0-50 sccm); an RF bias at 13.56 MHz; a temperature ranging from 350-700° C.; and a bias power ranging from 0 to 2000 W. Moreover, other CVD processes could be used to provide a non-conformal layer.
In addition, it is not necessary that the dopant be boron. Exemplary embodiments of the current invention include those in which at least one other impurity replaces or is added along with boron. It is noted that U.S. Pat. No. 5,985,770 discussed above discloses doping the oxide precursor with various materials before and during formation of the oxide layer. For example, application '987 indicates that phosphorous doping can be accomplished using PH3, phosphates, or phosphites; fluorine doping can involve NF3 or F2; carbon may serve as the dopant using C2H6, trimethyl silane ((CH3)3SiH) or CH4; and nitrogen may dope the oxide using NF3 or NH3. The current invention includes within its scope exemplary embodiments that involve doping a non-conformal oxide after its formation with the dopants above (either alone or in combination) by using precursor gases such as the ones above (again either alone or in combination). More specific exemplary embodiments include doping one portion of the non-conformal oxide with a first dopant and a second portion of the oxide with a second dopant. Appropriate masking of the portions can be used to allow for such selective doping.
Furthermore, in embodiments wherein a diffusion barrier layer (such as the first oxide 28) is preferred, it is not necessary that the diffusion barrier be deposited in a non-conformal manner. Other exemplary embodiments allow for the barrier layer to be provided through standard methods resulting in a conformal layer. For example, an SiO2 barrier layer could be provided under known conformal CVD parameters. Alternatively, a conformal layer of tetraethylorthosilicate (TEOS)-based glass could be layered before the non-conformal layer is provided and subsequently doped.
Given the variety of alternative embodiments described above, one skilled in the art can appreciate that, although specific embodiments of this invention have been described above for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Returning to the first exemplary embodiment described above, for instance, the first oxide under the doped second oxide is preferred to help prevent diffusion into other portions of the DRAM. However, the first oxide is not required, as careful processing can dope the second oxide without having the dopant diffuse beyond the oxide. Thus, embodiments without the first oxide fall within the scope of the invention. Further, as an addition to or an alternative to the preferred monomethylsilane/peroxide reaction, the current invention includes within its scope the use of other chemicals to provide a non-conformal oxide, including (but not limited to) dimethylsilane, trimethylsilane, tetramethylsilane, pentamethyldisilane, and combinations of chemicals. Moreover, while exemplary embodiments of the current invention have been illustrated in the context of a DRAM, these and other embodiments apply to semiconductor devices in general. Accordingly, the invention is not limited except as stated in the claims.
Claims
1-16. (canceled)
17. A method of processing an in-process semiconductor device, comprising:
- non-conformally depositing an oxide over said in-process semiconductor device;
- doping said oxide; and
- depositing an insulator over said oxide.
18. The method in claim 17, further comprising:
- initiating a removal of at least a portion of said insulator; and
- halting said removal using said oxide.
19. The method in claim 18, wherein said initiating step comprises initiating an etching of said insulator; and wherein said halting step comprises using said oxide as an etch stop.
20. The method in claim 18, wherein said initiating step comprises initiating a planarization of said insulator.
21. The method in claim 20, wherein said step of initiating a planarization of said insulator comprises initiating a chemical-mechanical planarization of said insulator; and wherein said halting step comprises using said oxide as a CMP stop.
22. A method of providing oxide for an in-process semiconductor device, comprising:
- depositing a first oxide over said in-process semiconductor device; and
- non-conformally depositing a porous second oxide onto said first oxide.
23. The method in claim 22, wherein said step of depositing a first oxide comprises depositing said first oxide in a chamber; and wherein said step of non-conformally depositing a porous second oxide comprises depositing said second oxide in said chamber.
24. The method in claim 22, wherein said step of non-conformally depositing a porous second oxide comprises reacting methylsilane with hydrogen peroxide.
25. The method in claim 22, wherein said step of non-conformally depositing a porous second oxide comprises reacting H3SiCH3 with H2O2.
26. The method in claim 25, wherein said step of non-conformally depositing a porous second oxide further comprises:
- cooling said in-process semiconductor device to about 0° C. before said reacting step; and
- providing a temperature of about 450° C. inside said chamber after said reacting step.
27. The method in claim 26, wherein said step of depositing a first oxide comprises reacting silane with hydrogen peroxide.
28. A method of providing a doped oxide, comprising:
- flowing an oxide precursor over a portion of a semiconductor device;
- forming an oxide from said precursor; and
- subsequently annealing said oxide in an atmosphere containing a dopant.
29. The method in claim 28, wherein said annealing step comprises annealing said oxide in an atmosphere consisting of a selection of PH3, a phosphate, a phosphite, NF3, F2, C2H6, trimethyl silane, CH4, NH3, B2H6, and combinations thereof.
30. The method in claim 29, wherein said annealing step further comprises annealing at a temperature ranging from 400 to 800° C., at a pressure ranging from 0.5 to 760 Torr, and for a time ranging from 10 seconds to 5 minutes.
31. A method of processing a surface of an in-process memory device, comprising:
- providing said surface as part of said memory device using a non-CVD process;
- flowing a material onto said surface;
- turning said material into a first oxide; and
- doping said first oxide.
32. The method in claim 31, wherein said step of providing said surface comprises providing a barrier oxide using a Flowfill process; and wherein said method further comprises blocking diffusion of a dopant from said first oxide using said barrier oxide.
33. The method in claim 32, wherein said step of doping said first oxide comprises:
- doping a first portion of said first oxide with a first impurity; and
- doping a second portion of said first oxide with a second impurity.
34. A method of providing an etch stop for a semiconductor device, comprising:
- providing at least one support surface as part of said semiconductor device, said surface having a horizontal portion and a non-horizontal portion;
- depositing an oxide onto said support surface, wherein said oxide has a uniform thickness on said horizontal portion and a variable thickness on said non-horizontal portion; and
- doping said oxide.
35. The method in claim 34, wherein said depositing step comprises depositing said oxide by way of a CVD process.
36. The method in claim 35, wherein said depositing step comprises depositing said oxide by way of an HDP CVD process.
37. A method of providing a CMP stop for a semiconductor device, comprising:
- providing an element of said semiconductor device, said element having a top and a side;
- depositing an oxide over said element, wherein said depositing leaves more of said oxide on said top than on said side; and
- annealing said oxide in a doping atmosphere.
38. The method in claim 37, wherein said step of depositing an oxide comprises:
- flowing a precursor to said oxide over said element; and
- heating said precursor.
39. The method of claim 38, wherein said step of depositing an oxide comprises depositing said oxide using a spin-on-glass process.
40. A method of selectively doping a circuit device material, comprising:
- depositing an oxide over a first horizontal surface of said circuit device material to the exclusion of a vertical surface of said material;
- introducing a dopant into said oxide; and
- diffusing said dopant from said oxide into said material.
41. The method in claim 40, further comprising a step of depositing a diffusion barrier over a second horizontal surface of said material; and wherein said step of depositing an oxide further comprises depositing said oxide over said diffusion barrier.
42. A method of filling a trench included as part of a semiconductor device, comprising:
- reacting methylsilane with hydrogen peroxide in a chamber containing said semiconductor device;
- allowing a product from a reaction of said methylsilane and said hydrogen peroxide to at least fill said trench;
- changing said product into a silicon oxide; and
- heating said silicon oxide in a boron atmosphere.
43. A fabrication process for a DRAM including a semiconductor substrate, said process comprising:
- depositing an undoped self-planarizing first oxide over an in-process device included as a part of said DRAM;
- depositing an undoped self-planarizing second oxide over said first oxide; and
- doping said second oxide.
44. The process in claim 43, further comprising:
- depositing an insulation layer over said second oxide;
- planarizing said insulation layer; and
- using said second oxide as a planarization stop.
45. The process in claim 43, further comprising:
- depositing an insulation layer over said second oxide;
- etching an opening in said insulation layer; and
- using said second oxide as an etch stop.
46. The process in claim 45, wherein said step of using said second oxide as an etch stop comprises using a portion of said second oxide over said substrate as said etch stop.
47. The process in claim 46, said step of etching an opening in said insulation layer comprises etching said insulation layer at a first etch rate; and wherein said step of using said second oxide as an etch stop comprises etching said second oxide at a second etch rate, wherein said second etch rate is less than said first etch rate.
48. The process in claim 47, wherein said step of etching said insulation layer comprises exposing said insulation to a selection of an HF vapor and an HF liquid.
49. The process in claim 48, wherein said step of etching said insulation layer comprises exposing said insulation to a buffered HF liquid having a temperature of about 23° C.
50. The process in claim 48, wherein said step of etching said second oxide comprises exposing said second oxide to said selection.
51. A damascene process, comprising:
- providing a material over a semiconductor substrate, said material having a fluid property;
- forming an oxide from said material in response to allowing said material to lose said fluid property;
- providing an insulation layer over said oxide;
- etching an opening in said insulation layer;
- halting said etching with said oxide; and
- depositing a conductive material within said opening.
52. The damascene process in claim 51, further comprising a step of removing at least a portion of said oxide after said halting step and before said depositing step.
53. The damascene process in claim 52, wherein said step of forming an oxide comprises:
- forming said oxide onto a BPSG layer; and
- doping said oxide before said step of providing an insulation layer.
54. The damascene process in claim 52, wherein:
- said step of providing a material comprises depositing said material having a planar surface and defining at least two different thicknesses, wherein depositing said material occurs before providing said insulation layer; and
- said method further comprises doping said oxide before providing said insulation layer.
55. The damascene process in 54, wherein said step of depositing said material comprises depositing said material over a gate and over a conductive plug next to said gate, wherein a top of said plug is lower in elevation than a top of said gate.
56. The damascene process in claim 55, wherein said etching step comprises etching using a selection of a reactive sputter process and a plasma process.
57. The damascene process in claim 56, wherein said etching step comprises plasma etching using a gas comprising fluorine, wherein said gas includes a selection of CHF3, CF4, and C2F6.
58. The damascene process in claim 57, wherein said plasma etching step comprises:
- providing a chamber configured to accommodate said semiconductor substrate;
- flowing CF4 into said chamber at a rate of 50 sccm;
- flowing CHF3 into said chamber at a rate of 50 sccm;
- flowing Argon into said chamber at a rate of 1000 sccm;
- providing pressure of 0.2 to 0.002 Torr inside said chamber; and
- providing 750 W of RF power to said chamber.
59-65. (canceled)
66. A method of depositing an interlayer dielectric, comprising:
- providing a first level of a semiconductor device, said first level defining a topography and comprising insulation;
- depositing BSG onto discrete portions of said topography, said BSG having a dielectric constant of at most 3; and
- providing a second level of said semiconductor device over said BSG.
67. The method in claim 66, wherein said step of depositing BSG comprises:
- depositing glass onto said topography, said depositing resulting in a planar surface of said glass; and
- lowering a dielectric constant of said glass.
68. The method in claim 67, wherein said step of depositing glass comprises:
- flowing a silicon oxide precursor over said topography; and
- hardening said precursor into a silicon oxide.
69. The method in claim 68, wherein said step of lowering a dielectric constant of said glass comprises doping said silicon oxide with boron.
70. The method in claim 69, wherein said step of providing a first level of a semiconductor device comprises providing a first level further comprising at least one conductive structure.
71. A method of processing a portion of a device including a higher horizontal surface, a lower horizontal surface, and a non-horizontal surface, said method comprising:
- providing an oxide in a non-conformal manner over said higher horizontal surface, said lower horizontal surface, and said non-horizontal surface; and
- introducing an impurity into said oxide.
72. The method in claim 71, wherein said step of providing an oxide in a non-conformal manner comprises providing an oxide having a first thickness on said higher horizontal surface, a second thickness on said lower horizontal surface, and a third thickness on said non-horizontal surface, wherein said first, second, and third thicknesses are different.
73. The method in claim 72, wherein said step of providing an oxide comprises providing an oxide having a first thickness greater than said second thickness.
74. The method in claim 72, wherein said step of providing an oxide comprises providing an oxide having a second thickness greater than said first thickness.
75. The method in claim 74, wherein said step of providing an oxide in a non-conformal manner comprises reacting methylsilane and hydrogen peroxide in an environment including a substrate having a temperature of about 20° C.
76. The method in claim 75, wherein said step of providing an oxide comprises providing an oxide over a non-horizontal surface connecting said higher horizontal surface to said lower horizontal surface.
77. A method of forming a doped oxide over a substrate, comprising:
- reacting a methylsilane with hydrogen peroxide proximate said substrate;
- forming an oxide from a product of said methylsilane and said hydrogen peroxide; and
- introducing a dopant into said oxide.
78. The method in claim 77, wherein said reacting step comprises reacting said hydrogen peroxide with a selection comprising dimethylsilane, trimethylsilane, tetramethylsilane, pentamethyldisilane, and combinations thereof.
79-88. (canceled)
Type: Application
Filed: Dec 2, 2005
Publication Date: Apr 27, 2006
Applicant:
Inventor: Gurtej Sandhu (Boise, ID)
Application Number: 11/292,449
International Classification: H01L 21/311 (20060101);