Voltage regulator circuit with a low quiescent current
A voltage regulator circuit with a low quiescent current for generating a stable output voltage includes a standby mode controller for generating an enable signal according to a standby signal, a reference voltage generator for receiving an operation voltage and generating a reference voltage, an amplifier for receiving the reference voltage and the output voltage and generating an amplified voltage, and a switch unit for receiving the operation voltage and generating the output voltage at an output terminal. The enable signal is kept enabled when the standby signal is disabled, and the enable signal is periodically enabled when the standby signal is enabled. The amplifier works only when the enable signal is enabled. The switch unit is controlled by the enable signal, and is turned on only when the enable signal is enabled. So, the quiescent current of the voltage regulator circuit in the standby mode can be greatly reduced.
Latest Patents:
This application claims the benefit of the filing date of Taiwan Application Ser. No. 093135710, filed on Nov. 19, 2004, the content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to a voltage regulator circuit, and more particularly to a voltage regulator circuit for controlling operations of internal elements of the voltage regulator circuit according to a periodic control signal so as to reduce the quiescent current.
2. Description of the Related Art
A voltage regulator circuit is adopted to provide a stable output voltage.
Vfb=Vout*[R2/(R1+R2)] (1)
Vout=Vref*[1+(R1/R2)] (2)
However, this basic voltage regulator circuit 10 has DC quiescent currents including a quiescent current (Iref) of the reference voltage generator 11, a quiescent current (lop) of the error amplifier 12 and a quiescent current (Idrive) of the load. Thus, when the voltage regulator circuit 10 is kept at a no-loading state (Iload=0), the system enters a so-called standby mode, and the quiescent currents Iref and lop still exist at the input terminal (Vin) of the voltage regulator circuit 10. Therefore, if the system power is provided by a battery, the demands of reducing the quiescent current and lengthening the battery life cannot be achieved.
SUMMARY OF THE INVENTIONIt is therefore an object of the invention to provide a voltage regulator circuit with a low quiescent current.
To achieve the above-identified object, the invention provides a voltage regulator circuit with a low quiescent current. The voltage regulator circuit includes a standby mode controller for receiving a standby signal and generating an enable signal according to the standby signal, a reference voltage generator for receiving an operation voltage and generating a reference voltage, an amplifier for receiving the reference voltage and the output voltage and generating an amplified voltage, and a switch unit for receiving the operation voltage and generating the output voltage at an output terminal. The enable signal is kept enabled when the standby signal is disabled, and the enable signal is periodically enabled when the standby signal is enabled. The amplifier works only when the enable signal is enabled. The switch unit is controlled by the enable signal, and is turned on only when the enable signal is enabled. So, the quiescent current of the voltage regulator circuit in the standby mode can be greatly reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
The voltage regulator circuit of the invention with a low quiescent current will be described with reference to the accompanying drawings.
The reference voltage generator 21 and the conventional reference voltage generator 11 of
The first switch unit 24 receives the control voltage Vop outputted from the error amplifier 23 and the ON/OFF state of the first switch unit 24 is controlled according to the first enable signal REG_EN. That is, when the first enable signal REG_EN is not enabled, the first switch unit 24 is off; and when the first enable signal REG_EN is enabled, the current flowing through the first switch unit 24 is controlled according to the control voltage Vop. The capacitor C1 is connected to the output terminal of the first switch unit 24 in order to stabilize the output voltage Vout. The first switch unit 24 of this embodiment is composed of two switch elements (e.g., MOS transistors) 241 and 242. Of course, other switch units capable of achieving the same function also may be used in this invention.
The standby mode controller 26 receives a standby signal SLEEP and generates the first enable signal REG_EN according to the standby signal.
As shown in
The reference voltage generator 41 and the conventional reference voltage generator 21 of
The second switch unit 42, which is coupled between the reference voltage generator 41 and the error amplifier 23, controls whether or not the output voltage Vrefl of the reference voltage generator 41 is to be outputted to the error amplifier 23. The second switch unit 42 is controlled by the third enable signal SW_EN, which is a periodic clock signal having the same frequency as the second enable signal VERF_EN, a delayed phase lagging behind that of the second enable signal VERF_EN, and a duty cycle smaller than that of the second enable signal VERF_EN.
The standby mode controller 46 receives a standby signal SLEEP and generates the first enable signal REG_EN, the second enable signal VERF_EN and the third enable signal SW_EN according to the standby signal.
As shown in
As shown in
In addition, the second enable signal VERF_EN and the third enable signal SW_EN are periodic clock signals when the voltage regulator circuit 40 is in either the normal mode or the standby mode. Because the voltage regulator circuit 40 utilizes the capacitor C2 to hold the voltage Vref at the input terminal of the error amplifier 23, the reference voltage generator 41 and the second switch unit 42 need not to always be held at the working state, and the voltage of the capacitor C2 may be held by the periodic operation. In addition, because the impedance at the input terminal of the error amplifier 23 is very large, the capacitor C2 may also be held at the stable voltage even if the capacitor C2 is charged sometimes. In this invention, because the reference voltage generator 41 and the second switch unit 42 only work periodically or sometimes, the DC quiescent current of the reference voltage generator 41 may be greatly reduced.
Furthermore, because the reference voltage generator 41 cannot output a stable reference voltage until a period of time has been elapsed after the second enable signal VERF_EN becomes the high logic level, the phase of the third enable signal SW_EN lags behind that of the second enable signal VERF_EN, and the duty cycle of the third enable signal SW_EN is also smaller than that of the second enable signal VERF_EN, such that the capacitor C2 may keep the stable voltage.
As shown in
Although the voltage regulator circuit with the low quiescent current in this invention further adds a standby mode controller 26(46) for generating the enable signal, the power consumption of the standby mode controller 26(46) is far smaller than that of the reference voltage generator, the error amplifier and the first switch unit. Thus, the quiescent current of the voltage regulator circuit of this invention is far smaller than that of the prior art voltage regulator circuit.
In the first embodiment, for example, if the standby mode controller consumes about A1 microamperes (uA), the error amplifier consumes about A2 microamperes, and the duty cycle of the first enable signal REG_EN may be set as X, then the ratio of the DC quiescent current that can be reduced in the standby mode is:
[A2−(A1+A2*X)]/A2*100%.
In the second embodiment, if the standby mode controller consumes about A1 microamperes, the error amplifier consumes about A2 microamperes, the reference voltage generator consumes about A3 microamperes, the duty cycle of the first enable signal REG_EN may be set as X, and the duty cycles of the second enable signal VERF_EN and the third enable signal SW_EN may be set as Y, then the ration of the DC quiescent current that can be reduced in the standby mode is:
[(A2+A3)−(A1+A2*X+A3*Y)]/(A2+A3)*100%.
The ratio of the DC quiescent current that can be reduced in the normal mode is:
[(A2+A3)−(A1+A2+A3*Y)]/(A2+A3)*100%.
For example, when A1=2 microamperes, A2=5 microamperes, A3=30 microamperes, X=1/256 and Y=1/256, the ratio of the DC quiescent current that can be reduced in the standby mode is 93.8%, and the ratio of the DC quiescent current that can be reduced in the normal mode is 79.6%.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.
Claims
1. A voltage regulator circuit comprising:
- a standby mode controller for receiving a standby signal and generating a first enable signal according to the standby signal, wherein the first enable signal is kept enabled when the standby signal is disabled and the first enable signal is periodically enabled when the standby signal is enabled;
- a reference voltage generator for receiving an operation voltage and generating a reference voltage;
- an amplifier for receiving the reference voltage and a stable output voltage and generating an amplified voltage, wherein the amplifier works only when the first enable signal is enabled; and
- a first switch unit for receiving the operation voltage and generating the stable output voltage at an output terminal, wherein the first switch unit is controlled by the first enable signal, and turned on when the first enable signal is enabled.
2. The voltage regulator circuit according to claim 1, further comprising a first capacitor, which is connected to the output terminal of the first switch unit in order to stabilize the output voltage.
3. The voltage regulator circuit according to claim 2, wherein the standby mode controller further receives the operation voltage and enables the first enable signal when the operation voltage is not stable.
4. The voltage regulator circuit according to claim 2, further comprising:
- a second switch unit connected between the reference voltage generator and the amplifier and controlled by the first enable signal; and
- a second capacitor connected to an output terminal of the second switch unit so as to stabilize a voltage at the output terminal of the second switch unit,
- wherein the second switch unit is turned on when the first enable signal is enabled.
5. The voltage regulator circuit according to claim 4, wherein the reference voltage generator further receives the first enable signal and works only when the first enable signal is enabled such that the quiescent current of the voltage regulator circuit can be reduced.
6. The voltage regulator circuit according to claim 2, wherein the reference voltage generator further receives a second enable signal and works only when the second enable signal is enabled.
7. The voltage regulator circuit according to claim 6, further comprising:
- a second switch unit connected between the reference voltage generator and the amplifier and controlled by a third enable signal; and
- a second capacitor connected to an output terminal of the second switch unit so as to stabilize a voltage at the output terminal of the second switch unit,
- wherein the second switch unit is turned on when the third enable signal is enabled.
8. The voltage regulator circuit according to claim 7, wherein the standby mode controller further generates the second enable signal and the third enable signal, both of which are kept enabled when the operation voltage is not stable and are periodically enabled when the operation voltage is stable.
9. The voltage regulator circuit according to claim 7, wherein the third enable signal and the second enable signal have the same frequency but a phase delay therebetween, and a duty cycle of the third enable signal is smaller than a duty cycle of the second enable signal.
Type: Application
Filed: Oct 19, 2005
Publication Date: May 25, 2006
Patent Grant number: 7106034
Applicant:
Inventors: Hung Chien (Hsin Chu City), Meng-Jyh Lin (Hsin Chu City)
Application Number: 11/252,791
International Classification: G05F 1/40 (20060101);