Method to eliminate PLL lock-up during power up for high frequency synthesizer

Abstract

A method and apparatus to eliminate PLL lock-up during power-up for a VCO. A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with a signal, wherein the signal from the VCO is at high frequency upon power up.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. provisional patent application Ser. No. 60/627,595, filed Nov. 12, 2004, entitled “RF CHIP FOR GLOBAL POSITIONING SYSTEM RECEIVER,” by Lloyd Jian-Le Jiang et al., which application is incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to Global Positioning System (GPS) receivers, and in particular, to a method and apparatus to eliminate Phase-Lock Loop (PLL) lock-up for high frequency synthesizers used in GPS receivers.

2. Description of the Related Art

The use of GPS in consumer products has become commonplace. Hand-held devices used for mountaineering, automobile navigation systems, and GPS for use with cellular telephones are just a few examples of consumer products using GPS technology.

As GPS technology is being combined with these devices, the GPS chips are being placed in widely ranging applications. Some of these applications require that the GPS receiver function at low power levels, where GPS receiver manufacturers utilize techniques to shut off portions of the GPS receiver to conserve power consumption.

However, when the power is turned on and off to portions of the GPS receiver, some of the components of the GPS receiver must be reset when powered up, which may place them in a condition that would provide errors for the GPS receiver. One of these components is a frequency synthesizer. At times, frequency synthesizers are placed in a condition called a “lock-up” condition, where the frequency output of the synthesizer cannot be changed as in normal operation. This prevents the frequency synthesizer from performing required functions in the GPS receiver.

It can be seen, then, that there is a need in the art to provide a method and apparatus for eliminating PLL lock-up during power up in GPS receivers.

SUMMARY OF THE INVENTION

To minimize the limitations in the prior art, and to minimize other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for eliminating PLL lock-up during power up for high frequency synthesizers.

A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal.

Such a method further optionally forces the VCO to high amplitude and high frequency during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation.

A Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency and high amplitude when the feedback loop is at a low voltage at power-up of the GPS receiver.

Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high amplitude and high frequency when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

FIG. 1A illustrates a block diagram of the related art;

FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art;

FIG. 2 illustrates divider operation regions of a divider of the present invention;

FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention;

FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention;

FIG. 4 illustrates an application of the PLL of the present invention; and

FIG. 5 illustrates a process chart for performing the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, reference is made to the accompanying drawings which form a part hereof, and which is shown, by way of illustration, several embodiments of the present invention. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

Overview

The present invention helps to solve the problem of lock-up when the power supply used to power the frequency synthesizer, and the associated PLL's with that synthesizer, by inverting the control voltage used to control the synthesizer itself.

FIG. 1A illustrates a block diagram of the related art.

Phase lock loop 100 is shown, with reference clock (refclk) 102 entering a phase detector 104. The output of the phase detector 104 is then coupled to a filter 106, which provides a control voltage 108 to a voltage controlled oscillator (VCO) 110. The output 112 frequency of the VCO 110 is used as an output of the PLL 100, and is also used as a feedback loop to a frequency divider 114, which, after division, is used as an input 116 to phase detector 104.

Phase detector then detects the phase difference between the reference clock 102 and the output 112 of the VCO 110. The phase detector 104 output 118 changes as the difference in phase changes, as does signal 108.

FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art.

Typically, as shown in FIGS. 1B and 1C, when signal 108 is low in voltage, as shown on point 120 of graph 122 in FIG. 1B, the output of VCO 110 is at a low frequency. Conversely, when signal 108 is high in voltage, point 124 on graph 122 shows that the output of the VCO 110 is high in frequency.

Similarly, when signal 108 is low in voltage, as shown on point 126 of graph 128 in FIG. 1C, the output of VCO 110 is at a low amplitude. Conversely, when signal 108 is high in voltage, point 130 on graph 128 shows that the output of the VCO 110 is high in frequency.

During a power up condition, the control voltage signal 108 is at a low voltage. This forces the VCO 110 to a low amplitude and low frequency condition. At low amplitudes, the divider 114 operates very poorly, especially for high frequency VCOs 110. The reason for this is that the divider 114 typically uses Current Mode Logic (CML), which is highly dependent on both amplitude and frequency. At the low frequency point 120 and low amplitude point 126, the divider 114 generates the wrong divide ratio, which generates signal 116 at a higher frequency than it should, which keeps forcing the VCO to lower and lower frequencies. Changing the reference clock signal 102 does not remedy this situation, because the feedback loop is stuck in this “lock-up” condition before the reference clock signal 102 can ever get through the phase detector. As such, the output 112 is at an incorrect frequency, and any circuitry using this output 112 will generate incorrect results.

FIG. 2 illustrates the operation regions of a divider of the present invention.

Graph 200 shows a correct divider operation region 202, an undesired operation region 204, and the minimum voltage point 206 and maximum voltage point 208. By changing the divider to operate at a frequency other than a minimum frequency when the voltage is low, the divider does not continue to force the VCO frequency lower and lower as in the PLL 100 shown in FIG. 1. Instead, the region 202, and, specifically, point 206, will be where the divider will start up in the present invention, which is the highest frequency that the VCO can put out. This condition remains until a corrective voltage is applied, i.e., signal 108, to lower the frequency, rather than having the system run to a low frequency all by itself. Further, a divider in accordance with the design of FIG. 2, which is the design of the present invention will provide the correct frequency division at lower voltages, allowing for a wider range of uses for the divider.

FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention.

Phase lock loop 300 is shown, with reference clock (refclk) 302 entering a phase detector 304. The output of the phase detector 304 is then coupled to a filter 306, which provides a control voltage 308 to a voltage controlled oscillator (VCO) 310. The output 312 frequency of the VCO is used as an output of the PLL 300, and is also used as a feedback loop to a frequency divider 314, which, after division, is used as an input 316 to phase detector 304.

Phase detector then detects the phase difference between the reference clock 302 and the output 312 of the VCO 310. The phase detector 304 output 318 changes as the difference in phase changes, as does signal 308.

FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention.

Unlike FIGS. 1B and 1C, FIGS. 3B and 3C show that when signal 308 is low in voltage, as shown on point 320 of graph 322 in FIG. 3B, the output of VCO 310 is at a high frequency. Conversely, when signal 308 is high in voltage, point 324 on graph 322 shows that the output of the VCO 310 is low in frequency.

Similarly, when signal 308 is low in voltage, as shown on point 326 of graph 328 in FIG. 3C, the output of VCO 310 is at a high amplitude. Conversely, when signal 308 is high in voltage, point 330 on graph 328 shows that the output of the VCO 310 is low in amplitude.

During a power up condition using the PLL 300 of the present invention, the control voltage signal 308 is at a low voltage, namely, at point 320. This forces the VCO 310 to a high amplitude and high frequency condition. At these points 320 and 326, divider 314 operates in the proper way, namely, in region 202, and, as such, does not drive the VCO 310 into a lock-up condition. Since the divider 310 is operating properly, the PLL 300 is properly moved by the divider 314, and lock-up is avoided.

Application of PLL

FIG. 4 illustrates an application of the PLL of the present invention.

GPS receiver 400 is shown, with PLL 300 shown providing output 312 to other parts of the circuitry within the radio frequency (RF) section 402 and the baseband section 404 of GPS receiver 400.

Process Chart

FIG. 5 illustrates a process chart for performing the present invention.

Box 500 illustrates coupling a divider to a Voltage Controlled Oscillator (VCO) to create a feedback loop.

Box 502 illustrates driving the divider with a signal, wherein the signal from the VCO is at high frequency when a control signal voltage is at a low voltage.

CONCLUSION

In summary, the present invention describes a method and apparatus to eliminate PLL lock-up during power-up for a VCO. Although described with respect to PLLs, the techniques and devices described herein would work for other feedback loops, and such other feedback loops are considered within the scope of the present invention. Also, although described with respect to VCOs, other types of oscillators or controllable frequency sources can be used without departing from the scope of the present invention. Further, the present invention would operate within the scope of the invention if the VCO would provide only the response of FIG. 3B, or FIG. 3C, and does not require both. For example, the VCO could only provide a high frequency and low amplitude or low frequency and high amplitude while the divider will operate in the preferred region 202 of FIG. 2. Although described with respect to a GPS receiver herein, the present invention is useful in many devices, wherever a feedback loop is used to control frequency output.

A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal.

Such a method further optionally forces the VCO to high frequency and high amplitude during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation.

A Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency when the feedback loop is at a low voltage at power-up of the GPS receiver.

Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high frequency and high amplitude when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.

The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but by the claims appended hereto and the equivalents thereof.

Claims

1. A method for preventing lock-up in a feedback loop, comprising:

coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop; and

driving the divider with a signal, wherein an output of the VCO is at high frequency when a control signal is at a low voltage.

2. The method of claim 1, wherein the output of the VCO is at a high amplitude when the control signal is at a low voltage.

3. The method of claim 2, wherein the feedback loop is a phase-locked loop.

4. The method of claim 3, wherein the divider is operated in a preferred region of operation upon power up.

5. The method of claim 4, wherein the feedback loop is used in a GPS receiver.

6. A Global Positioning System (GPS) Receiver, comprising:

a radio frequency section;

a baseband section; and

a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency at power-up of the GPS receiver.

7. The GPS receiver of claim 6, wherein the frequency source is a Voltage Controlled Oscillator (VCO).

8. The GPS receiver of claim 7, wherein the feedback loop is a phase-locked loop (PLL).

9. The GPS receiver of claim 8, further comprising a divider, coupled to the frequency source within the phase-locked loop.

10. The GPS receiver of claim 9, wherein the divider is operated in a preferred region of operation at power up.