Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate
A layer structure usable in manufacturing an integrated circuit is made, in a single apparatus, by a particular process in which a patterned substrate is provided. An electrolyte solution, out of which a conductive material can be plated under an applied potential, is supplied over a surface of the patterned substrate, and a potential is applied so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate. The film of conductive material is preferably polished as it is deposited. The conductive material is then removed from field regions of the patterned substrate, while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.
This application claims the priority of U.S. provisional application No. 60/198,371, filed Apr. 19, 2000, the disclosure of which is expressly incorporated by reference herein.
BACKGROUND AND SUMMARY OF THE INVENTIONMulti-level integrated circuit manufacturing requires many steps of metal or metal alloy and insulator film depositions followed by photoresist patterning and etching or other material removal operation. After photolithography and etching, the resulting wafer or substrate surface is non-planar and contains many features such as vias, lines or channels, test pads and bond pads. Often, these features need to be filled with a specific material such as a metal, and then the wafer topographic surface needs to be planarized, making it ready for the next level of processing.
Electrodeposition is a widely accepted technique for depositing a highly conductive material such as copper (Cu) into the features on the semiconductor wafer surface. Chemical mechanical polishing (CMP) is then employed to planarize the resulting surface and to polish the conductive material off of the field regions of the surface, leaving the conductive material only within the features themselves. Another approach by which the excess metal can be removed from the wafer surface is electro-polishing, which is often also referred to as “electrochemical etching” or “electro-etching”. Chemical etching can also be used to remove the excess metal or other conductive material. In chemical etching, the material to be removed from the wafer surface is brought into contact with an etching solution. A chemical reaction between the etching solution and the material causes dissolution of the material and removal of the material from the wafer surface. In electro-polishing, both the material to be removed and a conductive electrode are dipped into an electro-polishing electrolyte. Typically, an anodic (positive) voltage is applied to the material with respect to the conductive electrode. With the help of the applied voltage, the material is electrochemically dissolved and removed from the wafer surface. Electro-polishing is generally considered to be more controllable and faster than chemical etching.
In
The surface of the structure in
Removal of the large and non-uniform overburden of
One prior art process for electrochemical planarization is disclosed in U.S. Pat. No. 5,256,565 to Bernhardt et al. In that process, an already planarized metal film is etched back to the underlying dielectric layer by electro-polishing, ion milling or other procedure. However, this technique requires the use of several steps, i.e. deposition, planarization, and etching, carried out in different apparatus, making it very costly. For example, in the Bernhardt et al. method, Cu deposition is carried out with standard electroplating equipment, which is expected to give a Cu deposit as depicted in
The last step in the prior art technique disclosed by the Bernhardt et al. patent is the Cu removal step. This step is carried out in a separate electro-polishing or ion etching apparatus. Electro-polishing uses a special electrochemical etching solution in an electro-polishing apparatus. Ion milling requires a separate vacuum system tooled with special means of ion bombarding the substrate surface.
There is a need for the development of high-throughput techniques which can yield planar metal fillings that are formed in the surface features of semiconductor substrates. According to the present invention, such high-throughput techniques involve making, in a single apparatus, a layer structure usable in manufacturing an integrated circuit by performing certain operations. These operations include providing a patterned substrate, supplying an electrolyte solution out of which a conductive material can be plated, under an applied potential, over a surface of the patterned substrate, applying a potential so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate, and polishing the film of the conductive material as it is deposited. After the conductive material film has been deposited in this manner, the conductive material is removed from field regions of the patterned substrate while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.
The field regions are regions of an insulator layer forming part of the patterned substrate. In one preferred embodiment of the invention, at least one additional operation of depositing conductive material is performed after removing the conductive material from these field regions and before electrically isolating the deposits. Electro-etching of the conductive material deposited by each additional depositing operation may be performed.
Preferably, the potential is applied between the surface of the patterned substrate and an anode in the electrolyte solution.
The patterned substrate includes an insulator layer and a barrier layer overlying the insulator layer. The field regions are defined on the insulator layer, and the deposits of conductive material are electrically isolated by removing the barrier layer from these field regions.
At least one additional operation of depositing conductive material before electrically isolating the deposits may be performed. The deposits are annealed after the at least one additional conductive material depositing operation.
The process may further include annealing the deposits after they are electrically isolated. Electrical isolation of the deposits can be performed by chemical mechanical polishing. Removal of the conductive material can be performed by electro-etching the film of the conductive material. According to one feature of the invention, the film is electro-etched by inverting a polarity of the potential which was originally applied to plate the conductive material.
As an alternative to chemical mechanical polishing, electrical isolation of the deposits can be performed by either reactive ion etching or wet etching.
The film of conductive material may be any of Cu, doped Cu, a copper alloy, Pt, Ag, Au, Pd, Ni, a Pb—Sn alloy, a lead-free solderable alloy, and a magnetic alloy. Preferably, the film is deposited out of the electrolyte solution and polished simultaneously.
BRIEF DESCRIPTION OF THE DRAWINGS
The first step of the disclosed process is the deposition of conductive material having a planar surface on the surface of the patterned substrate with features. This can be accomplished by the electrochemical mechanical deposition (ECMD) tool that was previously disclosed by commonly assigned U.S. patent application Ser. No. 09/201,929, filed Dec. 1, 1998, titled METHOD AND APPARATUS FOR ELECTROCHEMICAL MECHANICAL DEPOSITION. In the present description, Cu is used as an example of the conductive material to be deposited. However, the invention can be used to deposit other commonly used materials such as doped Cu films, Cu-alloys, Pt, Ag, Au, Pd, Ni, Pb—Sn alloys, Pb-free solderable alloys, magnetic alloys, and others.
In the ECMD method, the deposition electrolyte is fed to a narrow gap between the substrate surface and a pad, which is mounted on or in the near proximity of an anode. The solution makes physical contact to the anode as well as to the substrate surface. The pad, which is typically abrasive, is physically pushed against the substrate surface. Commonly assigned, co-pending U.S. patent application Ser. No. 09/511,278, filed Feb. 23, 2000, titled PAD DESIGNS AND STRUCTURES FOR A VERSATILE MATERIALS PROCESSING APPARATUS, and Ser. No. 09/621,969, filed Jul. 21, 2000, titled PAD DESIGNS AND STRUCTURES WITH IMPROVED FLUID DISTRIBUTION, relate to certain pad configurations. When the substrate and pad are moved with respect to each other and a negative voltage is applied to the substrate surface with respect to the anode, metal gets plated out of the solution onto the patterned substrate surface and simultaneously gets polished, such that che metal deposition on the field is minimized, to yield the planar structure depicted in
The modified plating solution referred to is formed from standard plating solution compositions that are modified to allow the deposition of a high quality Cu layer, and at the same time allow either simultaneous or sequential polishing and planarization of the deposited layer. The terms “electrolyte solution” and “plating solution” are used interchangeably throughout the following description. In this approach, commercially available, highly acidic Cu plating solutions are modified by the addition of oxidizers which do not appreciably affect the pH of the solution or the quality of the plated Cu layer. No slurry or particles are included in the formulation. Polishing and planarization is achieved using a fixed abrasive pad.
For plating, a potential is applied between an electrical contact to a substrate (e.g. a wafer) which is to be plated and an electrical contact to an anode assembly making the substrate surface more negative than the anode assembly. The terms “substrate” and “wafer” are used interchangeably here. Under applied potential, a high quality layer of metal plates out of the modified plating solution onto the wafer surface. By adjusting the gap between an abrasive polishing pad and the wafer surface and/or by adjusting the pressure with which the pad and the wafer surface touch each other, one can achieve just plating, or plating and polishing. For example, if there is a gap between the wafer surface and the pad, plating is expected to take place over the whole wafer surface as illustrated in
If the pad and the wafer surface are touching at low pressures, then plating can freely take place in the holes in the substrate where there is no physical contact between the wafer surface and the abrasive pad, but the plating rate will be reduced on the top surfaces where there is physical contact between the pad and the surface. The result is a metal deposit with uniform metal overburden across the surface of the substrate as shown in
It is not fully understood how the addition of small amounts of oxidizers in the highly acidic Cu plating solutions allows the use of these solutions for plating and planarization. However, it is possible that the surface layer formed on the Cu deposit by the presence of oxidizers does not interfere with the plating of a good quality Cu layer, but at the same time can be efficiently removed from the sections of the film where the pad contacts it with some pressure. The amount of oxidizer added to the plating solution may be less than 500 ppm; preferably, however, it should be more. Oxidizer concentration may typically be in the 0.01 wt. % to 10 wt. % range. Both inorganic and organic oxidizers, either pure or mixed, or their mixtures can be used as modifying agents, but organic oxidizers are preferred. Among the many organic oxidizers known to those in the field of chemistry, the preferred modifying agents are organic nitrites and nitrates. Although butyl nitrite is an organic oxidizer that was used as the modifying agent in the following examples, other modifying agents can also be used to obtain the same result. For example, other organic oxidizers, preferably organic nitrites, can be used. Organic nitrites include, but are not limited to, alkyl nitrites, aromatic nitrites, and polyaromatic nitrites. Alkyl nitrites include, but are not limited to, primary, secondary and tertiary compounds of methyl, ethyl, propyl, butyl, and amyl nitrites. Additionally, nitrates of the above compounds may also be used.
Although the examples use Cu deposits, it should be understood that many other conductive materials such as Cu alloys, W, Au, Ni, Pt, Pd, Ag, Co, Sn, Pb and their alloys can be used.
EXAMPLE 1 Standard Electrolyte SolutionA Cu-sulfate based Cu plating solution was prepared as follows:
70 grams per liter of CuSO4+5H2O, 150 grams per liter of concentrated H2SO4, and 70 ppm per liter of Cl− ions were mixed in enough water to make 10 liters of solution. Twenty-five ml of Ultrafill S2001®, 1.0 ml of Ultrafill A2001® from Shipley were then added to obtain a standard good quality plating electrolyte.
This solution was used for Cu plating on a 200 mm diameter wafer surface. The wafer surface contained sub-micron size features as well as features in the 10-100 micron range. The pad was a fixed abrasive pad supplied by 3M® company. The diameter of the pad was 180 mm and the anode assembly was oscillated in the horizontal direction so that plating could be achieved on all areas on the larger wafer surface. During plating, the distance between the pad and the wafer surface was kept at around 0.1 cm. The plating current was 2 amperes and the plating solution flow was 5 liters/minute. The wafer was rotated at 75 rpm and the anode assembly with the pad was rotated at 100 rpm in the same direction. Several wafers were plated for times ranging from 90 seconds to 4 minutes. The Cu deposits after aging at room temperature for one day had a resistivity of below 2×10−6 ohm-cm, indicating good material quality.
EXAMPLE 2 Polishing and Planarization Using Standard Electrolyte SolutionThe plating experiment of Example 1 was repeated, except this time, after an initial period of 30 seconds, the pad was pushed against the wafer surface at a pressure of 1 psi for plating as well as polishing and planarization. The resulting Cu deposit had a rough surface with deep scratches apparently caused by the abrasive pad. There were also Cu particles smeared all over the surface of the wafer. Very little amount of material removal was achieved because material removed from one region of the surface by the action of the abrasive pad was probably deposited back onto the surface at another region in the form of smeared particles, which were welded or bonded to the substrate surface. The substrate defect level was extremely high and feature filling was poor.
EXAMPLE 3 Modified Electrolyte Solution Five ml per liter of butyl-nitrite were added as a modifying agent to the electrolyte of Example 1 and the plating and polishing experiment of Example 2 was repeated using this modified plating solution. The resulting Cu deposit was highly planar and was similar to the structure shown in
An anode assembly is disclosed in co-pending U.S. patent application Ser. No. 09/568,584, filed May 11, 2000, titled ANODE ASSEMBLY FOR PLATING AND PLANARIZING A CONDUCTIVE LAYER. A substrate holder/head assembly design is provided by co-pending U.S. patent application Ser. No. 09/472,523, filed Dec. 27, 1999, titled WORK PIECE CARRIER HEAD FOR PLATING AND POLISHING. The disclosures of these additional U.S. patent applications are also incorporated by reference herein as non-essential subject matter.
The second step of the present invention is carried out in the same deposition chamber and in the same electrolyte, and involves inverting the polarity of the applied potential, i.e. voltage, thereby making the substrate surface more positive than the anode. The circuitry used for application and adjustment of the applied voltage, and for inverting the voltage polarity, is well known and commonly used. Under these conditions, the already planar surface of the deposited material, such as the surface of the material shown in
It is possible to continue the electro-etching process that yields the structure of
The structures depicted in
One reason why prior art electro-polishing processes are carried out in special electro-polishing electrolytes is that when regular plating electrolytes are used for electro-polishing, they yield rough film surfaces. In this respect, it is more proper to refer to an electro-etching process such as the one we perform in our process as electrochemical etching or electro-etching rather than electro-polishing because the word “polishing” suggests that the resulting surface of the etched film is smooth and polished. Electro-polishing electrolytes may be high resistance and formulated using weak acids and special leveling additives to yield highly polished surfaces. Strong acids, such as phosphoric acid, neutral mineral salt solutions and their various combinations may also be used. Electrodeposition cannot be carried out with typical electro-polishing solutions. The unique feature of our invention is the use of the electroplating solution as the plating solution as well as the electro-etching solution in the same apparatus. The reason our invention can utilize the same solution for both plating and electro-etching is that our technique can planarize rough surfaces resulting from the electro-etching step, if necessary. We now will describe this unique feature.
After deposition of a planar film (
If the global uniformity of the etched Cu film on the patterned substrate of
If the electro-etching time period is extended so that some etching is also done within the features (
A structure such as the one shown in
When the structure of either
In other applications, the plated material deposited in the features of
In each embodiment of the invention described above, both the insulator layer 2 and the barrier layer 3 have conventional compositions such as those disclosed, for example, by U.S. Pat. No. 5,930,669 to Uzoh which names as the inventor one of the co-inventors of the subject matter of the present application. The insulator layer 2 may, for example, be composed of SiO2 or another conventional dielectric material, while suitable materials that may be employed for the barrier layer 3 include, but are not limited to, Cr, Ti, TiN, W, Ta, TaN, TaN/Ta, Ta/TaN, Ta/TaN/Ta, TaN/Ti, Ta—Ti alloy, Ta—Cr alloy and Ti—Ta—Cr alloys.
In each of the embodiments described above, voltages are applied to electroplate at current densities of approximately 5-50 milliamperes per cm2. Voltages are applied to obtain electro-etching, in each of the embodiments described, at current densities of approximately 0.1-20 milliamperes per cm2. These ranges, however, are not to be considered limiting.
The foregoing disclosure has been set forth merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof.
Claims
1. A process of making, in a single apparatus, a layer structure usable in manufacturing an integrated circuit comprising:
- providing a patterned substrate,
- supplying an electrolyte solution out of which a conductive material can be plated, under an applied potential, over a surface of said patterned substrate,
- applying a potential so as to deposit a film of said conductive material out of the electrolyte solution and over said surface of said patterned substrate and polishing the film of said conductive material,
- removing said conductive material from field regions of said patterned substrate while leaving deposits of said conductive material in features defined in said patterned substrate, and
- electrically isolating said deposits of said conductive material.
2. The process of claim 1, wherein the field regions are regions of an insulator layer forming part of said patterned substrate.
3. The process of claim 1, and further comprising at least one additional operation of depositing conductive material after removing said conductive material and before electrically isolating said deposits.
4. The process of claim 3, and further comprising electro-etching said conductive material deposited by each additional operation of depositing.
5. The process of claim 1, wherein said potential is applied between said surface of said patterned substrate and an anode in the electrolyte solution.
6. The process of claim 1, wherein said patterned substrate includes an insulator layer and a barrier layer overlying said insulator layer, wherein said field regions are defined on said insulator layer, and wherein said deposits of said conductive material are electrically isolated by removing said barrier layer from said field regions.
7. The process of claim 1, and further comprising at least one additional operation of depositing conductive material before electrically isolating said deposits.
8. The process of claim 7, and further comprising annealing said deposits after said at least one additional operation of depositing conductive material.
9. The process of claim 1, and further comprising annealing said deposits after electrically isolating the deposits.
10. The process of claim 1, wherein electrically isolating said deposits is performed by chemical mechanical polishing.
11. The process of claim 1, wherein removing said conductive material is performed by electro-etching the film of the conductive material.
12. The process of claim 11, wherein the film is electroetched by inverting a polarity of said potential.
13. The process of claim 1, wherein electrically isolating said deposits is performed by reactive ion etching.
14. The process of claim 1, wherein electrically isolating said deposits is performed by wet etching.
15. The process of claim 1, wherein said conductive material is any of Cu, doped Cu, a copper allow, Pt, Ag, Au, Pd, Ni, a Pb—Sn allow, a lead-free solderable alloy, and a magnetic alloy.
16. The process of claim 1, wherein the film is deposited out of said electrolyte solution and polished simultaneously.
17. A method of forming a planar conductive structure usable in manufacturing an interconnect for an integrated circuit, the method comprising:
- providing a substrate having a top portion that includes a surface portion and a cavity portion, wherein the cavity portion has at least a first cavity having a width of less than one micron and a second cavity having a width larger than 10 microns; and
- depositing a planar conductive layer within the cavity portion and on the surface portion, wherein the planar conductive layer, as deposited, has a predetermined thickness range over the surface portion that is between one tenth and one half of the thickness of the planar conductive layer within the cavity portion.
18. The method of claim 17, wherein providing comprises forming the top portion by depositing an insulator layer and a barrier layer overlying said insulator layer and forming the cavities in the insulator layer after depositing the insulator layer.
19. The method of claim 17, wherein the planar conductive material comprises copper or copper alloy.
20. The method of claim 17, wherein the planar conductive material comprises copper.
21. The method of claim 17, wherein depositing is electrochemical mechanical deposition, comprising:
- feeding an electrolyte to the top portion, wherein the electrolyte is in contact with an anode; and
- contacting a pad to the top portion while feeding the electrolyte while moving the substrate and pad with respect to each other.
Type: Application
Filed: Jan 30, 2006
Publication Date: Jun 8, 2006
Inventors: Bulent Basol (Manhattan Beach, CA), Cyprian Uzoh (Milpitas, CA), Homayoun Talieh (San Jose, CA)
Application Number: 11/343,477
International Classification: C25D 5/02 (20060101);