Semiconductor structure with partially etched gate and method of fabricating the same
A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
This application is a Divisional of co-pending application Ser. No. 10/695,739 filed on Oct. 30, 2003, which claims priority of Taiwan Application No. 092107601 filed on Apr. 3, 2003, and for which priority is claimed under 35 U.S.C. §120. The entire contents of each of the above-identified applications are hereby incorporated by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor device and the fabricating method thereof. More particularly, it relates to a semiconductor structure with partially etched gate and method of fabricating the same.
2. Description of the Related Art
In general, the gate structure of a metal oxide semiconductor field effect transistor (MOSFET) device is composed of a metal layer and an oxide layer stacked on a semiconductor substrate. Typically, the metal layer is substituted with a polysilicon layer to act as a gate conductive layer of the gate structure because of poor adhesion between metal and the oxide layer. However, the resistance of polysilicon materials is higher than that of the metal such that the polysilicon layer is usually doped with impurities to lower the resistance thereof. After doping with impurities, the conductivity of the polysilicon layer is reduced but not low enough to act as a conductive layer. A possible solution is to form a metal silicide layer such as tungsten silicide (WSi) layer thereon for improving gate conductivity. In addition, a cap layer is further disposed over the metal silicide layer of the gate structure, and a lining layer and spacers are respectively disposed beside the gate structure to insulate conductive materials thereof. Preferably, the cap layer and the spacer material can be silicon nitride to provide better insulation.
After formation of the gate structure of individual MOSFET device, which acts as a wordline (WL), a thick insulating layer (typically borophosphatesilicate glass (BPSG)) is formed over the wordline. Then an opening is etched through the insulating layer to the substrate between two adjacent wordlines by conventional photolithography and etching. Conductive material is then filled in the opening to form a contact node that connects the follow-up devices such as a bitline. The described process is the so-called “self-aligned contact” (SAC) opening process and is a frequently used semiconductor fabrication procedure.
Nevertheless, during formation of the SAC opening, the spacers are exposed and inevitably removed in part and conductive materials of the gate structure are still protected by the spacers and are not revealed. Once the conductive materials of the gate structure are revealed, an undesirable connection between the gate structure and the bitline contact (CB) can thus occur, referring to a so-called “CB to WL short”, and the MOSFET device and the electrical performance thereof cannot be achieved. Conventional semiconductor fabrication often results in over-etched spacers thus revealing the conductive materials of the gate structure causing the so-called “CB to WL short” which results in product loss. In other aspect, another so-called “CB open” can also occur between an insufficiently etched opening of the contact, causing disconnections between the MOSFET device and devices formed in follow-up processes.
Moreover, the aspect ratio between two adjacent gate structures is enlarged, with a shorter distance therebetween due to the increased device integration. Thus, voids in a poorly formed inter-layer dielectric (ILD) layer can cause undesirable shorts between two adjacent contacts such as the bitline contacts during the filling of conductive materials in a subsequent process, so called “CB to CB short”, causing device loss and decreased yield.
Thus, a better semiconductor structure for preventing the described undesirable shorts or openings is called for.
SUMMARY OF THE INVENTIONAccordingly, an object of the invention is to provide a semiconductor structure with a partially etched gate to avoid undesirable shorts between bitlines and wordlines or between two adjacent bitlines and bitline openings caused by insufficient etching during formation of device contacts.
Another object of the invention is to provide a fabrication method of a semiconductor structure with partially etched gate that ameliorates the described problems.
Thus, a semiconductor structure with a single-sided partially etched gate in accordance with one embodiment of the invention comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer disposed on one sidewall of the gate structure is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
Moreover, a method of forming the semiconductor structure with single-sided partially etched gate comprises the steps of providing a semiconductor substrate with at least two adjacent gate structures thereon, wherein each gate structure is composed of a gate dielectric layer, a gate conductive layer, a cap layer, sequentially stacked on the substrate, and a lining layer covered on sidewalls thereof. Then a protective layer and a masking layer are sequentially formed over the gate structures and an opening is formed in the masking layer and the protective layer. The protective layer in the opening is etched to partially expose the lining layer covering one sidewall of the two adjacent gate structures. Next, after the exposed lining layers are removed, the masking layer and the protective layer are then removed. Next, a spacer is formed overlying sidewalls of each gate structure to form a plurality of single-sided partially etched gate structures. In addition, an inter-layer dielectric layer is formed over the gate structures and a bitline contact is formed in the inter-layer dielectric layer to expose the substrate and portions of the adjacent gate structures therein. Moreover, after removal of the exposed lining layers the gate conductive layer adjacent to the exposed lining layer can also be partially removed.
A semiconductor structure with a dual-sided partially etched gate in accordance with another embodiment of the invention comprises a gate dielectric layer, a gate conductive layer and a cap layer, sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer disposed on two sidewalls of the gate structure is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer to expose the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.
Moreover, a method of forming the semiconductor structure with dual-sided partially etched gate comprises the steps of providing a semiconductor substrate with at least two adjacent gate structures thereon, wherein each gate structure is composed of a gate dielectric layer, a gate conductive layer, a cap layer, sequentially stacked on the substrate, and a lining layer covered on sidewalls thereof. A protective layer is then formed over the gate structures and portions of the protective layer are etched to partially expose the lining layer covering two sidewalls of the gate structures. After the exposed lining layers and the protective layer are removed, a spacer is formed overlying sidewalls of the gate structures to form a plurality of gate structures with dual-sided partially etched gate conductive layer. In addition, an inter-layer dielectric layer is formed, covering the gate structure, and a bitline contact is formed in the inter-layer dielectric layer to expose the substrate and portions of the gate structures therein, wherein the lining layers of the exposed gate structures are partially removed.
The semiconductor structure with single-sided or dual-sided partially etched gates in accordance with the present invention can prevent the so-called “CB to WL short”, “CB open” or “CB to CB short” and pitches between two adjacent gate structures can be enlarged to provide a larger window for the opening formation of the self-aligned contact (SAC) process to meet the demand for line/pitch shrinkage of gate structures.
Moreover, the semiconductor structure with partially etched gates in accordance with the present invention will not affect regions receiving ion implantation such as source/drain implantation and channel length of the partially etched gate structure remains the same and will not be affected by the structure thereof. The method of the present invention can be slightly modified from the in-line processes and quickly and easily applied to the fabrication process.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The method of fabricating a semiconductor structure with partially etched gate in accordance with one embodiment of the invention is shown through
In
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In
At this point, those skilled in the art can adjust the height of the remaining protective layer 22 by controlling the described etching of the protective layer 22 within the opening OP to further expose the polysilicon layer 14 of the gate conductive layer after removal of the exposed lining layer 20. Thus, exposure of the gate conductive layer can be adjusted and is not restricted to exposure of the previously formed metal silicide layer 16.
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Moreover, the photolithography step for forming the described opening OP and OP′ in first masking layer 24 and second masking layer 32, respectively, is not restricted to conventional photolithography. Nanoimprint lithography (NIL) is also applicable.
Thus, a semiconductor structures with a partially etched gate in accordance with one embodiment of the present invention is respectively illustrated in
In
Thus in
A method of fabricating a semiconductor structure with a partially etched gate in accordance with another embodiment of the invention is shown in
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Moreover, the processes shown in
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At this point, those skilled in the art can adjust height of the remaining protective layer 22 by controlling the described etching of the protective layer 22 within the opening OP to further expose the polysilicon layer 14 of the gate conductive layer after the removal of the exposed lining layer 20. Thus, exposure of the gate conductive layer can be adjusted and is not restricted to exposure of the previously formed metal silicide layer 16.
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Moreover, the photolithography for forming the described opening QP′ in second masking layer 32 is not restricted to the conventional photolithography. Nanoimprint lithography (NIL) can also be applied.
Thus, a semiconductor structure with a partially etched gate in accordance with another embodiment of the present invention can be respectively illustrated in
In
Thus in
The semiconductor structure with single-sided or dual-sided partially etched gates is shown in
In addition, removal of portions of the gate conductive layer in a gate structure can be controlled by the described fabricating methods of the present invention to maintain the sheet resistance of a gate. Moreover, removal of the lining layer adjacent to materials of the gate conductive layer such as a metal silicide layer therein can enlarge the pitch (referring to the distance X shown in
Applications of the SAC process based on the gate structure with a single or dual-sided partially etched gate conductive layer avoids the conventional problems such as CB to WL short, CB open, or CB to CB short. The fabrication method can be slightly modified from in-line processes and can be easily and quickly adapted to the fabrication process.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A method of fabricating a semiconductor structure with partially etched gate, comprising the steps of:
- providing a semiconductor substrate with at least two adjacent gate structures thereon, wherein each gate structure is composed of a gate dielectric layer, a gate conductive layer, a cap layer, sequentially stacked on the substrate, and a lining layer covered on sidewalls thereof;
- sequentially forming a protective layer and a masking layer over the gate structures;
- forming an opening in the masking layer and etching the protective layer thereunder to partially expose the lining layer covering one sidewall of the two adjacent gate structures;
- removing the exposed lining layers;
- removing the masking layer and the protective layer; and
- forming a spacer overlying sidewalls of each gate structure to form a plurality of single-side partially etched gate structures.
2. The method as claimed in claim 1, further comprising, after removing the exposed lining layers, the step of partially removing the gate conductive layer adjacent to the exposed lining layer.
3. The method as claimed in claim 1, further comprising the steps of:
- forming an inter-layer dielectric layer over the gate structures; and
- performing photolithography and etching to form a bitline contact in the inter-layer dielectric layer and exposing the substrate and portions of the adjacent gate structures therein.
4. The method as claimed in claim 1, wherein the gate conductive layer is composed of a polysilicon layer and a metal silicide layer.
5. The method as claimed in claim 4, wherein material of the metal silicide layer is tungsten silicide.
6. The method as claimed in claim 1, wherein the protective layer is an anti-reflection coating (ARC) layer.
7. The method as claimed in claim 1, wherein material of the masking layer is photoresist (PR).
8. The method as claimed in claim 1, wherein materials of the cap layer and the spacer are silicon nitride.
9. The method as claimed in claim 1, wherein the lining layer is a rapid thermal oxide (RTO) layer.
10. The method as claimed in claim 4, wherein the gate structure adjacent to the exposed lining layer is the metal silicide layer.
11. The method as claimed in claim 3, wherein the opening is substantially relative to a position of the bitline contact.
12. The method as claimed in claim 3, wherein the method for forming the opening and the bitline contact is nanoimprint lithography (NIL) or photolithography.
13. The method as claimed in claim 1, wherein the reticle for forming the opening is bitline contact node reticle or bitline contact reticle.
14. The method as claimed in claim 1, wherein removal of the exposed lining layer is achieved using diluted hydrofluoric acid (DHF) or buffer of etching (BOE) etchant.
15. The method as claimed in claim 2, wherein partial removal of the gate conductive layer is achieved using of RCA1 etchant.
16. A method of fabricating a semiconductor structure with partially etched gate, comprising the steps of:
- providing a semiconductor substrate with at least two adjacent gate structures thereon, wherein each gate structure is composed of a gate dielectric layer, a gate conductive layer, a cap layer, sequentially stacked on the substrate, and a lining layer covered on sidewalls thereof;
- forming a protective layer over the gate structures;
- etching portions of the protective layer to partially expose the lining layer covering two sidewalls of each gate structure;
- removing the exposed lining layers;
- removing the protective layer; and
- forming a spacer overlying sidewalls of each gate structures to form a plurality of dual-sided partially etched gate structure.
17. The method as claimed in claim 16, further comprising, before removing the partially exposed lining layers, the steps of:
- forming a masking layer over the protective layer; and
- forming a plurality of masking patterns in the masking layer, respectively covering the protective layer over the gate structures.
18. The method as claimed in claim 16, further comprising, after removing the exposed lining layers, the step of partially removing the gate conductive layer adjacent to the exposed lining layers.
19. The method as claimed in claim 16, further comprising the steps of:
- forming an inter-layer dielectric (ILD) layer over the gate structures; and
- performing photolithography and etching to form a bitline contact in the inter-layer dielectric layer and exposing the substrate and portions of the adjacent gate structures therein.
20. The method as claimed in claim 16, wherein the gate conductive layer is composed of a polysilicon layer and a metal silicide layer.
21. The method as claimed in claim 16, wherein materials of the protective layer are an anti-reflection coating (ARC) and photoresist (PR).
22. The method as claimed in claim 16, wherein the protective layer is an anti-reflection coating (ARC) layer and the masking layer is a photoresist (PR) layer.
23. The method as claimed in claim 16, wherein materials of the cap layer and the spacer are silicon nitride.
24. The method as claimed in claim 19, wherein the gate structure adjacent to the exposed lining layer is the metal silicide layer.
25. The method as claimed in claim 16, wherein removal of the exposed lining layer is achieved using diluted hydrofluoric acid (DHF) or buffer of etching (BOE) etchant.
26. The method as claimed in claim 18, wherein partially removing the gate conductive layer is achieved using RCA1 solution containing ammonium hydroxide (NH40H) and hydrogen peroxide (H2O2).
Type: Application
Filed: Jan 25, 2006
Publication Date: Jun 15, 2006
Inventors: Yueh-Chuan Lee (Nantou County), Ming-Sheng Tung (Hualian County)
Application Number: 11/338,679
International Classification: H01L 21/311 (20060101); H01L 21/461 (20060101); H01L 21/302 (20060101);