Stacking system and method
The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
This application is a continuation of U.S. application Ser. No. 10/400,309 filed Mar. 27, 2003, which is a continuation of U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, now issued as U.S. Pat. No. 6,576,992, each of which is hereby incorporated by reference for all purposes.
TECHNICAL FIELDThe present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages.
BACKGROUND OF THE INVENTIONA variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.
One family of alternative packages is identified generally by the term “chip scale packaging” or CSP. CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
CSP has enabled reductions in size and weight parameters for many applications. For example, micro ball grid array (μBGA) for flash and SRAM and wirebond on tape or rigid laminate CSPs for SRAM or EEPROM have been employed in a variety of applications. CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA) recently described in proposed JEDEC standard 95-1 for DSBGA. To meet the continuing demands for cost and form factor reduction with increasing memory capacities, CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel recently undertook support of what are called the S-CSP specifications for flash and SRAM applications. Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not provide a technology for stacking chip scale packages. Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.
There are several known techniques for stacking packages articulated in chip scale technology. The assignee of the present invention has developed previous systems for aggregating μBGA packages in space saving topologies. The assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.
In U.S. Pat. No. 6,205,654 B1 owned by the assignee of the present invention, a system for stacking ball grid array packages that employs lead carriers to extend connectable points out from the packages is described. Other known techniques add structures to a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM with angular placement of the packages. Such techniques provide alternatives, but require topologies of added cost and complexity.
U.S. Pat. No. 6,262,895 B1 to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs. The Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP. The flex circuit is said to have pad arrays on upper and lower surfaces of the flex.
The flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array. To create the package of Forthun, a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package. The sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package. Thus, as described in the Forthun disclosure, a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.
The previous known methods for stacking CSPs apparently have various deficiencies including complex structural arrangements and thermal or high frequency performance issues. Typically, the reliability of chip scale packaging is closely scrutinized. During such reliability evaluations, CSP devices often exhibit temperature cycle performance issues. CSPs are generally directly mounted on a PWB or other platform offset from the PWB by only the height of the ball or bump array emergent from the lower surface of the CSP. Consequently, stresses arising from temperature gradients over time are concentrated in the short lever arm of a low-height ball array. The issues associated with temp cycle performance in single CSPs will likely arise in those prior art CSP stacking solutions where the stack is offset from the PWB or application platform by only the height of the lower CSP ball grid array.
Thermal performance is also a characteristic of importance in CSP stacks. To increase dissipation of heat generated by constituent CSPs, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized. Prior art solutions to CSP stacking do not, however, address thermal gradient minimization in disclosed constructions.
What is needed, therefore, is a technique and system for stacking integrated circuits packaged in chip scale technology packaging that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods.
SUMMARY OF THE INVENTIONThe present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP packages of a variety of sizes and configurations ranging from typical BGAs with footprints somewhat larger than the contained die to smaller packages such as, for example, die-sized packages such as DSBGA. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with a pair of flex circuits. Each of the pair of flex circuits is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB).
The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
SUMMARY OF THE DRAWINGS
The invention is used with CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views of
Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“μBGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from lower surface 18 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in
In
Portions of flex circuits 30 and 32 are fixed to upper surface 16 of lower CSP 14 by adhesive 34 which is shown as a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive 34 is thermally conductive. Adhesives that include a flux are used to advantage in assembly of module 10. Layer 34 may also be a thermally conductive medium to encourage heat flow between the CSPs of module 10.
Flex circuits 30 and 32 are multi-layer flexible circuit structures that have at least two conductive layers. Preferably, the conductive layers are metal such as alloy 110. The use of plural conductive layers provides advantages as will be seen and the creation of a distributed capacitance across module 10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize. Module 10 of
With continuing reference to
Flex 30 is shown in
As depicted in
Respective ones of CSP contacts 24 of upper CSP 12 and lower CSP 14 are connected at the second conductive layer 58 level in flex circuits 30 and 32 to interconnect appropriate signal and voltage contacts of the two CSPs. Respective CSP contacts 24 of upper CSP 12 and lower CSP 14 that convey ground (VSS) signals are connected at the first conductive layer 54 level in flex circuits 30 and 32 by vias that pass through intermediate layer 56 to connect the levels as will subsequently be described in further detail. Thereby, CSPs 12 and 14 are connected. Consequently, when flex circuits 30 and 32 are in place about lower CSP 14, respective CSP contacts 24 of each of upper and lower CSPs 12 and 14 are in contact with upper and lower flex contacts 42 and 44, respectively. Selected ones of upper flex contacts 42 and lower flex contacts 44 are connected. Consequently, by being in contact with lower flex contacts 44, module contacts 36 are in contact with both upper and lower CSPs 12 and 14.
In a preferred embodiment, module contacts 36 pass through windows 62 opened in second outer layer 52 to contact lower CSP contacts 44. In some embodiments, as will be later shown, module 10 will exhibit a module contact array 38 that has a greater number of contacts than do the constituent CSPs of module 10. In such embodiments, some of module contacts 36 may contact lower flex contacts 44 that do not contact one of the CSP contacts 24 of lower CSP 14 but are connected to CSP contacts 24 of upper CSP 12. This allows module 10 to express a wider datapath than that expressed by the constituent CSPs 12 or 14. A module contact 36 may also be in contact with a lower flex contact 44 to provide a location through which different levels of CSPs in the module may be enabled when no unused CSP contacts are available or convenient for that purpose.
In a preferred embodiment, first conductive layer 54 is employed as a ground plane, while second conductive layer 58 provides the functions of being a signal conduction layer and a voltage conduction layer. Those of skill will note that roles of the first and second conductive layers may be reversed with attendant changes in windowing and use of commensurate interconnections.
As those of skill will recognize, interconnection of respective voltage CSP contacts 24 of upper and lower CSPs 12 and 14 will provide a thermal path between upper and lower CSPs to assist in moderation of thermal gradients through module 10. Such flattening of the thermal gradient curve across module 10 is further encouraged by connection of common ground CSP contacts 24 of upper and lower CSPs 12 and 14 through first conductive layer 54. Those of skill will notice that between first and second conductive layers 54 and 58 there is at least one intermediate layer 56 that, in a preferred embodiment, is a polyimide. Placement of such an intermediate layer between ground-conductive first conductive layer 54 and signal/voltage conductive second conductive layer 58 provides, in the combination, a distributed capacitance that assists in mitigation of ground bounce phenomena to improve high frequency performance of module 10.
In a preferred embodiment,
In a preferred embodiment,
Those of skill will recognize that as flex 30 is partially wrapped about lateral side 20 of lower CSP 14, first conductive layer 54 becomes, on the part of flex 30 disposed above upper surface 16 of lower CSP 14, the lower-most conductive layer of flex 30 from the perspective of upper CSP 12. In the depicted embodiment, those CSP contacts 24 of upper CSP 12 that provide ground (VSS) connections are connected to the first conductive layer 54. First conductive layer 54 lies beneath, however, second conductive layer 58 in that part of flex 30 that is wrapped above lower CSP 14. Consequently, some means must be provided for connection of the upper flex contact 42 to which ground-conveying CSP contacts 24 of upper CSP 12 are connected and first conductive layer 54. Consequently, in the depicted preferred embodiment, those upper flex contacts 42 that are in contact with ground-conveying CSP contacts 24 of upper CSP 12 have vias that route through intermediate layer 56 to reach first conductive layer 54. The sites where those vias meet first conductive layer 54 are identified in
Also shown in
In a wide datapath module 10, the data paths of the constituent upper CSP 12 and lower CSP 14 are combined to provide a module 10 that expresses a module datapath that is twice the width of the datapaths of the constituent CSPs in a two-high module 10. The preferred method of combination is concatenation, but other combinations may be employed to combine the datapaths of CSPs 12 and 14 on the array of module contacts 36 and 36E.
As an example,
In particular, in the embodiment depicted in
Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.
Claims
1. A high-density circuit module comprising:
- a first CSP having a major surface and a first plurality of CSP contacts along the major surface;
- a second CSP having a major surface and a second plurality of CSP contacts along the major surface, the first CSP and the second CSP being disposed in a stacked configuration;
- a flex circuit comprising a first conductive layer having first conductive areas, each electrically connected to a selected one of the first plurality of CSP contacts, and second conductive areas, each electrically connected to a selected one of the second plurality of CSP contacts a second conductive layer having third conductive areas, each electrically connected to a selected one of the first plurality of CSP contacts, and fourth conductive areas, each electrically connected to a selected one of the second plurality of CSP contacts, and an intermediate layer between the first conductive layer and the second conductive layer; and
- module contacts, at least one of which is electrically connected to one of the first conductive areas, and at least one of which is electrically connected to one of the third conductive areas.
2. The high-density circuit module of claim 1 in which at least one of the module contacts is electrically connected to one of the fourth conductive areas.
3. The high-density circuit module of claim 1 in which the first conductive layer comprises a ground plane.
4. The high-density circuit module of claim 1 in which a first selected one of the first plurality of CSP contacts is electrically connected through the first conductive layer to at least one of the second plurality of CSP contacts, and in which a second selected one of the first plurality of CSP contacts is connected through the second conductive layer to at least one of the second plurality of CSP contacts.
5. The high-density circuit module of claim 1 in which the first conductive layer, the intermediate layer, and the second conductive layer are configured to provide distributed capacitance.
6. The high-density circuit module of claim 1 in which the second conductive layer comprises electrical paths each connecting a selected one of the CSP contacts of the first plurality of CSP contacts to a selected one of the CSP contacts of the second plurality of CSP contacts.
7. The high-density circuit module of claim 6 in which selected ones of the plurality of the electrical paths have substantially equal signal lengths.
8. The high-density circuit module of claim 6 in which the second conductive layer further comprises a voltage plane.
9. The high-density circuit module of claim 1 in which thermally conductive material is disposed between the first CSP and the second CSP.
10. The high-density circuit module of claim 9 in which the thermally conductive material is a thermally conductive adhesive.
11. A high-density circuit module comprising:
- a first CSP stacked with a second CSP, the first CSP having an outline perimeter and a major surface with a first plurality of CSP contacts, and the second CSP having a major surface with a second plurality of CSP contacts; and
- a flex circuit having a first conductive layer, a second conductive layer, a first portion having a first plurality of flex contacts connected to selected ones of the first plurality of CSP contacts, a second portion having a second plurality of flex contacts connected to selected ones of the second plurality of CSP contacts, and a third portion having a bend disposed outside the outline perimeter of the first CSP and adjacent to the stack formed by the first CSP and the second CSP.
12. The high-density circuit module of claim 11 further comprising module contacts disposed along the first portion or the second portion of the flex circuit.
13. The high-density circuit module of claim 11 in which the first conductive layer comprises a ground plane.
14. The high-density circuit module of claim 11 in which a first selected one of the first plurality of CSP contacts is electrically connected through the first conductive layer to at least one of the second plurality of CSP contacts, and in which a second selected one of the first plurality of CSP contacts is connected through the second conductive layer to at least one of the second plurality of CSP contacts.
15. The high-density circuit module of claim 11 in which the second conductive layer comprises electrical paths each connecting a selected one of the CSP contacts of the first plurality of CSP contacts to a selected one of the CSP contacts of the second plurality of CSP contacts.
16. The high-density circuit module of claim 15 in which the second conductive layer further comprises a voltage plane and selected ones of the electrical paths comprise traces.
17. The high-density circuit module of claim 15 in which selected ones of the electrical paths have substantially equal signal lengths.
18. The high-density circuit module of claim 17 in which the second conductive layer further comprises a voltage plane and selected ones of the electrical paths comprise traces.
19. The high-density circuit module of claim 11 in which thermally conductive material is disposed between the first CSP and the second CSP.
20. The high-density circuit module of claim 19 in which the thermally conductive material is a thermally conductive adhesive.
21. A high-density circuit module component comprising:
- a CSP having a first major surface, a second major surface, an outline perimeter, and CSP contacts along at least the first major surface or the second major surface;
- a flex circuit having a plurality of conductive layers, a first generally planar portion proximal to at least a portion of the first major surface of the CSP, a second generally planar portion proximal to at least a portion of the second major surface of the CSP, and a bend outside the outline perimeter of the CSP;
- flex contacts disposed along the second generally planar portion of the flex circuit; and
- module contacts disposed along the first generally planar portion of the flex circuit.
22. The high-density circuit module component of claim 21 in which the flex contacts are connectable with CSP contacts of another CSP.
23. The high-density circuit module component of claim 21 in which one of the conductive layers comprises a ground plane.
24. The high-density circuit module component of claim 23 in which one of the flex contacts is connected to the ground plane by a via.
25. The high-density circuit module component of claim 24 in which the via is on-pad.
26. The high-density circuit module component of claim 24 in which the via is off-pad.
27. The high-density circuit module component of claim 21 in which the flex circuit comprises plural primary traces each connecting a selected one of the CSP contacts to a selected one of the flex contacts.
28. The high-density circuit module component of claim 27 in which selected ones of the primary traces have substantially equal signal lengths.
29. The high-density circuit module component of claim 27 in which the flex circuit further comprises at least one secondary trace connecting a selected one of the module contacts only to one or more of the CSP contacts.
30. The high-density circuit module component of claim 27 in which the flex circuit further comprises at least one secondary trace connecting a selected one of the module contacts only to one or more of the flex contacts.
31. The high-density circuit module component of claim 30 in which the flex circuit further comprises at least one tertiary trace connecting a selected one of the module contacts only to one or more of the CSP contacts.
32. A high-density circuit module comprising:
- a stack comprising a first CSP having a major surface along which a first plurality of CSP contacts is disposed and a second CSP having a major surface along which a second plurality of CSP contacts is disposed;
- a flex circuit having a plurality of conductive layers, a first generally planar portion disposed adjacent to at least a portion of the major surface of the first CSP, a second generally planar portion disposed adjacent to at least a portion of the major surface of the second CSP, and a folded portion disposed adjacent to the stack;
- sets of flex contacts, respectively comprising a first plurality of flex contacts, a second plurality of flex contacts, and a third plurality of flex contacts;
- a plurality of module contacts;
- conductive connections between ones of the first plurality of CSP contacts and ones of the first plurality of flex contacts;
- conductive connections between ones of the second plurality of CSP contacts and ones of the second plurality of flex contacts; and
- conductive connections between ones of the plurality of module contacts and ones of the third plurality of flex contacts.
33. The high-density circuit module of claim 32 in which a first of the conductive levels comprises a ground plane.
34. The high-density circuit module of claim 33 in which a second of the conductive levels has plural electrical paths, each between a selected one of the contacts of the first plurality of CSP contacts and a selected one of the contacts of the second plurality of CSP contacts.
35. The high-density circuit module of claim 34 in which the second conductive layer comprises a voltage plane, and the electrical paths comprise traces.
36. The high-density circuit module of claim 34 in which selected ones of the electrical paths have substantially equal signal lengths.
37. The high-density circuit module of claim 36 in which the second conductive layer comprises a voltage plane, and the electrical paths comprise traces.
38. The high-density circuit module of claim 32 in which a first selected one of the first plurality of CSP contacts is electrically connected through a first one of the conductive layers to at least one of the second plurality of CSP contacts, and in which a second selected one of the first plurality of CSP contacts is connected through a second one of the conductive layers to at least one of the second plurality of CSP contacts.
39. The high-density circuit module of claim 32 in which thermally conductive material is disposed between the first CSP and the second CSP.
40. The high-density circuit module of claim 39 in which the thermally conductive material is a thermally conductive adhesive.
Type: Application
Filed: Dec 22, 2005
Publication Date: Jun 22, 2006
Inventors: James Cady (Austin, TX), James Wilder (Austin, TX), David Roper (Austin, TX), James Wehrly (Austin, TX), Julian Dowden (Austin, TX), Jeff Buchle (Austin, TX)
Application Number: 11/317,425
International Classification: H01L 23/12 (20060101);