Non-volatile memory array with simultaneous write and erase feature
A non-volatile transistor memory array, having individual cells, each individual cell having a current injector transistor and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row is erased by charge being driven from a memory transistor. A series of conductive plates are arranged in capacitive relation to the word line, with each plate having a pair of oppositely extending tangs, one allowing programming of a cell in a first row and another allowing erasing of a cell in another row.
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This is a divisional of pending U.S. patent application Ser. No. 10/773,059, filed Feb. 4, 2004 and entitled “NON-VOLATILE MEMORY ARRAY WITH SIMULTANEOUS WRITE AND ERASE FEATURE,” incorporated herein by reference.
TECHNICAL FIELDThe invention relates to non-volatile memory arrays and, in particular, to a non-volatile memory array adapted for a simultaneous write and erase.
BACKGROUND ARTImpact ionization has been known for several years. U.S. Pat. No. 4,432,075 to B. Eitan and U.S. Pat. No. 4,821,236 to Hayashi et al. describe an EEPROM transistor adjacent to a charge generator, creating a substrate current near the EEPROM, creating excess charge or holes, resembling space charge, near subsurface electrodes of the EEPROM. Assume that the holes are generated and accelerated toward one of the electrodes of the EEPROM. Resulting secondary electrons are sufficiently energetic to penetrate gate oxide over the substrate and become injected into a conductive floating gate. For very small EEPROMs, the floating gate becomes charged by band-to-band tunneling, a situation which eliminates the need for a control gate over the floating gate.
U.S. Pat. No. 5,126,967 and U.S. Pat. No. 4,890,259 to R. Sinks describe a memory array made of non-volatile transistors that can store analog waveforms.
The ability of EEPROM transistors to directly record analog waveforms, without A-to-D conversion, gives rise to new applications, such as use in neural networks. This has been pointed out in U.S. Pat. No. 6,125,053 where C. Dioris and C. Mead describe use of EEPROMs storing variable amounts of charge generated by impact ionization to represent an analog value. This is in contrast to a conventional EEPROM where a floating gate either stores charge or does not store charge, thereby indicating a digital value. In the '053 patent, an EEPROM is described that permits simultaneous writing and reading.
An analogous problem is simultaneous programming and erasing operations in an array. An object of the invention was to devise a memory array that has simultaneous programming of one memory region and erasing of another memory region.
SUMMARY OF THE INVENTIONThe above object has been met with semiconductor non-volatile memory array having cells in one row that can be written while cells in another row are erased. The cells feature a non-volatile memory transistor of the type having a floating gate, plus a charge injector formed in an isolated but adjacent isolation area, plus customary row and column address lines. The charge injector creates space charge flowing toward the bottom of the substrate below isolation regions. Because of proximity of the injector to the memory transistor, one or more of the electrodes of the memory transistor is biased to attract charge, e.g. holes. Impacts of the holes upon the charged electrode or electrodes gives rise to secondary particles, specifically electrons, by impact ionization, having sufficient energy for injecting onto the floating gate. Current stimulation in the injector, a fast diode, and electrode bias in the transistor, in a carefully controlled manner leads to placement of precise amounts of charge on the floating gate. A current meter placed at an electrode may or could measure the transferred charge over a particular range, out of several possible ranges, determined by substrate and injector region doping. Different doping levels give rise to different conduction thresholds for memory cells in the transistor and hence different ranges. The different thresholds in a transistor array allow an array to act over an extended range of analog signal trimming, without analog-to-digital conversion.
To achieve simultaneous writing and erasing, a row being currently written is selected by a word line, while the same line erases an adjacent, non-current row. The word line is spaced by dielectric material from a plurality of polysilicon plates, the spacing creating a capacitive relation relative to the word line. The poly plates have tangs that form control gates of transistors. Tangs extending in one direction form EEPROM control gates for writing in one row while tangs extending in another direction form control gates for erasing in another row.
BRIEF DESCRIPTION OF THE DRAWINGS
With reference to
Program lines 11 and 13 are arranged to provide bias to MOS transistor 21 when appropriate bias is established on actuation line 33 by an n-channel MOS transistor 35 connected as a plate capacitor. EEPROM memory transistor 23 has a distributed floating gate formed by the gates of transistors 35, and 21, essentially lead wire forming line 36, while the control gate is a novel capacitively coupled structure partly formed by word line 19.
Word line 19 is shown to be part of a capacitive device 25 in cell 15, as well as capacitive device 125 in a neighboring cell. A feature of the word line and associated capacitive devices is that bias is provided to one cell for writing but in the neighboring cell for erasing in a manner but explained below with reference to
A current meter 39 associated with bit line 37 and contact 32, measures current through memory transistor 23 via device 25 when transistor 23 is read or written to by placing appropriate bias on bit lines and programming lines. The programming lines 11 and 13 are normally floating during other times. The bit lines 17 and 37 are biased to provide an accurate current flow measurement through transistor 23 of a selected cell. Not shown in
A column-wise adjacent cell 115 has the same components as cell 15, namely an MOS transistor 135 connected as a plate capacitor, a current injector formed by a diode 129 and injector transistor 121, an EEPROM memory transistor 123 and a capacitive device 125. A current meter 139 reads the output of memory transistor 123 along bit line 137. Programming lines 11 and 13 bias the current injector for conduction when appropriate bias is established by actuation line 133, with electrons driven to the floating gate of memory transistor 123. The method of charge injection into the oxide and floating gate or from the floating gate into the oxide and substrate can be any of the following mechanisms: photo-emission, Fowler-Nordheim tunneling, hot electron injection at appropriate temperatures (i.e. not lower than 500° C.), or Zener or Avalanche breakdown (i.e. if carriers in substrate acquire energies in excess of the electron or hole barrier height). Other cells in the memory array, such as cells 215 and 315 have similar components as memory cells 15 and 115, respectively.
The current to or from a selected memory transistor could be measured during a programming operation, i.e. channel conductivity present, in order to have an indication of the amount of stored charge on the floating gate structure formed by the three gates of transistors 35, 21, and 23. Part of the channel conductivity for MOS transistor 21 is provided by the injector, in particular, injector diode 29, as seen below. Impact ionization is most frequently measured by monitoring substrate current in the memory transistor. The source and drain of memory transistor 23 are electrically floating at bit line 17 and word line 19 during programming. Current meter 39 has contact via 32 for reading the state of charge.
To enable low voltage impact ionization, both sides of the injector diode junction 29 are heavily doped and the barrier thickness is approximately equal to the depletion width. As an example, this dimension is 100 Å with a doping level on the lightly doped side of the junction exceeding 1017 cm−3.
In the memory cell 15 of
With reference to
Together, transistor 21 and the fast diode form a current injector. As the reverse voltage across the diode is increased, the leakage current remains essentially constant until the breakdown voltage is reached where the current increases dramatically. This breakdown voltage is the Zener voltage. While for the conventional rectifier or diode it is imperative to operate below this voltage, the current injector diode is intended to operate at the Zener voltage.
The following is the correspondence between elements of
In
In
The measured current on current meter 39 is proportional to stored charge on the floating gate of the memory transistors in the same well. Since more than one memory transistor can share the same well, calibration is needed to relate measured current to stored charge. One of the remarkable features of the present invention is illustrated in
Each word line has a capacitive relation with a plurality of poly plates, all spaced apart from the word line by insulative material, such as oxide. A voltage applied to a word line can cause writing to all non-volatile memory transistors in one row and erasing to all non-volatile memory transistors in another row. Each poly plate preferably has two tangs extending in opposite directions, forming poly gates of transistors in adjacent rows.
In
In
In
In
Word line 19 behaves as one plate of a capacitor. The layer of oxide 138 acts a dielectric separator for a second capacitor plate, the poly plate 43. In a memory array, the buried word line and the plurality of poly plates form a new type of semiconductor device in a memory array.
Burying of the word line is optional. The word line could be plated over the poly plates. However, by burying the word line a much more compact memory array is formed. As usual, each word line is controlled independently. Typically, each word line controls a single row or column of a memory array for a write operation and a single row or column for an erase operation. Tangs extending from each poly plate form control gates for transistors as explained above. Because the tangs extend from the poly plates in opposite directions it is possible to control writing in one row where the tangs operate or control injector transistors and to control erasing in another row where the tangs operate or control a memory transistor.
In operation, following are suggested voltages for word lines and bit lines for memory cell programming where the cell is an array having “M’ rows, where “M” is greater than “i”. WLi is the “i”th word line where “i” is an integer and BLi is the “i”th bit line. The n-well is at approximately positive 5 volts and the p-substrate is grounded. The values below are sub-bandgap ionization voltages.
Following are suggested voltages for erasing, assume a Fowler-Nordheim erase mode. The n-well is at approximately negative 15 volts and the p-substrate is grounded.
Following are suggested read voltages. The n-well and the p-substrate are both grounded. The active bit line voltage must be lower than the programming voltage.
The above voltage values are exemplary and intended to indicate relative values. Actual values will differ.
Claims
1. A non-volatile memory array having a plurality of memory cells in rows and columns, each memory cell comprising,
- a non-volatile memory transistor with a source, drain, and channel disposed within a first isolation region in the substrate;
- an injector transistor having a source and drain disposed within a second isolation region in the substrate with a space charge means for accelerating charge carriers to at least one of the source and drain, and
- a word line portion in capacitive plate relation to serve as a control gate for the memory transistor.
2. The apparatus of claim 1 wherein rows of the array have word lines and columns have bit and program lines, all with selectively applied bias voltages, the word lines and poly plates of adjacent rows connected in a manner whereby memory cells in a first row can be selectively written to, simultaneously erasing of memory cells in an adjacent row.
3. The apparatus of claim 1 wherein different rows of the memory array have different doping densities, thereby establishing different threshold voltages in different rows.
4. The apparatus of claim 1 wherein memory transistors of common thresholds may be disposed in a row, with different rows having different thresholds.
5. The apparatus of claim 4 wherein different rows of memory transistors span a range of thresholds.
6. The apparatus of claim 1 wherein each memory cell is associated with an electrically communicating current meter measuring stored charge in the memory cell.
7. The apparatus of claim 1 wherein each memory cell has at least two mutually connected floating gate transistors.
8. The apparatus of claim 1 wherein the memory array comprises a plurality of capacitive plates of polysilicon.
9. The apparatus of claim 1 wherein the capacitive plate has a first region forming said control gate and a second region that forms a control means for an injector transistor in an adjacent row to the memory cell.
10. The apparatus of claim 9 wherein the injector transistor in the adjacent row is in an adjacent column to the memory cell.
11. The apparatus of claim 1 wherein the space charge means is a p-n junction having the source of the injector transistor as a member of the junction.
12. The apparatus of claim 1 wherein the charge injector diode is a p-n junction having the drain of the injector transistor as a member of the junction.
13. A non-volatile memory array comprising,
- a plurality of memory cells in rows and columns, each cell having a non-volatile memory transistor with a source, drain, and channel and an auxiliary transistor means for generating space charge for programming the non-volatile memory transistor; and
- a word line in capacitive relation to a first row of memory cells of the array via a plurality of capacitive plates, each of the plurality of capacitive plates comprising a first region of the word line forming a control gate for a memory transistor.
14. The non-volatile memory array of claim 13 wherein the each of the plurality of capacitive plates further comprises a second region forming a control gate for a programming transistor in a second row of memory cells of the array.
15. The non-volatile memory array of claim 13 wherein the non-volatile memory transistors are disposed within a first isolation region within the substrate and the auxiliary transistors are disposed within a second isolation region within the substrate.
16. The non-volatile memory array of claim 13 wherein the programming transistors are configured to transfer charge carriers to the capacitive plate by means of avalanche injection.
17. The non-volatile memory array of claim 13 wherein the means for generating space charge comprises a charge injector communicating charge to at least one of the source and drain of the auxiliary transistor, the accelerated charge carriers giving rise to energetic charged particles which can be stored in a gate of a non-volatile memory transistor.
18. A non-volatile memory array having a plurality of memory cells in rows and columns comprising:
- a non-volatile memory transistor in each cell with a source, drain, and channel;
- an injector transistor associated with each cell having means for generating space charge for use with an associated non-volatile memory transistor, and
- a plurality of word lines, each word line having a plurality of capacitive plates, each of the plurality of capacitive plates having a first region forming a control gate for a memory transistor in one row and a second region forming a control gate for an injector transistor in another row.
Type: Application
Filed: Apr 19, 2006
Publication Date: Aug 24, 2006
Applicant:
Inventor: Bohumil Lojek (Colorado Springs, CO)
Application Number: 11/407,568
International Classification: G11C 16/04 (20060101);