METHOD OF FORMING A CONTACT STRUCTURE INCLUDING A VERTICAL BARRIER STRUCTURE AND TWO BARRIER LAYERS
This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.
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This application is a Divisional of U.S. application Ser. No. 10/753,041, filed Jan. 7, 2004, which is a Divisional of U.S. application Ser. No. 09/653,640, filed Aug. 31, 2000, now U.S. Pat. No. 6,787,833, both of which are incorporated herein by reference.
FIELDThis invention relates to contact structures, and more particularly to contact structures used in the fabrication of integrated circuits.
BACKGROUNDAn integrated circuit, such as a dynamic random access memory (DRAM) includes passive devices, such as capacitors, and active devices, such as metal-oxide semiconductor field-effect transistors (MOSFETS), fabricated on a single substrate. In fabricating an integrated circuit to perform a particular function, the passive and active devices are coupled together. For example, a capacitor electrode is electrically coupled to a MOSFET drain or source to form a dynamic random access memory (DRAM) cell for storing information.
One method of coupling a capacitor electrode to a MOSFET drain or source includes the operation of directly coupling the capacitor electrode to the drain or source by fabricating the capacitor electrode at the drain or source. Unfortunately, several problems arise when a non-silicon electrode is directly coupled to a MOSFET drain or source. First, the electrode can experience oxidation, which interferes with the electrode conductivity and may cause unpredictable memory cell operation. Electrode oxidation is most likely to occur during capacitor formation processes performed in an O2 atmosphere. Second, atomic migration to and from a substrate, such as silicon substrate, may occur between the substrate in which the MOSFET source and drain are formed and other integrated circuit elements, such as the dielectric layer of a capacitor. Atomic migration alters the electrical properties of the integrated circuit elements and may cause unpredictable memory cell operation.
One solution to these problems is to form a contact structure having a barrier layer located between the electrode and the source or drain for blocking oxygen migration and atomic migration to and from the substrate. Unfortunately, a single barrier layer that effectively blocks both oxygen migration and atomic migration from the substrate may react with the conductive layer fabricated at the source or drain and cause unpredictable circuit operation.
For these and other reasons, there is a need for the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
A contact structure is described that includes one or more layers and other structures for blocking atomic migration in an integrated circuit, which improves the reliability of the circuit.
The present invention provides, in one embodiment, a contact including a polysilicon layer formed on a substrate, one or more barrier layers formed above the polysilicon layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. The polysilicon layer provides a conductive material for coupling to an active or a passive device in an integrated circuit. At least one of the one or more barrier layers restricts the migration of atoms to and from the substrate, and at least one of the one or more barrier layers restricts the migration of oxygen atoms. Restricting the migration of substrate atoms, prevents the electrical properties of the integrated circuit devices from being inadvertently altered during circuit fabrication. Restricting the migration of oxygen atoms, deters oxidation at electrode surfaces, such as capacitor electrode surfaces. Since the barrier layers of the contact are also electrically conductive, the contact is suitable for use in interconnecting integrated circuit devices.
In an alternate embodiment, the present invention provides a method of fabricating a contact. The method includes forming a polysilicon layer and a tungsten nitride layer above a base integrated circuit structure. The polysilicon layer is formed at an electrical connection site of an integrated circuit device. The polysilicon layer and the tungsten nitride layer are etched to a level below the surface of the base integrated circuit structure. The polysilicon layer encircling the contact is etched much deeper, and a silicon nitride layer is formed to encircle the tungsten nitride layer. A ruthenium silicide layer is formed above the tungsten nitride layer as an oxygen barrier. The silicon nitride layer prevents the polysilicon layer from reacting with the ruthenium silicide layer. After polishing and cleaning, the ruthenium silicide layer is ready for coupling to an integrated circuit device.
A structure described herein encircles a second structure or layer when the structure partially or completely surrounds any portion of the second structure or layer. For example, in
Substrate 117 is preferably fabricated from a material, such as a semiconductor, that is suitable for use as a substrate in connection with the fabrication of integrated circuits. Substrate 117 includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures having an exposed surface with which to form the contact structures of the present invention. Substrate 117 refers to semiconductor structures during processing, and may include other layers that have been fabricated thereon. In one embodiment, substrate 117 is fabricated from silicon. Alternatively, substrate 117 is fabricated from germanium, gallium-arsenide, silicon-on-insulator, silicon-on-sapphire, or any other crystalline or amorphous material suitable for use as a substrate in the manufacture of integrated circuits. Substrate 117 is not limited to a particular material, and the material chosen for the fabrication of substrate 117 is not critical to the practice of the present invention.
Referring again to
Contact structures and methods of fabricating contact structures have been described. The contact structures include one or more barrier layers and a barrier structure. One of the barrier layers is capable of blocking the migration of substrate atoms. Another of the barrier layers is capable blocking the migration of oxygen atoms. The barrier structure prevents at least two layers in the contact structure from reacting with each other. The methods of fabricating the contact structure include processes for forming the layers of the contact structure, etching the layers of the contact structure, forming the barrier structure, and polishing the contact structure.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims
1. A memory cell comprising:
- a capacitor;
- a transistor;
- a contact structure coupling the capacitor to the transistor; and
- an insulating structure encircling the contact structure.
2. The memory cell of claim 1, wherein the transistor is a metal-oxide semiconductor field-effect transistor.
3. The memory cell of claim 1, wherein the contact structure includes one or more layers.
4. A memory cell comprising:
- a capacitor;
- a metal-oxide semiconductor field effect transistor (MOSFET);
- a contact structure coupling the capacitor to the MOSFET; and
- an insulating structure encircling the contact structure.
5. The memory cell of claim 4, wherein the MOSFET has a source and the contact structure couples the capacitor to the source.
6. The memory cell of claim 5, wherein the contact structure includes at least two barrier layers.
7. The memory cell of claim 4, wherein the contact structure includes a polysilicon layer, a tungsten nitride layer, and a platinum-iridium layer.
8. The memory cell of claim 7, wherein the insulating structure is fabricated from a tungsten nitride.
9. The memory cell of claim 7, wherein the contact structure separates the platinum-iridium layer from the polysilicon layer.
10. The memory cell of claim 7, wherein the insulating layer is capable of preventing the polysilicon layer from reacting with the contact structure.
11. The memory cell of claim 7, wherein platinum-ruthenium layer is separated from the polysilicon layer by the insulating structure.
12. The memory cell of claim 4, wherein the insulating structure is located between the contact structure and a borophosphosilicate glass layer.
13. A memory cell comprising:
- a capacitor;
- a transistor;
- a contact structure including a polysilicon layer, a tungsten nitride layer, and a ruthenium silicide layer, the contact structure coupling the capacitor to the transistor; and
- an insulating structure encircling the contact structure.
14. The memory cell of claim 13, wherein the transistor is a bipolar transistor.
15. The memory cell of claim 13, wherein the insulating layer is separated from the polysilicon layer by an air gap.
16. The memory cell of claim 13, wherein the transistor is a metal-oxide semiconductor field effect transistor (MOSFET).
17. A system comprising:
- a processor; and
- one or more memory cells coupled to the processor, wherein at least one of the memory cells includes a contact having an insulating structure to prevent a conductive layer from interacting with a barrier layer.
18. The system of claim 17, wherein the processor is a microprocessor.
19. The system of claim 17, wherein at least one of the memory cells is a dynamic random access memory (DRAM) cell.
20. The system of claim 19, wherein the processor is a reduced instruction set (RISC) processor.
21. The system of claim 17, wherein the barrier layer is to prevent migration of oxygen atoms into a substrate.
22. A system comprising:
- a processor; and
- one or more dynamic random access memory (DRAM) cells coupled to the processor, wherein at least one of the DRAM cells includes a contact structure including a barrier structure fabricated from silicon nitride.
23. The system of claim 22, wherein the barrier structure encircles the contact structure.
24. The system of claim 22, wherein the contact structure includes one or more barrier layers.
25. A system comprising:
- a processor; and
- one or more memory cells, wherein at least one of the memory cells includes a contact structure having an insulating structure encircling the contact structure.
26. The system of claim 25, wherein the contact structure includes a polysilicon layer and two barrier layers.
27. The system of claim 25, wherein the contact structure includes a barrier layer capable of blocking migration of silicon atoms and a barrier layer capable of blocking migration of oxygen atoms.
28. A method comprising:
- forming an active device on a substrate;
- forming a passive device on the substrate; and
- forming a contact structure including a barrier structure for coupling the passive device to the active device.
29. The method of claim 28, wherein forming the active device further includes forming the active device below a conductive layer.
30. The method of claim 29 further comprising, forming a first barrier layer above the conductive layer.
31. The method of claim 30 further comprising, forming a second barrier layer above the first barrier layer.
32. The method of claim 28, wherein forming the active device further includes forming the active device as a metal-oxide semiconductor field-effect transistor (MOSFET).
33. A method comprising:
- forming a conductive layer on a base structure having a surface;
- forming a first barrier layer above the conductive layer;
- etching the conductive layer and the first barrier layer to a level below the surface;
- forming a barrier structure that encircles the conductive layer and the first barrier layer;
- forming a second barrier layer above the first barrier layer; and
- polishing the second barrier layer and the surface.
34. The method of claim 33, further comprising:
- forming an active device below the conductive layer.
35. The method of claim 34, further comprising:
- forming a passive device above the second barrier layer.
36. A method comprising:
- forming a polysilicon layer on a base structure having a surface;
- forming a tungsten nitride layer above the conductive layer;
- etching the polysilicon layer and the tungsten nitride layer to a level below the surface;
- forming a silicon nitride structure that encircles the polysilicon layer and the tungsten nitride layer;
- forming a ruthenium silicide layer above the first barrier layer; and
- polishing the ruthenium silicide layer and the surface.
37. The method of claim 36, further comprising:
- forming a MOSFET below the conductive layer.
38. The method of claim 37, further comprising:
- forming a capacitor above the second barrier layer.
39. A method comprising:
- forming a conductive layer on a base structure having a surface;
- forming a first barrier layer above the conductive layer;
- forming a second barrier layer above the first barrier layer;
- etching the first barrier layer and the second barrier layer;
- etching the conductive layer and the first barrier layer to a level below the surface;
- forming an oxide layer above the second barrier layer; and
- removing the oxide layer from above the second barrier layer.
40. The method of claim 39, further comprising:
- forming a transistor below the conductive layer.
41. The method of claim 40, further comprising:
- forming a passive device above the second barrier layer.
42. A method of forming a contact, the method comprising:
- forming a structure having a plug volume above a substrate;
- forming a polysilicon layer in the plug volume;
- forming one or more barrier layers above the polysilicon layer;
- etching an outer perimeter to recess the outer perimeter of the plug volume down to a tungsten nitride layer;
- forming a barrier structure in the outer perimeter;
- etching the barrier structure to leave a sidewall above the tungsten nitride, but still expose the top surface;
- depositing the oxygen barrier layer to fill the rest of the plug; and
- polishing to isolate individual plug features.
43. The method of claim 42 further comprising, forming the polysilicon layer as a conductive layer
44. The method of claim 43 further comprising, forming the barrier structure to encircle the conductive layer.
Type: Application
Filed: May 31, 2006
Publication Date: Oct 5, 2006
Applicant:
Inventor: Fred Fishburn (Boise, ID)
Application Number: 11/421,406
International Classification: H01L 29/94 (20060101);