System and method for a high-speed access architecture for semiconductor memory
A memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is electrically connected to the first device by the first plurality of wires. The memory cell is electrically connected to the second device by a second plurality of wires. The second device is adapted to sense a small swing signal in the first plurality of wires, and to generate a full swing signal on the second set of wires in response to the small swing signal. The memory cell stores the full swing signal.
This application is a continuation of U.S. patent application Ser. No. 10/967,447, filed Oct. 18, 2004, and entitled “System and Method for a High-Speed Access Architecture for Semiconductor Memory,” which application claims the benefit of U.S. Provisional Application No. 60/585,023 filed on Jul. 2, 2004, entitled “System and Method for a High Speed Access Architecture for Semiconductor Memory,” both of which applications are hereby incorporated herein by reference.
TECHNICAL FIELDThe present invention relates generally to a system and method for semiconductor devices and more particularly to a system and method for a high-speed access architecture for semiconductor memory.
BACKGROUNDComplementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. ULSI circuits commonly include memory devices for the storage of data.
Memory devices 100 typically require memory arrays 108 with millions, billions, or more memory cells 112 organized into rows 107 and columns 109. The repeated elements in
A memory controller 102 selectively controls the data bus 114 to read from, and write to the memory cells 112 in the memory array 108. A data bus may be generally considered to include at least two circuits interconnected by one or more wires. The data bus of the prior art 114 in
Therefore, what is needed is a system and method for a high-speed access architecture for semiconductor memory devices, specifically, a system and method for high-speed access architecture of large-scale semiconductor memories.
SUMMARY OF THE INVENTIONThese and other problems are generally solved or circumvented, and technical advantages are generally achieved, by illustrative embodiments of the present invention which provides a high-speed access architecture for semiconductor memory devices. In accordance with one aspect of the present invention, a memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is electrically connected to the first device by the first plurality of wires. The memory cell is electrically connected to the second device by a second plurality of wires. The second device is adapted to sense a small swing signal in the first plurality of wires, and to generate a full swing signal on the second set of wires in response to the small swing signal. The memory cell stores the full swing signal.
In accordance with another aspect of the present invention, a memory access architecture is provided, which includes a first device, a second device, a memory cell, and a third device. The first device is electrically connected to a first pair of wires. The first device is adapted to generate a small swing signal in the first pair of wires. The second device is electrically connected to the first device by the first pair of wires. The second device is adapted to sense a first small swing signal in the first pair of wires and in response generate a full swing signal in a second set of wires. The memory cell is electrically connected to the second device by a second pair of wires. The memory cell stores the full swing signal. The memory cell is adapted to generate a second small swing signal in the second pair of wires. The third device is electrically connected to the memory cell by the second pair of wires, wherein upon sensing the second small swing signal in the second pair of wires. The third device generates a third small swing signal in the third pair of wires. The third device is electrically connected to a fourth device by a third pair of wires.
In accordance with still another aspect of the present invention, a memory access architecture is provided, which includes a first device, a second device, a memory cell, and a third device. The first device is electrically connected to a first pair of wires. The first device is adapted to generate a small swing signal in the first pair of wires. The second device is electrically connected to the first device by the first pair of wires. The second device is adapted to sense a first small swing signal in the first pair of wires and in response generate a full swing signal in a second set of wires. The memory cell is electrically connected to the second device by a second pair of wires. The memory cell stores the full swing signal. The memory cell is adapted to generate a second small swing signal in the second pair of wires. The third device is electrically connected to the memory cell by the second pair of wires, wherein upon sensing the second small swing signal in the second pair of wires. The third device generates a third small swing signal in the third pair of wires. The third device is electrically connected to the fourth device and to the first device by the first pair of wires.
In accordance with yet another aspect of the present invention, a method of memory device operation is provided. This method includes the following steps described in this paragraph, the order of which may vary. A first small swing signal is a generated onto a first data bus. Upon detecting the first small swing signal, a full swing signal are generated on a second data bus. The second data bus is electrically connected to a group of memory cells.
In accordance with another aspect of the present invention, a method of memory device operation is provided. This method includes the following steps described in this paragraph, the order of which may vary. Writing to a first memory cell. The writing to the first memory cell includes: generating a first small swing signal onto a first pair of wires, wherein the first small swing signal is generated by a write driver electrically connected to a first transmission buffer (also called write-buffer, since it deals with signals for writing) by the first pair of wires; sensing the first small swing signal on the first pair of wires and generating a first full swing signal on a second pair of wires in response to the first small swing signal, wherein the second pair of wires electrically connect the first transmission buffer to the first memory cell; and storing the first full swing signal in the first memory cell. Reading from a second memory cell. The reading from the second memory cell includes: generating a second small swing signal onto a third pair of wires, the second small swing signal being generated by the second memory cell, the second memory cell being electrically connected to a second transmission buffer (also called read-buffer, since it deals with signals for reading) by the third pair of wires; and sensing the second small swing signal on the third pair of wires and generating a third small swing signal on a fourth pair of wires in response to the second small swing signal, wherein the fourth pair of wires electrically connect a read amplifier to the second transmission buffer. The writing to the first memory cell and the reading from the second memory cell are performed independently with respect to time.
BRIEF DESCRIPTION OF THE DRAWINGSFor a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the presently illustrative embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.
The present invention will be described with respect to illustrative embodiments in a specific context, namely a high-speed access architecture for semiconductor memory devices. The first illustrative embodiment of the present invention has a basic data bus architecture, as shown in
The global data bus 200 in
A local data bus 215 of the illustrative embodiment is shown in
The transmission buffer 220 also has a read transfer enable (RTE) wire connected to the read buffer 222 and a write transfer enable (WTE) wire connected to the write buffer 224. The RTE and WTE carry the transfer enable signal. When the write transfer enable (WTE) signal is transferred, write buffer 224 is enabled and in an operating state, thereby responding selectively to electrical signals on their inputs Win1 and Win2. When the read transfer enable (RTE) signal is transferred, the read buffer 222 is in an operating state, thereby responding selectively to electrical signals generated on the inputs Rin1 and Rin2.
When the write buffer 224 is in an operating state, it will generate a full swing signal in the output terminals Wout1 and Wout2 in response to a small swing signal in the input terminals Win1 and Win2. When the read buffer 222 is in an operating state, it will generate a small swing signal in the output terminals Rout1 and Rout2 in response to a small swing signal in the input terminals Rin1 and Rin2.
An example of a small swing signal 226 and a full swing signal 228 are shown in
It should be noted that small swing signals are distinct from voltage droops or other undesired voltage events that may appear in the local and global data bus transmission mediums. Undesired voltage events may bring the voltage in a wire down to a percentage of VDD at random times and for comparatively short durations. In contrast, small swing signal properties are well known in the art, such as fall time, rise time and a stabilized voltage level. It should be further noted that although memory devices of the present invention may be manufactured with a desired small swing voltage level, it is well known that the actual voltage level of the finished product may not be the desired voltage level. Rather, the small swing voltage level of the finished product will typically be within a range of the desired level, such as within +/−5%, +/−10%, and +/−30%, for example. As is well known, the small swing voltage level of the finished product will depend on various factors, including temperature variations, manufacturing process variations, and voltage source variations, for example.
The first illustrative embodiment of the present invention, shown in
The global data bus 233 may also be described as having two independent buses. The global data bus 233 includes a unidirectional write bus 234, shown separately in
The transmission buffers 220 of the first illustrative embodiment are adapted so that the unidirectional read bus 236 and the unidirectional write bus 234 of the global data bus 233 may operate independently. The unidirectional read bus 236 may transmit data from the transmission buffers 220 to the read amplifier 211 within the same period of time that data is transmitted from the write driver 216 to the transmission buffers 220 on the unidirectional write bus 234. Conventionally, a separated data read bus and data write bus allow the memory device to perform read and write access to a memory cell in a different local data bus at the same time. However, if the data bus is now shared for both read and write access, like the memory device 232, only one type of access is allowed to transmit the data on the bus in the same period of time. Thus the memory device 232 now performs a collision logic function (not shown) that prevents a read operation and a write operation from being performed to memory cells 212 in the same local data bus 215 within the same period of time.
With reference again to
The read operation and the write operation of the data bus 230 of the first illustrative embodiment are discussed below with reference to
In the first illustrative embodiment, the write operation 238 occurs within the same time frame as the read operation 240. The write driver 216 generates a small swing signal on the unidirectional write bus transmission wires GWB and GWBB. The transfer enable signal in the wire TE2 is enabled. Upon sensing that the transfer enable signal is enabled, and upon sensing the small swing signal in the global write transmission wires GWBB and GWB, the write buffer 224b in the transmission buffer 220b generates a full swing signal on the local data bus wires LDBB2 and LDB2. Forcing the wordline wire WL2 to VDD causes the memory cell 212b to store the full swing signal on the wires LDBB2 and LDB2.
The second illustrative embodiment shown in
Voltage waveforms showing the read 244 and write 246 operations in the second illustrative embodiment are shown in
At time t2-11, the read operation 244 on the data bus 248 of the second illustrative embodiment is performed. The controller 202 causes the wordline WL3 connected to the memory cell 212c to be activated by switching the voltage on the wordline wire from zero volts to VDD. In response, the memory cell 212c generates a small swing signal on the local data bus wires LDB and LDBB that is similar to the values stored in the memory cell 212c. The transfer enable signal is enabled on the wire TE3, thereby causing the read buffer 222c in the transmission buffer 220c to enter an operational state. The read buffer 222c senses the small swing signal on the local data bus wires LDB and LDBB and generates a small swing signal on the global data bus transmission wires GDB and GDBB. At time t3-11 the read amplifier 211 senses the small swing signal on the global data bus wires GDB and GDBB and distributes the signal for further processing.
In illustrative embodiments of the present invention, the write buffer in each transmission buffer provides increased memory speed by reducing the time required to transmit signals from the write driver to each memory cell.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. As example, it will be readily understood by those skilled in the art that high-speed access architecture for semiconductor memory may be varied while remaining within the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A method for operating memory devices, the method comprising:
- generating a first small swing signal;
- transmitting the first small swing signal through a first plurality of wires;
- amplifying the first small swing signal to generate a full swing signal; and
- storing a state corresponding to the full swing signal into a memory cell.
2. The method of claim 1 further comprising:
- reading from the memory cell to generate a second small swing signal;
- generating a third small swing signal from the second small swing signal; and
- transmitting the third small swing signal through a second plurality of wires.
3. The method of claim 2, wherein the first and the second plurality of wires are a same set of bi-directional wires, and wherein the steps of transmitting the first small swing signal and transmitting the third small swing signal are performed during different time frames.
4. The method of claim 2 further comprising enabling wordlines of the memory cell to reach a voltage equal to a magnitude of the full swing signal during the step of reading from the memory cell.
5. The method of claim 1 further comprising enabling enabling wordlines of the memory cell to reach a voltage equal to a magnitude of the full swing signal during the step of storing the state into the memory cell.
6. The method of claim 1, wherein the first small swing signal has a magnitude less than about 50 percent a magnitude of the full swing signal.
7. The method of claim 6, wherein the magnitude of the first small swing signal is equal to about 25 percent of the magnitude of the full swing signal.
8. The method of claim 1, wherein the first plurality of wires comprises two wires or four wires.
9. A method for operating memory devices, the method comprising:
- reading from a memory cell to generate a first small swing signal;
- generating a second small swing signal from the first small swing signal; and
- transmitting the second small swing signal through a plurality of wires.
10. The method of claim 9 further comprising amplifying the second small swing signal.
11. The method of claim 9 further comprising enabling wordlines of the memory cell to reach a voltage equal to a magnitude of the full swing signal during the step of reading the memory cell.
12. The method of claim 9, wherein the first and the second small swing signals have magnitudes less than about 50 percent a magnitude of the full swing signal.
13. The method of claim 9, wherein the magnitudes of the first and the second small swing signals are each equal to about 25 percent of the magnitude of the full swing signal.
14. The method of claim 9, wherein the plurality of wires comprises bi-directional wires, and wherein the plurality of wires is also used for transmitting signals for write operations of the memory cell.
15. The method of claim 9, wherein the plurality of wires comprises two wires or four wires.
16. A method for operating a memory device, the method comprising:
- providing a memory cell;
- connecting transmission buffers to the memory cell, wherein the transmission buffers are configured to interface with the memory cell; and
- transmitting small swing signals between the transmission buffers and devices, wherein the small swing signals have magnitudes substantially smaller than a magnitude of a voltage supply of the memory device.
17. The method of claim 16, wherein the transmission buffers comprise a write buffer for write operations and a read buffer for read operations.
18. The method of claim 16, wherein the devices comprise a write driver for generating the small swing signals during write operations and a read amplifier for amplifying small swing signals during read operations.
19. The method of claim 16, wherein, during write operations, the small swing signals are amplified to full swing signals before writing into the memory cell.
20. The method of claim 16, wherein the small swing signals each have amplitudes of less than about 50 percent of the voltage supply.
Type: Application
Filed: Jun 14, 2006
Publication Date: Oct 19, 2006
Inventor: Chien-Hua Huang (Hsinchu City)
Application Number: 11/452,807
International Classification: G11C 7/10 (20060101);