Patents by Inventor Chien-Hua Huang

Chien-Hua Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240192576
    Abstract: A camera module suited for assembled in a casing is provided. The camera module includes a camera and a switch cover. The camera is disposed in the casing and aligned with a camera hole of the casing. The switch cover is slidably disposed in the casing, wherein the switch cover includes a sliding member and a shielding member secured to the sliding member, and a thickness of the shielding member is less than a thickness of the sliding member. The camera hole is seated on a sliding path of the shielding member. The shielding member is suited for blocking between the camera and the camera hole or moving out between the camera and the camera hole. An electronic device is also provided.
    Type: Application
    Filed: August 13, 2023
    Publication date: June 13, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Chin Huang, Cheng-Mao Chang, Li-Hua Hu, Pao-Min Huang, Chien-Yuan Chen
  • Publication number: 20240192732
    Abstract: In example implementations, an apparatus is provided. The apparatus includes a plurality of ports, a magnetic field sensor, a magnetic port cover, and a processor. A subset of ports of the plurality of ports are deactivated and covered with the magnetic port cover. The magnetic field sensor is coupled to each one of the plurality of ports. The processor is communicatively coupled to the magnetic field sensor. The processor is to detect removal of the magnetic port cover from a deactivated port of the subset of ports that are deactivated via a signal from the magnetic field sensor of the deactivated port and generate notification in response to the magnetic port cover being removed to notify a user to replace the magnetic port cover on the deactivated port.
    Type: Application
    Filed: June 29, 2021
    Publication date: June 13, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po-Ying Chih, Chien-Wei Chen, Chi-Wei Ting, Chun-Hua Huang, Chien Fa Huang
  • Patent number: 12010924
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Pin Chiu, Chang-Lin Yang, Chien-Hua Huang, Chen-Chiu Huang, Chih-Fan Huang, Dian-Hau Chen
  • Publication number: 20240162159
    Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang WANG, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
  • Publication number: 20240128378
    Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chu, Chien-Hua Huang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240099149
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20240090336
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20240079758
    Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Wen-Hgin Chuang, Lin-Hsu Chiang, Chang-Hua Wu, Han-Wei Wang, Chun-Jung Hu
  • Patent number: 11923315
    Abstract: Semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. Dies of the pair of dies are disposed side by side. Each die includes a contact pad. Redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. Redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. Innermost dielectric layer is closer to the pair of dies. Redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. Outermost dielectric layer is furthest from the pair of dies. Conductive plate is electrically connected to the contact pads of the pair of dies. Conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. Vertical projection of the conductive plate falls on spans of the dies of the pair of dies.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
  • Patent number: 11856854
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Patent number: 11849644
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • Publication number: 20230298900
    Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Chien-Hua Huang, Tzu-Hui Wei, Cherng-Shiaw Tsai
  • Publication number: 20230263069
    Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Chang-Lin Yang, Sheng-Yuan Chang, Chung-Te Lin, Han-Ting Lin, Chien-Hua Huang
  • Patent number: 11664237
    Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hua Huang, Tzu-Hui Wei, Cherng-Shiaw Tsai
  • Publication number: 20230157032
    Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.
    Type: Application
    Filed: March 9, 2022
    Publication date: May 18, 2023
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20230138005
    Abstract: An exemplary method includes forming a multilayer interlevel dielectric (ILD) layer having a metal-containing dielectric layer (e.g., an aluminum oxide layer) between a first dielectric layer and a second dielectric layer and forming a bottom electrode via in the multilayer ILD layer. The method further includes forming a bottom electrode layer over the bottom electrode via, magnetic tunnel junction (MTJ) layers over the bottom electrode layer, and a top electrode layer over the MTJ layers. The bottom electrode layer, the MTJ layers, and the top electrode layer are etched to form a bottom electrode, an MTJ element, and a top electrode, respectively, of a magnetoresistive random-access memory (MRAM). The etching, such as an ion beam etch, forms a recess in the multilayer ILD layer that extends to the metal-containing dielectric layer of the multilayer ILD layer. In some embodiments, the etching extends the recess into and/or through the metal-containing dielectric layer.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 4, 2023
    Inventors: Hsiang-Lun Kao, Chen-Chiu Huang, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20220406992
    Abstract: Some embodiments relate to a memory device. The memory device includes a substrate comprising an inter-metal dielectric layer having a metal line, a dielectric layer over the substrate, a bottom electrode via through the dielectric layer and in contact with the metal line, a bottom electrode over the bottom electrode via, a magnetic tunneling junction (MTJ) element over the bottom electrode, and a top electrode over the MTJ element. A center portion of the bottom electrode directly above the bottom electrode via is thicker than an edge portion of the bottom electrode.
    Type: Application
    Filed: April 21, 2022
    Publication date: December 22, 2022
    Inventors: Yi-Cheng Chu, Chung-Te Lin, Kai-Wen Cheng, Han-Ting Tsai, Jung-Tsan Tsai, Pao-Yi Tai, Chien-Hua Huang
  • Publication number: 20220384521
    Abstract: Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Wei-De HO, Lan-Hsin CHIANG, Chien-Hua HUANG, Chung-Te LIN, Yung-Yu WANG, Sheng-Yuan CHANG, Kai-Chieh LIANG
  • Patent number: 11495465
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Publication number: 20220336733
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.
    Type: Application
    Filed: September 1, 2021
    Publication date: October 20, 2022
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin