Patents by Inventor Chien-Hua Huang

Chien-Hua Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250106187
    Abstract: A method, a network device, and a non-transitory computer-readable storage medium are described in relation to a low latency, low loss, and scalable throughput (LI4S)-triggered prioritized connection service. The LI4S-triggered prioritized connection service may enable an evolved packet data gateway (ePDG) to provision prioritized and non-prioritized tunnels with end devices via untrusted wireless local area networks. The prioritized tunnel may support LI4S or another quality of service in which the ePDG may provide prioritized data forwarding. The end device may transmit a request that includes priority data.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Chien-Yuan Huang, Suzann Hua, Tony Ferreira
  • Patent number: 12262642
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • Patent number: 12245515
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20250052963
    Abstract: A method for forming an optical device structure is provided. The method includes disposing a first end portion of an optical fiber into a fiber array unit structure. The first end portion penetrates through the fiber array unit structure. The method includes bonding the first end portion of the optical fiber to a co-packaged optical device. The method includes bonding a fiber shield structure to the fiber array unit structure and the co-packaged optical device after the first end portion is bonded to the co-packaged optical device. The fiber shield structure surrounds the optical fiber.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Inventors: Chien-Yuan HUANG, Shih-Chang KU, Chen-Hua YU, Chuei-Tang WANG
  • Patent number: 12211700
    Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hua Huang, Tzu-Hui Wei, Cherng-Shiaw Tsai
  • Publication number: 20240412975
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 12, 2024
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Publication number: 20240389465
    Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes a substrate, a dielectric layer over the substrate, memory cells disposed in the dielectric layer, and a metal line above the memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. A bottom surface of the metal line has a continuously flat portion that directly interfaces each of the top electrodes of the memory cells.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20240349616
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20240347608
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconducting material layer, a gate electrode under the semiconducting material layer, a pair of contact terminals over the semiconducting material layer, and a hydrogen-blocking dielectric layer on the semiconducting material layer. The pair of contact terminals penetrates through the hydrogen-blocking dielectric layer to be in contact with the semiconducting material layer at a contact surface, and the contact surface is substantially coplanar with and levelled with an interface between the hydrogen-blocking dielectric layer and the semiconducting material layer.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chu, Chien-Hua Huang, Katherine H. CHIANG, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12048250
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • Publication number: 20240212139
    Abstract: An automatic calculation method of gray-to-white-matter ratio for head computed tomography of patients with cardiac arrest is disclosed and includes an image registration step, a K-means segmentation step, a segmentation refinement step and a GWR calculation step. Measure the gray-white-matter ratio through brain computed tomography early after cardiac arrest to automatically identify the corpus callosum, caudate nucleus, putamen, and posterior branch of the internal brain cyst. It is a 3D three-dimensional structure rather than a manually selected flat circular area to evaluate the effectiveness of predicting neurological prognosis at discharge.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 27, 2024
    Applicants: NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN UNIVERSITY HOSPITAL
    Inventors: Chien-Hua HUANG, Chien-Yu CHI, Liang-Wei WANG, Yu-Jen SU, Weichung WANG, Hsin-Han TSAI, Cheyu HSU
  • Patent number: 12010924
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Pin Chiu, Chang-Lin Yang, Chien-Hua Huang, Chen-Chiu Huang, Chih-Fan Huang, Dian-Hau Chen
  • Publication number: 20240128378
    Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.
    Type: Application
    Filed: January 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chu, Chien-Hua Huang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240099149
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Publication number: 20240090336
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Patent number: 11856854
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • Patent number: 11849644
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • Publication number: 20230298900
    Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventors: Chien-Hua Huang, Tzu-Hui Wei, Cherng-Shiaw Tsai
  • Publication number: 20230263069
    Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Chang-Lin Yang, Sheng-Yuan Chang, Chung-Te Lin, Han-Ting Lin, Chien-Hua Huang
  • Patent number: 11664237
    Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hua Huang, Tzu-Hui Wei, Cherng-Shiaw Tsai