Abstract: A method for image alignment is provided. The method for image alignment includes the following stages. A first image with a first property from a first sensor is received. A second image with a second property from a second sensor is received. The first property is similar to the second property. The first feature correspondence between the first image and the second image is calculated. A third image with a third property from the first sensor and a fourth image with a fourth property from the second image sensor are received. The third property is different from the fourth property. Image alignment is performed on the third image and the fourth image based on the first feature correspondence between the first image and the second image.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: A multi-axis servo control system includes a plurality of motors and a plurality of drive control apparatuses. The drive control apparatuses are connected to each other through an external field bus. Each drive control apparatus includes a control unit and a plurality of drive units. The drive units are connected to the control unit in series by a plurality of local buses to form a series-connected communication loop of sequentially transmitting data. Each drive unit controls at least one of the motors. The control unit receives multi-axis position commands through the external field bus, and the drive units correspondingly receive multi-axis commands through the local buses so as to control the motors in a decentralization manner.

Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes a substrate, a dielectric layer over the substrate, memory cells disposed in the dielectric layer, and a metal line above the memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. A bottom surface of the metal line has a continuously flat portion that directly interfaces each of the top electrodes of the memory cells.

Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

Abstract: A method includes: positioning a wafer in a first probe chamber of a first probe apparatus by a robot arm, the first probe apparatus being adjacent a transfer rail, the robot arm, in operation, moving along the transfer rail; testing the wafer by the first probe apparatus; following the testing, transferring the wafer to an environmental buffer attached to the first probe chamber; cooling the wafer in the environmental buffer; and following the cooling, transferring the wafer from the environmental buffer to a second probe chamber of a second probe apparatus by the robot arm, the second probe apparatus being adjacent the transfer rail and offset from the first probe apparatus.

Abstract: An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconducting material layer, a gate electrode under the semiconducting material layer, a pair of contact terminals over the semiconducting material layer, and a hydrogen-blocking dielectric layer on the semiconducting material layer. The pair of contact terminals penetrates through the hydrogen-blocking dielectric layer to be in contact with the semiconducting material layer at a contact surface, and the contact surface is substantially coplanar with and levelled with an interface between the hydrogen-blocking dielectric layer and the semiconducting material layer.

Abstract: A fan management system includes a fan and a server. The fan includes a driving circuit, and the driving circuit is configured for driving the fan. The fan operates in an operation mode. The server is connected to the fan and is configured for controlling the operation of the fan. The driving circuit outputs a digital label signal when the fan operates abnormally, and the server obtains a production history, an operation information and a warning message of the fan through the digital label signal. The server adjusts the operation mode of the fan according to the warning message simultaneously.

Abstract: A method for high dynamic range imaging is provided. The method includes the following stages. A first image from a first sensor capable of sensing a first spectrum is received. A second image from a second sensor capable of sensing a second spectrum is received. The second spectrum has a higher wavelength range as compared to the first spectrum. A first image feature from the first image and a second image feature from the second image are retrieved. The first and second images are fused by referencing the first image feature and the second image feature to generate a final image.

Abstract: A touch sensor includes a substrate, sensing channels, and a protective layer. The sensing channels are disposed at intervals on a surface of the substrate, and any one of the sensing channels includes an electrode portion and a silver trace portion electrically connected to the electrode portion. The protective layer is disposed on the substrate and covers and encapsulates the sensing channels. After the touch sensor is subjected to a salt spray test with sodium chloride solution of a mass percentage concentration of 5% at a rate of 1 mL/H to 2 mL/H under an ambient temperature of 35° C. for 48 hours, a resistance change rate of any one of the sensing channels is less than or equal to 10%, and a resistance distribution difference between the sensing channels is less than or equal to 10%.

Abstract: An image calibration method is applied to an image calibration device includes an image receiver and an operation processor. The image calibration method of providing a motion deblur function includes driving a first camera to capture a first image having a first exposure time, driving a second camera disposed adjacent to the first camera to capture a second image having a second exposure time different from and at least partly overlapped with the first exposure time, and fusing a first feature of the first image and a second feature of the second image to generate a fusion image.

Abstract: A method for laminating a film to a wafer and apparatus for performing the lamination process are disclosed. The method includes providing the wafer and the film in a process chamber where the wafer and the film are separated from each other, achieving a vacuum state and a process temperature in the process chamber, and laminating the film to contact a surface of the wafer.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.

Abstract: An automatic calculation method of gray-to-white-matter ratio for head computed tomography of patients with cardiac arrest is disclosed and includes an image registration step, a K-means segmentation step, a segmentation refinement step and a GWR calculation step. Measure the gray-white-matter ratio through brain computed tomography early after cardiac arrest to automatically identify the corpus callosum, caudate nucleus, putamen, and posterior branch of the internal brain cyst. It is a 3D three-dimensional structure rather than a manually selected flat circular area to evaluate the effectiveness of predicting neurological prognosis at discharge.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.