WAFER GETTERING USING RELAXED SILICON GERMANIUM EPITAXIAL PROXIMITY LAYERS
One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region. In various embodiments, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed to epitaxially form the relaxed silicon germanium gettering region. In various embodiments, forming the relaxed silicon germanium gettering region includes implanting germanium ions into a silicon substrate with a desired dose and energy to form a silicon region containing germanium ions and heat treating the substrate to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. Other aspects are provided herein.
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This application is a continuation under 37 C.F.R. 1.53(b) of U.S. application Ser. No. 10/443,339 filed May 21, 2003, which application is incorporated herein by reference.
This application is related to the following commonly assigned U.S. patent applications which are herein incorporated by reference in their entirety: “Strained Si/SiGe Structures by Ion Implantation,” U.S. application Ser. No. 10/431,134 filed on May 7, 2003, now U.S. Pat. No. 6,987,037 (Attorney Docket 1303.094US1); and “Gettering of Silicon On Insulator Using Relaxed Silicon Germanium Epitaxial Proximity Layers,” U.S. application Ser. No. 10/443,337 filed on May 21, 2003 (Attorney Docket 1303.103US1).
TECHNICAL FIELDThis disclosure relates generally to semiconductors, and more particularly, to wafer gettering by relaxed silicon germanium layers in close proximity to device layers.
BACKGROUNDUnwanted crystalline defects and impurities can be introduced during crystal growth or subsequent wafer fabrication processes. These defects and impurities can degrade device characteristics and overall yield. Gettering has been described as a process for moving contaminants and/or defects in a semiconductor into its bulk and away from its top surface to create a denuded zone cleared from contaminants and/or defects. Preferably, devices are built in the denuded zone.
Historically, extrinsic backside gettering was used to getter silicon wafers. Various extrinsic backside gettering processes involve damaging the backside of the wafer mechanically or by implanting argon, germanium, hydrogen or other implants, or providing a gettering layer on the backside of the wafer using a phophorosilicate glass or oxide backside layer, a polysilicon backside layer, and a silicon germanium (SiGe) backside epitaxial layer. Subsequently, “intrinsic” gettering was developed, which employed oxygen precipitation and “bulk microdefects” precipitated into the bulk of the wafer after the surface was “denuded” of oxygen. The precipitation process, the gettering effects, and the electrical characterization of defects and gettering silicon wafers have been investigated. Recently, intrinsic gettering modifications have been developed, including neutron irradiation, high boron doping, nitrogen doping, and the use of magnetic fields during crystal growth.
These gettering processes depend on the diffusion of unwanted impurities over significant distances to the gettering sites. However, modem low temperature processes have small thermal budgets, and do not afford an opportunity for significant diffusion of dopants and/or unwanted impurities. Thus, it is desirable to reduce the distance between the gettering sites and the device area. It has been previously proposed to implant various impurities in proximity to the device areas, to co-implant oxygen and silicon to form a gettering layer in close proximity to the device area, to implant helium to form cavities close to the device areas which getter impurities, and to getter material in trench isolation areas in close proximity to the device areas.
BRIEF DESCRIPTION OF THE DRAWINGS
The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. The various embodiments are not necessarily mutually exclusive as aspects of one embodiment can be combined with aspects of another embodiment. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The terms “horizontal” and “vertical”, as well as prepositions such as “on”, “over” and “under” are used in relation to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
This application discloses the use of relaxed silicon germanium as gettering sites in close proximity to device areas. Various embodiments use ultra high vacuum chemical vapor deposition (UHV CVD) epitaxial techniques to place a relaxed silicon germanium layer immediately under the device areas. Various embodiments use ion implantation and solid phase epitaxial (SPE) regrowth to form a relaxed silicon germanium layer immediately below a silicon layer within a silicon substrate. The ion implantation and SPE regrowth method is less costly and complex than the UHV CVD process. The relaxed silicon germanium generates defects by relaxation of the silicon germanium lattice strain and/or the injection of silicon interstitials when the germanium is substitutionally incorporated into the lattice. These defects serve to getter unwanted impurities.
One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region.
One aspect of this disclosure relates to a method for forming a semiconductor structure. A relaxed silicon germanium gettering region is formed to be proximate to a device region. Subsequent semiconductor fabrication processes are performed, including processes to fabricate a semiconductor device in the device region. Defects generated by the relaxed silicon germanium gettering region getters unwanted impurities from the device region during the subsequent semiconductor fabrication processes.
One aspect of this disclosure relates to a method for forming a transistor. A proximity gettering region is formed to be proximate to a crystalline silicon region in a wafer. The proximity gettering region includes relaxed silicon germanium. A gate dielectric is formed over the crystalline silicon region, and a gate is formed over the gate dielectric. A first diffusion region and a second diffusion region are formed in the strained crystalline silicon region. The first and second diffusion regions are separated by a channel region formed in the crystalline silicon region between the gate and the proximity gettering region. In various embodiments, the crystalline silicon region is sufficiently thin and is positioned on the silicon germanium such that a lattice mismatch strains the crystalline silicon region. In various embodiments, the crystalline silicon region is sufficiently thick such that the crystalline silicon region is not strained. Aspects of this disclosure incorporate such transistors into memory cells and/or control circuitry of memory devices.
A relaxed silicon germanium region or layer is formed to be proximate to a device area such that defects generated by the relaxed silicon germanium getter impurities from the device area even with the small thermal budgets associated with modem low temperature processes. In various embodiments, a UHV CVD process is used to epitaxially form a relaxed silicon germanium layer and a silicon layer on the relaxed silicon germanium layer such that the silicon germanium layer forms a proximity gettering site. In various embodiments, germanium ions are implanted into a silicon substrate, and an SPE process is performed to regrow a crystalline silicon layer over a resulting silicon germanium layer in the substrate. The defects generated by relaxation of the silicon germanium lattice strain and/or the injection of silicon interstitials when the germanium is substitutionally incorporated into the lattice serves to getter unwanted impurities.
As represented in
During an ion implantation process, the ions can channel along the crystal directions of the substrate, such that the ions do not encounter nuclei and are slowed down mainly by electronic stopping. Channeling can be difficult to control, and can cause the ions to penetrate several times deeper than intended. In various embodiments, to avoid channeling during the germanium ion implant, the silicon substrate is amorphized using a silicon ion implant to prepare the substrate for the germanium ion implant. In various embodiments, the dose of this silicon ion implant is approximately 1015/cm2 and the energy of this silicon ion implant is greater than 170 KeV. Preparing the substrate using the silicon ion implant to amorphize the substrate results in better depth control during the germanium ion implant process.
The structure 300 is heat treated, or annealed, such that the amorphized layers are regrown by a solid phase epitaxy (SPE) process. In various embodiments, the SPE process involves heating the structures at temperatures within a range of approximately 550° C. to 700° C. for a time within a range from approximately one hour to approximately two hours. The resulting structure 300 is illustrated in
In various embodiments, the crystalline silicon layer is approximately 20 nm thick. However, the present invention is not limited to a particular thickness. The thickness of the crystalline silicon layer is controlled by the energy of the implant. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to control the germanium implant to achieve a desired thickness of the crystalline silicon layer 303B.
The devices are formed in the silicon layer on the silicon germanium gettering layer. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that thicker silicon wafers on the relaxed silicon germanium gettering layer are not strained, and thinner silicon wafers on the relaxed silicon germanium gettering layer are strained. For example, ultra thin silicon layers having a thickness of approximately 2000 Å or less are strained by the lattice mismatch with the relaxed silicon germanium gettering layer. In various embodiments, the silicon layer has a thickness of approximately 1000 Å or less. In various embodiments, the silicon layer has a thickness within a range of approximately 300 Å to approximately 1000 Å.
One area of interest for improving the speed and performance of semiconductor devices includes strained silicon technology, which has been shown to enhance carrier mobility in both n-channel and p-channel devices, and is being considered to improve the electron mobility and drift velocity in n-channel MOSFETs in CMOS technology.
Thin layers of strained silicon are being considered for CMOS n-channel devices. Thinner layers of silicon are more tolerant of strain. One technique for producing strained silicon involves epitaxially growing the silicon and silicon germanium layers using an ultra-high vacuum chemical vapor deposition (UHV CVD) process, a costly and complex process, to form silicon layers on relaxed silicon germanium layers. A large mismatch in the cell structure causes a pseudo-morphic layer of silicon on relaxed silicon germanium to be under biaxial tensile strain. The biaxial strain modifies the band structure and enhances carrier transport in the silicon layer. The strain on the silicon layer depends of the lattice constant difference between silicon and silicon germanium. The lattice constant of silicon germanium is between the lattice constant of silicon (5.43095 Å) and the lattice constant of germanium (5.64613 Å), and depends on the percentage of germanium in the silicon germanium layer.
Upon reading and comprehending this disclosure, one of ordinary skill in the art will appreciate the benefits of strained silicon. The strained silicon layer improves the electron mobility in the n-channel transistors in CMOS technology. A pseudo-morphic layer of silicon on relaxed silicon germanium is under biaxial tensile strain, which modifies the band structure and enhances carrier transport. In an electron inversion layer, the subband splitting is large in strained silicon because of the strain-induced band splitting in addition to that provided by quantum confinement. The ground level splitting in a MOS inversion layer at 1 MV/cm transverse field is about 120 and 250 meV for unstrained and strained silicon, respectively. The increase in energy splitting reduces inter-valley scattering and enhances NMOSFET mobility, as demonstrated at low (<0.6 MV/cm) and higher (approximately 1 MV/cm) vertical fields. The scaled gm is also improved due to the reduced density of states and enhanced non-equilibrium transport. The germanium content can be graded in steps to form a fully relaxed silicon germanium buffer layer before a thin strained silicon channel layer is grown. X-ray diffraction analysis is used to quantify the germanium content and strain relaxation in the silicon germanium layer. The strain state of the silicon channel layer can be confirmed by Raman spectroscopy.
The lattice mismatch of the silicon surface layer with the underlying silicon germanium layer 302B causes the silicon layer 303B to be strained. In various embodiments, N-channel CMOS devices are fabricated in this strained silicon layer 303B using conventional techniques, which are not described here for the sake of brevity.
One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the concentration (X) of germanium in the silicon is controlled by the dose and energy of the germanium ion implant process. Additionally, one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the concentration (X) of germanium in the silicon can be graded by controlling the dose and energy of two or more germanium ion implant process. A benefit of grading germanium concentration involves forming a silicon germanium layer on a silicon substrate to have a relaxed silicon germanium surface upon which the crystalline silicon layer is regrown.
The silicon germanium layer 702 in the structure illustrated in
In various embodiments, the silicon layer 703 is sufficiently thick such that it is not strained by a lattice mismatch between the silicon germanium 702 and the silicon layer 703. In various embodiments, the silicon layer 703 is sufficiently thin to be strained by a lattice mismatch between the silicon germanium 702 and the silicon layer 703. In various embodiments, the thin silicon layer is ultra thin. In various embodiments, the thin silicon layer has a thickness of approximately 2000 Å or less. In various embodiments, the thin silicon layer has a thickness of approximately 1000 Å or less. In various embodiments, the thin silicon layer has a thickness in a range of approximately 300 Å to approximately 1000 Å.
The memory array 1670 includes a number of memory cells 1678. The memory cells in the array are arranged in rows and columns. In various embodiments, word lines 1680 connect the memory cells in the rows, and bit lines 1682 connect the memory cells in the columns. The read/write control circuitry 1672 includes word line select circuitry 1674, which functions to select a desired row. The read/write control circuitry 1672 further includes bit line select circuitry 1676, which functions to select a desired column.
The illustration of the system 1784 is intended to provide a general understanding of one application for the structure and circuitry, and is not intended to serve as a complete description of all the elements and features of an electronic system using proximity gettering regions according to the various embodiments of the present invention. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
Applications containing a gettering region as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems.
CONCLUSIONVarious embodiments disclosed herein provide methods to getter silicon wafers using a relaxed silicon germanium epitaxial layer immediately under the device areas. In various embodiments, the relaxed silicon germanium epitaxial layer are formed by implantation and solid phase epitaxial regrowth. In various embodiments, the relaxed silicon germanium layers are formed by UHV CVD epitaxial techniques. The relaxation of the silicon germanium lattice strain and/or the injection of silicon interstitials when the germanium is substitutionally incorporated into the lattice to generate defects. These defects serve to getter unwanted impurities from the device areas.
This disclosure includes several processes, circuit diagrams, and structures. The present invention is not limited to a particular process order or logical arrangement. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations or variations. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing the above description. The scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims
1. A method, comprising:
- defining a device region in a silicon wafer;
- generating desired defects in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
- forming a device in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
2. The method of claim 1, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region.
3. The method of claim 1, wherein generating desired defects includes implanting germanium ions into the silicon wafer and heat treating to form a crystalline silicon layer over a silicon germanium layer.
4. The method of claim 1, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer.
5. The method of claim 1, wherein forming the device includes forming the device in a strained crystalline silicon layer having a thickness within a range of approximately 300 Å to 1000 Å.
6. A method, comprising:
- defining a device region in a silicon wafer;
- generating desired defects, by relaxation of the silicon germanium lattice strain or injection of silicon interstitials, in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
- forming a device in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
7. The method of claim 6, wherein generating desired defects includes generating desired defects by relaxation of the silicon germanium lattice strain and injection of silicon interstitials when the device is formed.
8. The method of claim 6, wherein forming the device includes forming the device in a strained crystalline silicon layer having a thickness less than approximately 2000 Å.
9. The method of claim 6, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region.
10. The method of claim 6, wherein generating desired defects includes implanting germanium ions into the silicon wafer using a first implant of a first desired dose and energy and a second implant of a second desired dose and energy, and heat treating to form a crystalline silicon layer over a silicon germanium layer.
11. The method of claim 6, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer using a bond cut process.
12. A method, comprising:
- defining a device region in a silicon wafer;
- generating desired defects in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
- forming a device on the gettering site in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
13. The method of claim 12, wherein forming the device includes forming the device in a strained crystalline silicon layer having a thickness less than approximately 2000 Å.
14. The method of claim 12, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region using an ultra high vacuum chemical vapor deposition (UHV CVD) process).
15. The method of claim 12, wherein generating desired defects includes implanting germanium ions into the silicon wafer and heating treating with a temperature within a range from approximately 550° C. to approximately 700° C. to form a crystalline silicon layer over a silicon germanium layer.
16. The method of claim 12, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer using a bond cut process.
17. A method, comprising:
- defining a device region in a silicon wafer;
- generating desired defects in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
- forming a device in a strained silicon layer in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
18. The method of claim 17, wherein the strained silicon layer has a thickness less than approximately 1000 Å.
19. The method of claim 17, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region.
20. The method of claim 17, wherein generating desired defects includes implanting germanium ions into the silicon wafer and heat treating to form a crystalline silicon layer over a silicon germanium layer.
21. The method of claim 17, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer.
Type: Application
Filed: Jul 27, 2006
Publication Date: Nov 16, 2006
Applicant:
Inventor: Leonard Forbes (Corvallis, OR)
Application Number: 11/460,398
International Classification: H01L 21/322 (20060101);