HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICES AND METHOD OF MAKING THE SAME

Abstract

A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This is a divisional application of U.S. patent application Ser. No. 10/908,784, filed May 26, 2005 by Chien-Ming Lin, Ming-Tsung Tung and Chin-Hung Liu.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the fabrication of semiconductor integrated circuits and, more particularly, to an improved process for fabricating high-voltage devices. According to the present invention, the salicide process is integrated with the high-voltage process, thereby reducing the resistance of high-voltage metal-oxide-semiconductor transistor devices.

2. Description of the Prior Art

Integrated circuits (ICs) containing both high-voltage and low-voltage devices such as high/low voltage MOS transistor devices are known in the art. For example, the low-voltage device may be used in the control circuits as the high-voltage device may be used in electrically programmable read only memory (EPROM) or the driving circuits of the liquid crystal display devices.

It is also known that self-aligned suicide (also referred to as “salicide”) process is typically utilized to form metal silicide layer such as cobalt silicide or titanium silicide on the gates, source or drain regions in order to reduce sheet resistances. However, the salicide process is merely performed on the low-voltage devices. Considering hot carrier effects, the conventional high-voltage process cannot integrate with the salicide process. As a result, the sheet resistance of the high-voltage devices is high.

In light of the above, there is a need to provide an improved method for reducing the sheet resistance of the high-voltage devices.

SUMMARY OF THE INVENTION

It is the primary object of the present invention to provide an improved high-voltage process for fabricating high-voltage metal-oxide-semiconductor (MOS) devices, thereby reducing the sheet resistance thereof.

According to the claimed invention, a method for fabricating metal-oxide-semiconductor devices is provided. The method includes the steps of:

(1) providing a semiconductor substrate;

(2) forming a gate dielectric layer having a thickness of t₁ on the semiconductor substrate;

(3) depositing a polysilicon layer on the gate dielectric layer;

(4) forming a resist mask on the polysilicon layer;

(5) etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode;

(6) etching a thickness of the gate dielectric layer not covered by the gate electrode;

(7) stripping the resist mask;

(8) forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer laterally protruding an offset “d” from bottom of the gate electrode;

(9) etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the semiconductor substrate and forming a salicide block lug portions with a thickness t₂ on two opposite sides of the gate electrode with the offset “d” from sidewalls of the gate electrode, wherein t₂<t₁;

(10) depositing a metal layer over the semiconductor substrate; and

(11) making the metal layer react with the semiconductor substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 to FIG. 9 are schematic cross-sectional diagrams showing major intermediate stages in the process of fabricating high- and low-voltage MOS transistor devices in accordance with one preferred embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 1 to FIG. 9. FIG. 1 to FIG. 9 are schematic cross-sectional diagrams showing major intermediate stages in the process of fabricating high- and low-voltage MOS transistor devices in accordance with one preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 comprises a low-voltage device area 102 and a high-voltage device area 104. Within the low-voltage device area 102, low-voltage devices such as low-voltage (5V, 3.3V or lower) MOS transistors are fabricated. Within the high-voltage device area 104, high-voltage devices such as high-voltage (18V or even higher) MOS transistors are fabricated. Initially, isolation structures 12 such as shallow trench isolation (STI) and active areas are defined on the semiconductor substrate 10 both in the low-voltage device area 102 and high-voltage device area 104.

As shown in FIG. 2, a low-voltage gate dielectric 22 and a high-voltage gate dielectric 24 are formed on the surface of the semiconductor substrate 10 within the low-voltage device area 102 and high-voltage device area 104, respectively. Techniques of forming gate dielectrics with two different thicknesses are known in the art, and are not discussed further. According to the preferred embodiment, the low-voltage gate dielectric 22 has a thickness that is less than 200 angstroms, preferably less than or equal to 100 angstroms, while the high-voltage gate dielectric 24 has a thickness that is thicker than 400 angstroms, preferably thicker than 600 angstroms.

As shown in FIG. 3, a polysilicon layer 30 is deposited on the low-voltage gate dielectric 22 and on the high-voltage gate dielectric 24. A photoresist mask 42 and photoresist mask 44 are defined on the polysilicon layer 30, wherein the photoresist mask 42 defines the gate pattern of a low-voltage MOS transistor device within the low-voltage device area 102, while the photoresist mask 44 defines the gate pattern of a high-voltage MOS transistor device within the high-voltage device area 104.

Subsequently, as shown in FIG. 4, using the photoresist masks 42 and 44 as an etching hard mask, a plasma dry etching is carried out to etched away the polysilicon layer 30 that is not covered by the photoresist masks 42 and 44, thereby forming a gate electrode 32 of the low-voltage MOS transistor device and gate electrode 34 of the high-voltage MOS transistor device. The low-voltage dielectric 22 outside the gate electrode 32 is etched away to expose the semiconductor substrate 10. The aforesaid plasma dry etching is not terminated until a predetermined thickness of the thicker high-voltage dielectric 24 is removed. At this phase, the remaining high-voltage dielectric 24 still covers the high-voltage device area 104.

As shown in FIG. 5, a layer of photoresist (not explicitly shown) is coated over the semiconductor substrate 10, and is then exposed and developed using conventional lithography to form photoresist mask 52 and photoresist mask 54. The photoresist mask 52 covers the entire low-voltage device area 102, while the photoresist mask 54 merely masks the gate electrode 34 and a portions of the remaining high-voltage dielectric 24 laterally protruding an offset “d” from the bottom of the gate electrode 34. The offset “d” is substantially equal to the distance between the gate electrode 34 and the source/drain salicide formed in the subsequent processes.

As shown in FIG. 6, using the photoresist mask 52 and photoresist mask 54 as a hard mask, a plasma dry etching is carried out to etch away the remaining high-voltage dielectric 24 that is not covered by the photoresist mask 54. Thereafter, the photoresist mask 52 and photoresist mask 54 are stripped off. The remaining high-voltage dielectric 24 that is not directly under the gate electrode 34 is hereinafter referred to as lug portions 24a that are formed on two opposite sides of the gate electrode 34 with an offset “d” from the gate sidewalls. According to the preferred embodiment, the lug portions 24a have a thickness of about 100˜600 angstroms, and the offset “d” is in a range of about 20˜500 angstroms.

As shown in FIG. 7, a spacer dielectric layer 60 such as silicon nitride is deposited over the semiconductor substrate 10. Next, as shown in FIG. 8, an isotropic dry etching is carried out to etch the spacer dielectric layer 60, thereby forming spacers 62 and 64 on sidewalls of respective gate electrodes 32 and 34. Conventional ion implantation process is then performed to form source/drain regions 72 within the low-voltage device area 102 and source/drain regions 74 within the low-voltage device area 104. After the implantation of source/drain regions, a typical salicide process is carried out. A metal layer 80 such as cobalt or titanium is deposited over the semiconductor substrate 10. The metal layer 80 covers both the low-voltage device area 102 and high-voltage device area 104. It is one feature of the present invention that the lug portions 24a function as a salicide block that keeps the metal layer 80 from contacting the substrate within the offset area directly under the lug portions 24a.

Finally, as shown in FIG. 9, a thermal process is performed. The source/drain regions 72 and 74 that are in contact with the metal layer 80 react with the overlying metal layer 80 to form metal salicide layers 82a and 84a. Simultaneously, metal salicide layers 82b and 84b are formed on the exposed gate electrodes 32 and 34.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A metal-oxide-semiconductor device, comprising:

a semiconductor substrate;

a gate dielectric layer with a thickness t1 formed on the semiconductor substrate;

a gate electrode formed on the gate dielectric layer;

a salicide block lug portions with a thickness t2 being contiguous with the gate dielectric layer, wherein the salicide block lug portions are disposed on two opposite sides of the gate electrode with an offset distance “d” from sidewalls of the gate electrode, wherein t2<t1;

a source/drain region disposed adjacent to the salicide block lug portions; and

a salicide layer formed on the source/drain region that is kept the offset distance “d” away from the gate electrode.

2. The metal-oxide-semiconductor device according to claim 1 wherein the thickness t1>400 angstroms.

3. The metal-oxide-semiconductor device according to claim 1 wherein the thickness t2>100 angstroms.

4. The metal-oxide-semiconductor device according to claim 1 wherein the offset distance “d” is in a range of 20˜500 angstroms.

5. The metal-oxide-semiconductor device according to claim 1 wherein the metal-oxide-semiconductor device is a high-voltage (18V or higher voltage) metal-oxide-semiconductor transistor device.