PACKAGED INTEGRATED CIRCUITS AND METHODS OF PRODUCING THEREOF
A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
The present invention relates to integrated packaging, packaged integrated circuits and methods of producing packaged integrated circuits.
REFERENCE TO CO-PENDING APPLICATIONSApplicants hereby claim priority of Israel Patent Application No. 140,482, filed Dec. 21, 2001, entitled “Packaged Integrated Circuits and Methods of Producing Thereof”, and U.S. patent application Ser. No. 09/758,906 filed Jan. 11, 2001, entitled “Packaged Integrated Circuits and Methods of Producing Thereof”.
BACKGROUND OF THE INVENTIONVarious types of packaged integrated circuits are known in the prior art. The following patents and published patent applications of the present inventor and the references cited therein are believed to represent the state of the art: U.S. Pat. Nos. 4,551,629; 4,764,846; 4,794,092; 4,862,249; 4,984,358; 5,104,820; 5,126,286; 5,266,833; 5,546,654; 5,567,657; 5,612,570; 5,657,206; 5,661,087; 5,675,180; 5,703,400; 5,837,566; 5,849,623; 5,857,858; 5,859,475; 5,869,353; 5,888,884; 5,891,761; 5,900,674; 5,938,45; 5,985,695; 6,002,163; 6,046,410; 6,080,596; 6,092,280; 6,098,278; 6,124,637; 6,134,118. EP 490739 A1; JP 63-166710 WO 85/02283; WO 89/04113; WO 95/19645
The disclosures in the following publications:
“Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technology” by R. J. Wojnarowski, R. A. Filliion, B. Gorowitz and R. Sala of General Electric Company, Corporate Research & Development, P.O. Box 8, Schenectady, N.Y. 12301, USA, International Conference on Wafer Scale Integration, 1993.
“M-DENSUS”, Dense-Pac Microsystems, Inc., Semiconductor International, December 1997, p. 50;
“Introduction to Cubic Memory, Inc.” Cubic Memory Incorporated, 27 Janis Way, Scotts Valley, Calif. 95066, USA;
“A Highly Integrated Memory Subsystem for the Smaller Wireless Devices” Intel(r) Stacked-CSP, Intel Corporation, January 2000;
“Product Construction Analysis (Stack CSP)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
“Four Semiconductor Manufacturers Agree to Unified Specifications for Stacked Chip Scale Packages”, Mitsubishi Semiconductors, Mitsubishi Electronics America, Inc., 1050 East Arques Avenue, Sunnyvale, Calif. 94086, USA;
“Assembly & Packaging, John Baliga, Technology News, Semiconductor International, December 1999;
“<6 mils Wafer Thickness Solution (DBG Technology)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
“Memory Modules Increase Density”, DensePac Micro Systems, Garden Grove, Calif., USA, Electronics Packaging and Production, p. 24, Nov. 1994;
“First Three-Chip Staked CSP Developed”, Semiconductor International, January 2000, p. 22;
“High-Density Packaging: The Next Interconnect Challenge”, Semiconductor International, February 2000, pp. 91-100;
“3-D IC Packaging”, Semiconductor International, p. 20, May 1998;
“High Density Pixel Detector Module Using Flip Chip and Thin Film Technology” J. Wolf, P. Gerlach, E. Beyne, M. Topper, L. Dietrich, K. H. Becks, N. Wermes, O. Ehrmann and H. Reichl, International System Packaging Symposium, January 1999, San Diego;
“Copper Wafer Bonding”, A. Fan, A. Rahman and R. Rief, Electrochemical and Solid State Letters, 2(10), pp. 534-536, 1999;
“Front-End 3-D Packaging”, J. Baliga, Semiconductor International, December 1999, p 52, are also believed to represent the state of the art.
SUMMARY OF THE INVENTIONThe present invention seeks to provide improved packaged integrated circuits and methods for producing same.
There is thus provided in accordance with a preferred embodiment of the present invention a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
Further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is partially transparent to infra-red radiation.
There is also provided in accordance with another preferred embodiment of the present invention a packaged integrated circuit assembly including a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and at least one additional electrical circuit element mounted onto and supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
Still further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
There is further provided in accordance with a preferred embodiment of the present invention a method for producing packaged integrated circuits. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
Further in accordance with a preferred embodiment of the present invention the plurality of individual chip packages are chip scale packages.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
There is also provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages and mounting onto the at second planar surface of at least one of the plurality of individual chip packages, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
There is further provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, mounting onto the at second planar surface of the wafer scale packaging, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
Reference is now made to
In contrast with prior art devices, such as those described in applicant's published PCT application WO 95/19645, the packaged integrated circuit shown in
As seen in
There are also provided third and fourth edge surfaces 30 and 32, each of which intersects the plane of silicon substrate 24 and extends from a location slightly beyond that plane to planar surface 18. There are also provided fifth and sixth edge surfaces 40 and 42, neither of which intersects the plane of silicon substrate 24. Each of edge surfaces 40 and 42 intersects a respective one of surfaces 30 and 32 and extends therefrom to planar surface 14. There are additionally provided seventh and eighth edge surfaces 50 and 52, neither of which intersects the plane of silicon substrate 24. Each of edge surfaces 50 and 52 intersects a respective one of surfaces 20 and 22 and extends therefrom to planar surface 18.
It is seen that contacts 12 extend along respective edge surfaces 20 and 22 and onto planar surface 14 and are in electrical contact with edges of pads 60 extending from silicon substrate 24 in the plane thereof It is also seen that contacts 16 extend along respective edge surfaces 30 and 32 and onto planar surface 18 and are in electrical contact with edges of pads 62 extending from silicon substrate 24 in the plane thereof.
Reference is now made to
Reference is now made to
In accordance with a preferred embodiment of the present invention, and as illustrated in
The cover plate 126 may be opaque or transparent or may be colored or tinted in order to operate as a spectral filter. Alternatively, a dichroic or colored spectral filter may be formed on at least one surface of the cover plate 126.
It is appreciated that certain steps in the conventional fabrication of silicon wafer 120 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating.
The complete silicon wafer 120 may be formed with an integral color filter array by conventional lithography techniques at any suitable location therein. Prior to the bonding step of
Following the bonding step described hereinabove, the silicon wafer 120 is preferably ground down to a decreased thickness, typically 100 microns, as shown in
Following the reduction in thickness of the wafer, which is optional, the wafer is etched, using a photolithography process, along its back surface along predetermined dice lines which separate the individual dies. Etched channels 130 are thus produced, which extend entirely through the thickness of the silicon substrate, typically 100 microns thick. The etched wafer is shown in
The aforementioned etching typically takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the silicon down to the field oxide layer, as shown in
The result of the silicon etching is a plurality of separated dies 140, each of which includes silicon of thickness of about 100 microns.
As seen in
The sandwich of the etched wafer 120 and the first and second insulating packaging layers 126 and 142 is then partially cut along lines 150, lying along the interstices between adjacent dies 140 to define notches along the outlines of a plurality of pre-packaged integrated circuits. It is noted that lines 150 are selected such that the edges of the dies along the notches are distanced from the outer extent of the silicon 140 by at least a distance d, as shown in
It is noted that partial cutting of the sandwich of
It is a particular feature of the present invention that notches are formed in the sandwich of
Reference is now made to
It is noted that metal contacts are formed onto the dies in electrical contact with surfaces 62 of pads 172 without first separating the dies into individual chips.
Reference is now made to
It is noted that metal contacts are formed onto the dies in electrical contact with surfaces 60 of pads 272 without first separating the dies into individual chips.
Reference is now made to
The bonded wafer 121 (
The wafer 121 is then etched at its non-active surface, preferably by photolithography, such as by using conventional spin-coated photoresist, which is commercially available from Hoechst, under the brand designation AZ 4562.
The photoresist is preferably mask exposed by a suitable UV exposure system 385, such as a Karl Suss Model KSMA6, through a lithography mask 386 to define etched channels 130 (
The photoresist is then developed in a development bath (not shown), baked and then etched in a silicon etch solution 388 located in a temperature controlled bath 390. Commercially available equipment for this purpose include a Chemkleen bath and an WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A.. A suitable conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro-Image Technology Ltd. of England. The wafer is conventionally rinsed after etching. The resulting etched wafer is shown in
Alternatively, the foregoing wet chemical etching step may be replaced by dry plasma etching.
The etched wafer is bonded on the non-active side to another protective layer. 142 by bonding apparatus 392, which may be essentially the same as apparatus 382, to produce a doubly bonded wafer sandwich 393 as shown in
Notching apparatus 394 initially partially cuts the bonded wafer sandwich 393 of
Notching apparatus 394 thereafter partially cuts the bonded wafer sandwich 393 of
The notched wafer 393 is then subjected to anti-corrosion treatment in a bath 396, containing a chromating solution 398, such as described in any of the following U.S. Pat. Nos. 2,507,956; 2,851,385 and 2,796,370, the disclosure of which is hereby incorporated by reference.
Conductive layer deposition apparatus 400, which operates by vacuum deposition techniques, such as a Model 903M sputtering machine manufactured by Material Research Corporation of the U.S.A., is employed to produce a conductive layer initially on surfaces 30, 32 and 18 of each die of the wafer as shown in
Configuration of contact strips 12 and 16 as shown in
The photoresist is preferably light configured by a UV exposure system 404, which may be identical to system 385, using masks 405 and 406 to define suitable etching patterns. The photoresist is then developed in a development bath 407, and then etched in a metal etch solution 408 located in an etching bath 410, thus providing a conductor configuration such as that shown in
The exposed conductive strips 12 and 16 shown in
The wafer is then diced into individual pre-packaged integrated circuit devices. Preferably the dicing blade 414 is a diamond resinoid blade of thickness 4-12 mils. The resulting dies appear as illustrated generally in
It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove as well as variations and modifications which would occur to persons skilled in the art upon reading the specification and which are not in the prior art.
Claims
1. A packaged integrated circuit comprising:
- an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
- a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane; and
- a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface.
2. A packaged integrated circuit according to claim 1 and wherein said package is a chip-scale package.
3. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
4. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
5. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
6. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
7. A packaged integrated circuit assembly comprising:
- a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and a plurality of electrical contacts, each connected to said electrical circuitry at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and
- at least one additional electrical circuit element mounted onto and supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.
8. A packaged integrated circuit assembly according to claim 7 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
9. A packaged integrated circuit according to claim 7 and wherein said package is a chip-scale package.
10. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
11. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
12. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
13. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
14. A method for producing packaged integrated circuits comprising:
- producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
- providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
- forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and
- separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.
15. A method for producing packaged integrated circuits according to claim 14 and wherein said plurality of individual chip packages are chip scale packages.
16. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
17. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
18. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
19. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
20. A method for producing packaged integrated circuit assemblies, the method comprising:
- producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
- providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
- forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;
- separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages; and
- mounting onto said at second planar surface of at least one of said plurality of individual chip packages, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.
21. A method of forming a packaged integrated circuit assembly according to claim 20 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
22. A method for producing packaged integrated circuits according to claim 20 and wherein said plurality of individual chip packages are chip scale packages.
23. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
24. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
25. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
26. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
27. A method for producing packaged integrated circuit assemblies, the method comprising:
- producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
- providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
- forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;
- mounting onto said at second planar surface of said wafer scale packaging, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong; and
- separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.
28. A method of forming a packaged integrated circuit assembly according to claim 27 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
29. A method for producing packaged integrated circuits according to claim 27 and wherein said plurality of individual chip packages are chip scale packages.
30. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
31. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
32. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
33. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
Type: Application
Filed: Dec 19, 2001
Publication Date: Jan 18, 2007
Patent Grant number: 7408249
Inventor: Avner Badihi (Yehuda)
Application Number: 10/451,564
International Classification: H01L 21/44 (20060101); H01L 23/02 (20060101);