Contact etching utilizing partially recessed hard mask
A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.
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The present invention relates to a semiconductor process and in particular to fabrication of a semiconductor device using a partially recessed hard mask.
The increasing demand for highly integrated and high-performance semiconductor devices has fueled the need for advances in integrated circuit manufacturing technology. To produce an integrated circuit with high integration density, semiconductor device and interconnect sizes must be reduced. Lithography and etching form trenches and contact holes in the dielectric layer prior to formation of the interconnects. Thereafter, the trenches and contact holes are filled with a metal layer, followed by polishing to complete the fabrication. This is a typical damascene process in semiconductor manufacturing technology. In a common etching technique used to form openings, such as trenches or contact holes, in a target layer on a substrate, a photoresist pattern is formed on the target layer serving as an etch mask. Since the thickness of the photoresist pattern can dictate the etching rate, the photoresist pattern must be thick if the contact holes are to be very small.
A photoresist layer having a thickness of 3000 Å or more, however, is not sensitive to the light used for lithography. That is, it is difficult to form a contact hole with a small critical dimension using a photoresist layer as an etch mask. Accordingly, the fabrication of a contact hole with small critical dimension using a polysilicon layer as an etch mask has been widely employed.
During the fabrication of the semiconductor device, the alignment mark 101 on the alignment region 20 may fail due to light strongly reflected from the thicker polysilicon hard mask 114. That is, it is difficult to define the contact holes 113a, 113b, and 113c during lithography. In order to solve this problem, the polysilicon hard mask 114 over the alignment mark 101 must be removed prior to definition of the contact holes 113a, 113b, and 113c. As a result, a deeper and wider opening is formed by removing the ILD layer 112 over the alignment mark 101 during definition of the contact holes 113a, 113b, and 113c. As the subsequent metal layer 118 is filled for the fabrication of contact plugs, the deeper and wider opening cannot be completely filled with the metal layer 118. The metal layer 118, however, is conformably formed on the inner surface of the opening. A dishing effect thus occurs during planarization by chemical mechanical polishing (CMP). As a result, the metal layer 118 adjacent to the alignment mark 118 is disconnected, as depicted by the arrows 119 shown in
An embodiment of the invention provides a method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region comprising an opening therein serving as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon pattern layer is formed overlying the dielectric layer serving as the hard mask, in which the polysilicon pattern layer comprises a recessed region over the opening and a plurality of holes therein on the device region to expose the underlying dielectric layer. The exposed dielectric layer is etched using the polysilicon pattern layer as an etch mask, to form the plurality of contact holes in the dielectric layer on the device region.
The polysilicon pattern layer has a thickness of about 700 to 1000 Å and the recessed region a depth of about 300 to 500 Å. Moreover, the contact hole may comprise a bit line contact hole, a gate contact hole, or a substrate contact hole.
An embodiment of the invention also provides a semiconductor device fabricated using a partially recessed hard mask. The device comprises a substrate, a dielectric layer, a polysilicon pattern layer, a barrier layer, and a metal layer. The substrate has a device region and an alignment region comprising an opening therein serving as an alignment mark. The dielectric layer overlies the substrate and fills the opening, with the dielectric layer on the device region comprising a plurality of contact holes therein. The polysilicon pattern layer is disposed on the dielectric layer serving as the hard mask, with that over the opening on the alignment region having a recessed region and that on the device region having a plurality of holes therein to expose the contact holes formed in the underlying dielectric layer. The barrier layer is conformably disposed on the polysilicon pattern layer and the inner surfaces of the contact holes and the recessed region. The metal layer is disposed on the barrier layer and fills the contact holes and the recessed region.
The polysilicon pattern layer has a thickness of about 700 to 1000 Å and the recessed region a depth of about 300 to 500 Å. Moreover, the contact hole may comprise a bit line contact hole, a gate contact hole, or a substrate contact hole.
BRIEF DESCRIPTION OF THE DRAWINGSEmbodiments of the invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the invention.
First, as shown in
As shown in
Next, a polysilicon layer 214 is deposited overlying the ILD layer 212 serving as a hard mask for subsequent etching. The polysilicon layer 214 may be formed by conventional deposition, such as CVD. Moreover, the polysilicon layer 214 has a thickness of about 700 to 1000 Å. Next, a photoresist pattern layer 216 is formed on the polysilicon layer 214, which has an opening 217 therein to expose the polysilicon layer 214 over the opening 201 on the alignment region 40.
Next, in
As mentioned above, if the polysilicon hard mask is too thick, the alignment mark for subsequent lithography may fail due to light strongly reflected from the hard mask. Conversely, if the polysilicon hard mask is not thick enough, the subsequent etching may suffer. However, in this embodiment, the thickness of the polysilicon hard mask 214a over the alignment mark 201 is reduced due to the formation of the recessed region 219. Accordingly, the strongly reflected light is prevented during subsequent lithography for the definition of contact holes.
Next, in
Finally, in
According to an embodiment of the invention, the thickness of the polysilicon pattern layer 214a over the alignment mark 201 may be reduced, eliminating strongly reflected light from the hard mask. Moreover, since the step height of the metal layer 224 on the alignment region 40 is reduced by the partially recessed hard mask 214a, disconnection of the metal layer 224 adjacent to the alignment mark 201 may be prevented after planarization.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art) . Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.
Claims
1. A method for forming contact holes using a partially recessed hard mask, comprising:
- providing a substrate with a device region and an alignment region comprising an opening therein serving as an alignment mark;
- forming a dielectric layer overlying the substrate and filling the opening;
- forming a polysilicon pattern layer overlying the dielectric layer, acting as the hard mask, wherein the polysilicon pattern layer comprises a recessed region over the opening and a plurality of holes therein on the device region, exposing the underlying dielectric layer; and etching the exposed dielectric layer using the polysilicon pattern layer as an etch mask, forming a plurality of contact holes in the dielectric layer on the device region.
2. The method as claimed in claim 1, wherein formation of the polysilicon pattern layer comprises:
- forming a polysilicon layer overlying the dielectric layer;
- partially etching the polysilicon layer over the opening on the alignment region using a first photoresist pattern layer as a hard mask, forming the recessed region;
- removing the first photoresist pattern layer;
- etching the polysilicon layer on the device region using a second photoresist pattern layer as a hard mask, forming a plurality of holes therein; and
- removing the second photoresist pattern layer.
3. The method as claimed in claim 1, wherein the dielectric layer comprises borophosphosilicate glass or tetraethyl orthosilicate oxide.
4. The method as claimed in claim 1, wherein the polysilicon pattern layer has a thickness of about 700 to 1000 Å.
5. The method as claimed in claim 4, wherein the recessed region has a depth of about 300 to 500 Å.
6. The method as claimed in claim 1, wherein the contact hole comprises a bit line contact hole, a gate contact hole, or a substrate contact hole.
7. The method as claimed in claim 1, further comprising:
- conformably forming a barrier layer overlying the polysilicon pattern layer and the inner surfaces of the contact holes on the device region and the recessed region on the alignment region;
- forming a metal layer on the barrier layer and filling the contact holes and the recessed region; and
- planarizing the metal layer.
8. The method as claimed in claim 7, wherein the barrier layer comprises titanium and titanium nitride.
9. The method as claimed in claim 7, wherein the metal layer comprises tungsten.
10. The panel as claimed in claim 7, wherein the metal layer is planarized by chemical mechanical polishing.
11-17. (canceled)
Type: Application
Filed: Sep 29, 2006
Publication Date: Jan 25, 2007
Applicant: NANYA TECHNOLOGY CORPORATION (TAOYUAN)
Inventors: Wen-Kuei Hsieh (Tainan County), Hui-Min Mao (Taipei City), Yi-Nan Chen (Taipei City)
Application Number: 11/540,392
International Classification: H01L 23/544 (20060101);