Patents Assigned to Nanya Technology Corporation
  • Publication number: 20240194240
    Abstract: The memory device of the disclosure includes a fuse voltage generator, a fuse storage and a logic circuit. The fuse voltage generator generates a fuse voltage in response to an enable signal having a first logic level, and stop generating the fuse voltage in response to the enable signal having a second logic level. The fuse storage storages a setting data of the memory device. The fuse storage outputs the setting data in response to the fuse voltage. The logic circuit generates the enable signal in response to at least two operating signals.
    Type: Application
    Filed: December 9, 2022
    Publication date: June 13, 2024
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 12009022
    Abstract: A semiconductor device can be applied to a memory device. The semiconductor device of the disclosure includes a voltage sensor, a convertor and a command/address on-die-termination (CA_ODT) circuit. The voltage sensor receives a voltage setting command, and sense a voltage level of the voltage setting command to generate a sensing signal. The convertor generates a setting signal in response to the sensing signal. The CA_ODT circuit generates a power voltage for the memory device in response to the setting signal, wherein a voltage level of the power voltage corresponds to the voltage level of the voltage setting command.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: June 11, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Ting Lin
  • Patent number: 12009212
    Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 11, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 12007800
    Abstract: A power voltage supply device, including a reference bias voltage generating circuit, a temperature compensation bias voltage generating circuit, a compensation voltage generator, and a voltage buffer, is provided. The reference bias voltage generating circuit generates a reference bias voltage. The temperature compensation bias voltage generating circuit generates a temperature compensation bias voltage that changes as temperature rises. The compensation voltage generator generates a first power voltage based on the reference bias voltage, and selectively boosts the first power voltage based on the temperature compensation bias voltage. An input terminal of the voltage buffer receives the first power voltage. The voltage buffer generates a second power voltage corresponding to the first power voltage to a load circuit.
    Type: Grant
    Filed: July 17, 2022
    Date of Patent: June 11, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Hang Chang
  • Patent number: 12009424
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a first surface and a second surface protruding from the first surface of the substrate; a gate oxide layer disposed on the second surface of the substrate; and a first spacer disposed on the first surface of the substrate, and contacting the substrate and the gate oxide layer.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: June 11, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 12002803
    Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: June 4, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Patent number: 12000890
    Abstract: An electronic device including a phase detector is provided. The phase detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first equalizer device. The first transistor has a first input terminal configured to receive a first signal. The second transistor has a second input terminal configured to receive a second signal. The third transistor is electrically connected to the first transistor and has a first output terminal. The fourth transistor is electrically connected to the second transistor and has a second output terminal. The first equalizer device is connected between the first output terminal and the second input terminal.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: June 4, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 12002772
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: June 4, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Teng-Yen Huang
  • Patent number: 12002752
    Abstract: The present disclosure provides a method for manufacturing a fuse component having a three-dimensional (3D) structure. The method includes providing an active region, forming a first recess region and a second recess region in the active region, disposing a fuse dielectric material in the first recess region and the second recess region, and filling the first recess region and the second recess region with a gate metal material.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: June 4, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Kai-Po Shang, Jui-Hsiu Jao
  • Patent number: 12002765
    Abstract: A mark for overlay error measurement and overlay error measurement is provided. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate. The second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern collaboratively define a first overlay error.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: June 4, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Yuan Ma
  • Publication number: 20240177763
    Abstract: A word line pump device of a dynamic random access memory (DRAM) chip and a clamp circuit thereof are provided. The DRAM chip receives a first voltage and a second voltage from outside, and the first voltage is smaller than the second voltage. The clamp circuit clamps a word line voltage to the second voltage in response to the word line pump device not receiving a power supply voltage.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 11996390
    Abstract: The present application discloses a semiconductor device with stacking structures. The semiconductor device includes a bottom die; a first stacking structure including a first controller die positioned on the bottom die, and a plurality of first storage dies stacked on the first controller die; and a second stacking structure including a second controller die positioned on the bottom die, and a plurality of second storage dies stacked on the second controller die. The plurality of first storage dies respectively include a plurality of first storage units configured as a floating array. The plurality of second storage dies include a plurality of second storage units respectively including an insulator-conductor-insulator structure.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: May 28, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11983066
    Abstract: The present disclosure provides a data storage device. The data storage device includes a first area configured to store a first data; a second area configured to store a second data. The second data is associated with the first data, and the first data and/or the second data exclude an ECC.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Patent number: 11984389
    Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.
    Type: Grant
    Filed: April 23, 2023
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-Chung Wang, Hsih-Yang Chiu
  • Patent number: 11984397
    Abstract: A semiconductor structure includes a substrate, first and second transistors, first and second fuses, a contact structure, and a dielectric layer. The substrate has first and second device regions, and a fuse region. The first and second transistors are respectively above the first and second device regions. The first fuse is electrically connected to the first transistor and includes a first fuse active region having first and second portions. The second fuse is electrically connected to the second transistor and includes a second fuse active region having third and fourth portions. The contact structure interconnects the second portion and the third portion, wherein the first portion and the fourth portion are on opposite sides of the contact structure. The dielectric layer is between the contact structure and the fuse region of the substrate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wei-Zhong Li, Hsih-Yang Chiu
  • Patent number: 11984511
    Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11985816
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain region positioned in the substrate; a common source region positioned in the substrate and opposing to the drain region; a bit line structure including a bit line conductive layer positioned on the substrate and electrically coupled to the common source region; a cell contact positioned on the substrate, adjacent to the bit line structure, and electrically connected to the drain region; a landing pad positioned above the bit line conductive layer and electrically connected to the cell contact; and an air gap positioned between the landing pad and the bit line conductive layer.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 14, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Liang-Pin Chou
  • Patent number: 11978662
    Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: May 7, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Liang-Pin Chou
  • Patent number: 11978785
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor substrate having an active region, forming a fin structure in the active region, and forming a conductive element on the body portion and the first tapered portion of the fin structure. The fin structure includes a body portion, and a first tapered portion protruding from an upper surface of the body portion.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 7, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11978500
    Abstract: The present disclosure provides a memory device. The memory device includes a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate. The first metallization layer is disposed within the dielectric layer and extends along a first direction. The first channel layer is surrounded by the first metallization layer. The second metallization layer is disposed within the dielectric layer and extends along the first direction. The second channel layer is surrounded by the second metallization layer. The first metallization layer includes a first protruding portion protruding toward the second metallization layer.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: May 7, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jar-Ming Ho