Patents Assigned to Nanya Technology Corporation
  • Patent number: 10418356
    Abstract: The present disclosure provides a diode structure and an electrostatic discharge (ESD) protection circuit including the same. The diode structure includes a P-type substrate. The diode structure further includes a plurality of wavy N-doping regions formed on the P-type substrate. Each of the wavy N-doping regions extends in a first direction and has an N-doping width in a second direction perpendicular to the first direction. The diode structure further includes a plurality of wavy P-doping regions formed on the P-type substrate. Each of the wavy P-doping regions extends in the first direction and has a P-doping width in the second direction. The N-doping widths are essentially identical at different positions along the first direction, and the P-doping widths are essentially identical at different positions along the first direction.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 17, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Fang-Wen Liu, Tseng-Fu Lu
  • Patent number: 10410910
    Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps. A substrate is provided. A plurality of first trenches, a plurality of second trenches, a plurality of first island structures and a plurality of second island structures are formed. Each of the first island structures is separated from each of the second island structures by the first trenches. The plurality of first island structures are separated from each other by the second trenches, and the plurality of second island structures are separated from each other by the second trenches. A first dielectric layer is then conformally formed to cover sidewalls and a bottom of each first trench and sidewalls and a bottom of each second trench. A semiconductor layer is formed on the first dielectric layer. An oxidation is performed to convert the semiconductor layer into a semiconductor oxide layer in each of the first trenches and each of the second trenches.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 10, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10394735
    Abstract: A circuitry includes a source circuit; a first circuit; a second circuit; and a data-distributing circuit including: a receiving circuit configured to receive a first datum for the first circuit via a first and second front line, and to receive from the source circuit a second datum for the second circuit via a third front line and a fourth front line; and a forwarding circuit configured to receive one of the first datum and the second datum via a first intermediate line and a second intermediate line, to receive a target address associated with the one of the first datum and the second datum via a third intermediate line, and, according to the target address, provide the one of the first datum and the second datum to one of the first circuit and the second circuit.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 27, 2019
    Assignee: Nanya Technology Corporation
    Inventor: Wen Ming Lee
  • Patent number: 10395976
    Abstract: A method of manufacturing a semiconductor device includes: forming a first patterned target layer on a substrate having a first region and a second region, the first patterned target layer has first stripes and first openings along a first direction; sequentially forming a lower hardmask layer and a middle hardmask layer covering the first patterned target layer; forming a patterned upper hardmask layer on the middle hardmask layer, the patterned upper hardmask layer has second stripes and second openings along a second direction and exposing a portion of the middle hardmask layer; etching the exposed portion of the middle hardmask layer to form third openings exposing a portion of the lower hardmask layer; and etching the exposed portion of the lower hardmask layer and the first patterned target layer thereunder to form a second patterned target layer having rounded patterns on the first region.
    Type: Grant
    Filed: May 13, 2018
    Date of Patent: August 27, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Szu-Han Chen
  • Patent number: 10381351
    Abstract: The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10381307
    Abstract: The present invention provides a method of forming a barrier layer over a via or a trench. The method includes generating a high density plasma in a chamber and depositing a barrier material over the via or the trench by using the high density plasma. The depositing of the barrier material comprises at least a first deposition step, a second deposition step and a third deposition step in sequence. The first, second and third deposition steps is respectively performed under a first bias power, a second bias power and a third bias power. The third bias power is greater than the second bias power, and the second bias power is greater than the first bias power. The present invention also provides a via structure formed by the method.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wen-Hua Lien
  • Patent number: 10380024
    Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10373932
    Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 6, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10361171
    Abstract: A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: July 23, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 10354713
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 16, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10348194
    Abstract: The present disclosure provides a pump circuit comprising a plurality of first enabling modules. Each of the plurality of first enabling modules is configured to generate a first enable signal and includes a first voltage input, a first comparing unit, a first digital logic gate and a second digital logic gate. The first comparing unit is coupled to the first voltage input and is configured to compare a voltage of the first voltage input with a first reference voltage. The first digital logic gate is coupled to the first comparing unit and is configured to implement a logical operation. The second digital logic gate is coupled to the first digital logic gate and is configured to implement a logical negation. Each of the plurality of first enabling modules generates the first enable signal when the voltage of the first voltage input is less than the first reference voltage.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 9, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Jen Chen, Ting-Shuo Hsu
  • Patent number: 10338831
    Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10340149
    Abstract: A method of forming dense hole patterns of semiconductor devices includes: forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate; forming a spacer layer on the lower hard mask layer to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars; etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars; removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer; etching the first portions and the second portions of the lower hard mask layer at least until portions of the substrate are exposed; and removing remaining portions of the spacer layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Jen-Jui Huang
  • Patent number: 10332579
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10332749
    Abstract: A method includes forming a plurality of first core features and one frame feature encircling the first core features. The first core features extend along a first direction and are arranged along a second direction perpendicular to the first direction, and each of the first core features is spaced apart from the frame feature by a first gap along the first direction. The method also includes forming a spacer layer filling the first gaps and forming a plurality of individual recesses entirely separated from each other. The method also includes forming a plurality of second core features in the individual recesses, wherein the second core features are entirely separated from each other and are spaced apart from the frame feature by the spacer layer. The method then removes the spacer layer to form a plurality of openings between the first core features, the second core features and the frame feature.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Patent number: 10332580
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10325644
    Abstract: The present disclosure provides a pump circuit comprising a temperature-sensing module, an oscillating module and a pumping module. The temperature-sensing module is configured to measure a temperature of a dynamic random access memory (DRAM). The oscillating module is coupled to the temperature-sensing module and is configured to generate a clock signal based on the temperature of the DRAM. The pumping module is coupled to the oscillating module and is configured to generate a pump voltage and a pump current to drive the DRAM, wherein the pump current is generated based on an oscillating frequency of the clock signal. When the temperature of the DRAM changes, the oscillating frequency of the clock signal changes based on the temperature of the DRAM, and the pump current correspondingly changes based on the oscillating frequency of the clock signal.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 18, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10325991
    Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 18, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shih-Ting Lin, Jhen-Yu Tsai
  • Patent number: 10310549
    Abstract: An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 4, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Jen Chang, Wen-Ming Lee
  • Patent number: 10304516
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a storage area and a control device. The storage area includes a memory row. The control device is configured to selectively allow the memory row to be eligible for a row-hammer refresh according to temperature of the DRAM.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 28, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-jen Chen