Patents Assigned to Nanya Technology Corporation
  • Patent number: 11521926
    Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 11521978
    Abstract: The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising a first region and a second region; a first semiconductor element positioned in the first region of the substrate; a second semiconductor element positioned in the first region of the substrate and electrically coupled to the first semiconductor element; and a programmable unit positioned in the second region and electrically connected to the first semiconductor element.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Ling Yang
  • Patent number: 11521916
    Abstract: The present application discloses provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first conductive layer, forming a first etch stop layer on the first conductive layer, bonding a second semiconductor die, which includes a second conductive layer above the first etch stop layer and a second etch stop layer on the second conductive layer, onto the first etch stop layer, performing a via etch process to concurrently form a first via opening to expose the first etch stop layer and a second via opening to expose the second etch stop layer, conformally forming isolation layers in the first via opening and the second via opening, performing a punch etch process to extend the first via opening and the second via opening, and concurrently forming a first through substrate via in the first via opening and a second through substrate via in the second via opening.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11521974
    Abstract: A memory device includes a semiconductor substrate having a first active region and a second active region adjacent to the first active region. The memory device also includes a first word line extending across the first active region and the second active region. The memory device further includes a first source/drain region in the first active region and a second source/drain region in the second active region disposed at opposite sides of the first word line. In addition, the memory device includes a first capacitor disposed over and electrically connected to the first source/drain region in the first active region, and a second capacitor disposed over and electrically connected to the second source/drain region in the second active region. The first capacitor and the second capacitor have different sizes.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jung-Hsing Chien
  • Patent number: 11521976
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bit line structure positioned above the substrate and including a first line portion arranged in parallel to a first direction, and a second line portion connecting to a first end of the first line portion and arranged in parallel to a second direction in perpendicular to the first direction; a first bit line top contact including a first bar portion positioned on the first end of the first line portion and arranged in parallel to the first direction, and a second bar portion connecting to a first end of the first bar portion, positioned on the second line portion, and arranged in parallel to the second direction; and a first top conductive layer electrically coupled to the first bit line top contact.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Ting Tsai, Jui-Hsiu Jao
  • Patent number: 11521924
    Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11521945
    Abstract: The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Chi Lai
  • Patent number: 11521883
    Abstract: The present disclosure provides a substrate processing apparatus including at least one input/output chamber. The load lock device includes a base, a guide rail, a platform and an optical measuring module. The guide rail is connected to the base. The platform, carrying a cassette for holding a batch of spaced substrates, is movably disposed on the guide rail. The optical measuring module is configured to acquire an actual moving distance traveled by the platform along the guide rail based on at least one optical signal reflected from the platform.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chia-Fu Chen
  • Patent number: 11521892
    Abstract: The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ping Hsu
  • Patent number: 11521901
    Abstract: The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: December 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chun-Shun Huang, Jui-Hsiu Jao, Wei-Li Lai
  • Patent number: 11515312
    Abstract: A memory cell includes a semiconductor substrate, a transistor, and a first anti-fuse structure. The transistor is above the semiconductor substrate. The first anti-fuse structure is above the semiconductor substrate and adjacent the transistor, and includes a first terminal and a second terminal. The first terminal of the first anti-fuse structure is in the semiconductor substrate and laterally surrounds the transistor. The second terminal of the first anti-fuse structure is above and spaced apart from the first terminal of the first anti-fuse structure.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: November 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11515388
    Abstract: The present application discloses a semiconductor device with a P-N junction isolation structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first well layer positioned in the substrate and having a first electrical type, a bottom conductive layer positioned in the first well layer and having a second electrical type opposite to the first electrical type, a first insulating layer positioned on the bottom conductive layer, an isolation-mask layer positioned on the substrate and enclosing the first insulating layer, a first conductive line positioned on the first insulating layer, and a bias layer positioned in the first well layer and spaced apart from the bottom conductive layer. The bottom conductive layer, the first insulating layer, and the first conductive line together configure a programmable unit.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11515310
    Abstract: A cell array includes a substrate and a conductive line. The substrate has active areas in the substrate. The conductive line is disposed across the active areas and includes work function nodes and line sections which are horizontally and alternately arranged with work function nodes, in which each work function node is between two of the active areas.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: November 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tsung-Yu Tsai
  • Patent number: 11515405
    Abstract: The present application discloses a method for fabricating a semiconductor device with a programmable feature such as anti-fuse The method includes forming a semiconductor fin on a buried insulating layer; forming a dummy gate structure on the semiconductor fin; forming a top insulating layer over the semiconductor fin and covering the dummy gate structure; removing the dummy gate structure and concurrently forming a first trench in the top insulating layer; performing an etch process in the first trench to form a tapered pit separating the semiconductor fin; forming a first insulating layer to completely fill the first trench and the tapered pit; and replacing the semiconductor fin with first conductive blocks.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: November 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11508729
    Abstract: The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11508722
    Abstract: A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a gate electrode and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure. The S/D region is electrically connected to the resistor electrode.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11508653
    Abstract: The present disclosure provides a semiconductor component including a substrate, a plurality of metallic lines, a passivation layer and a spacer. The metallic lines are disposed on the substrate, the passivation layer is disposed over the substrate and the metallic lines, and the spacer is interposed between the substrate and the dielectric layer and between the metallic lines and the dielectric layer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: November 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Da-En Chien
  • Patent number: 11502025
    Abstract: The present application discloses a semiconductor device with an etch stop layer having greater thickness and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor die including a first conductive layer, a first etch stop layer positioned on the first conductive layer, a second semiconductor die including a second conductive layer positioned above the first etch stop layer, a second etch stop layer positioned on the second conductive layer, a first through substrate via positioned along the second semiconductor die and the first etch stop layer, extended to the first semiconductor die, and positioned on the first conductive layer, and a second through substrate via extended to the second semiconductor die, positioned along the second etch stop layer, and positioned on the second conductive layer. A thickness of the second etch stop layer is greater than a thickness of the first etch stop layer.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11502075
    Abstract: A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu
  • Patent number: 11502163
    Abstract: A semiconductor structure includes an active region, an isolation structure, a first gate structure, and a second gate structure. The active region is disposed over a semiconductor substrate and has a first portion, a second portion, and a third portion. The third portion is between the first portion and the second portion. A shape of the first portion is different from a shape of the third portion, in a top view. The isolation structure is disposed over the semiconductor substrate and surrounds the active region. The first gate structure is disposed between the first portion and the third portion of the active region. The second gate structure is disposed between the second portion and the third portion of the active region.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu