Patents Assigned to Nanya Technology Corporation
  • Patent number: 10896848
    Abstract: A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: January 19, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10886236
    Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Hsih-Yang Chiu
  • Patent number: 10886406
    Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate having a pattern-dense region and a pattern-loose region; a first drain stressor disposed in the pattern-dense region; a first source stressor disposed in the pattern-dense region; a buried gate structure disposed in the pattern-dense region, between the first drain stressor and the first source stressor; a second drain stressor disposed in the pattern-loose region; a second source stressor disposed in the pattern-loose region; and a planar gate structure disposed in the pattern-loose region, between the second drain stressor and the second source stressor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chang-Chieh Lin
  • Patent number: 10879125
    Abstract: The present disclosure relates to a FinFET structure and a method of manufacturing the same. The FinFET structure includes a first fin and a second fin. The first fin is over a first base and has a first channel region. The first channel region has a first channel length. The second fin is over a second base and has a second channel region. The second channel region has a second channel length. The second channel length is different from the first channel length.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: December 29, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Chun-Heng Wu
  • Patent number: 10878881
    Abstract: The memory apparatus includes a plurality of memory chips and a plurality of temperature sensors. The memory chips are coupled to each other. The temperature sensors are respectively disposed on the memory chips. One of the memory chips is configured to be a master memory chip, and a first temperature sensor of the master memory chip is enabled to sense an ambient temperature. The master memory chip generates a refresh rate control signal according to the ambient temperature and controls refresh rates of all of the memory chips.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10877086
    Abstract: A holder includes a substrate, at least one first fastener and a pressure block. The substrate includes a top surface, a primary recess recessed from the top surface, at least one first side-recess recessed from the top surface, wherein the first side-recess neighbors and communicates with the primary recess, and a channel recess recessed from the top surface, wherein the channel recess neighbors and communicates with the primary recess, and the first side-recess and the channel recess are positioned at opposite sides of the primary recess. The first fastener is disposed in the first side-recess, wherein the first fastener has a top substantially leveled with the top surface of the substrate. The pressure block is disposed in the channel recess, wherein the pressure block has a top substantially leveled with the top surface of the substrate.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: December 29, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chung Wang, Jui-Hsiu Jao
  • Patent number: 10868467
    Abstract: A pump circuit is disclosed. The pump circuit includes a first pump core circuit and a second pump core circuit. The second pump core circuit is coupled to the first pump core circuit. When a voltage value of a power source input to the pump circuit is not lower than a threshold voltage value, the first pump core circuit is operated and the second pump core circuit is not operated. When the voltage value of the power source is lower than the threshold voltage value, the first pump core circuit and the second pump core circuit are operated, so that a current value of the output current transmitted by the pump circuit is not lower than a threshold current value.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: December 15, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10861711
    Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure including a plurality of conductive pads on a substrate, an etch stop layer between the conductive pads, and an UBM layer on the conductive pads and the etch stop layer. A plurality of mask structures are formed on the UBM layer, and a plurality of openings are formed between thereof. Each of the mask structures is located on one of the conductive pads, and the openings expose a first portion of the UBM layer. A supporting layer is formed in the openings. The mask structures are removed to form a plurality of cavities exposing a second portion of the UBM layer. A conductive material layer is formed in the cavities. The supporting layer is removed. The first portion of the UBM layer is removed to form a plurality of conductive bumps separated from each other.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 8, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10854545
    Abstract: An anti-fuse structure includes a substrate, an active layer, an electrode layer, and a dielectric layer. The active layer is on the substrate and has a body portion and a convex portion protruding from the body portion. The electrode layer is on the active layer and partially overlaps the convex portion of the active layer. The electrode layer has a hollow region, and the convex portion of the active layer is in the hollow region. The dielectric layer is between the active layer and the electrode layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 1, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Chiang-Lin Shih
  • Patent number: 10840136
    Abstract: The present disclosure provides a method for preparing a conductive plug. The method includes forming a first conductive structure over a substrate; forming a first dielectric structure over the first conductive structure; transforming a sidewall portion of the first conductive structure into a first dielectric portion; and removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: November 17, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 10833029
    Abstract: The present disclosure relates to an electronic device and a method of manufacturing a filtering component of the electronic device. The electronic device includes a semiconductor component, an insulating layer, at least one contact plug, and a filtering component. The insulating layer is disposed on the semiconductor component. The contact plug penetrates through the insulating layer. The filtering component is disposed on the insulating layer and the contact plug. The filtering component includes a bottom electrode, an isolation layer, a top electrode, and a dielectric layer. The bottom electrode is divided into a first segment connected to the contact plug and a second segment separated from the first segment. The isolation layer is disposed on the bottom electrode, the top electrode is disposed in the isolation layer, and the dielectric layer is disposed between the bottom electrode and the top electrode.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 10, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Hsih-Yang Chiu, Ting-Cih Kang
  • Patent number: 10825794
    Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10825799
    Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a semiconductor unit, one or more bonding structures, and at least one supporter. The semiconductor unit includes at least one via. The one or more bonding structures are disposed over the semiconductor unit and electrically connected to the at least one via. The at least one supporter is disposed over the semiconductor unit. The at least one supporter is a metal block or a polymer block spaced apart from the one or more bonding structures.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Shing-Yih Shih
  • Patent number: 10825796
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a device chip and a protecting material. The device chip has an active area and an inactive area arranged around the active area. The protecting material includes a first portion and a second portion, the first portion is disposed within the inactive area and encircles the active area, and the second portion is disposed over a lower surface of the device chip.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Hsih-Yang Chiu
  • Patent number: 10825898
    Abstract: The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10825823
    Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a substrate, a main device, a one-time-programmable (OTP) device and a decoupling capacitor array. The substrate includes a first region and a second region. The main device is in the first region, the OTP device and the decoupling capacitor array are in the second region, and the decoupling capacitor array overlies the OTP device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shian-Jyh Lin
  • Patent number: 10825722
    Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure on a substrate. The precursor structure includes a first conductive structure, a first spacer layer, and a spacer oxide layer sequentially on the substrate. The spacer oxide layer exposes a top surface of the first spacer layer. The spacer oxide layer is then recessed. A second spacer layer is formed to cover the spacer oxide layer and the first spacer layer. A portion of the second spacer layer and a portion of the spacer oxide layer are then etched to expose the lateral portion of the first spacer layer. The remaining spacer oxide layer is etched to form an air gap between the first spacer layer and the second spacer layer. A third spacer layer is formed on the lateral portion of the first spacer layer to seal the air gap.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Fan Kuan
  • Patent number: 10825744
    Abstract: A method includes forming a transistor over a substrate; forming a conductive structure over the substrate, such that a first end of the conductive structure is electrically coupled to a gate of the transistor, and a second end of the conductive structure is electrically coupled to the substrate; applying biases to the gate of the transistor and source/drain structures of the transistor; determining whether the first end and the second end of the conductive structure are electrically connected; generating, based on the determination, a first result indicating that the first end and the second end of the conductive structure are electrically connected; and qualifying the conductive structure as an antenna in response to the first result.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tsang-Po Yang, Jui-Hsiu Jao, Chun-Shun Huang
  • Patent number: 10825931
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10818341
    Abstract: A sub-word line driver circuit includes a substrate, a plurality of gate lines, at least one gate tab, and a variable-thickness gate dielectric. The substrate includes an isolation area and an active area. The gate lines are arranged in a first direction and extend in a second direction perpendicular to the first direction. The gate tab extends in the first direction to cover the isolation area, in which the gate lines and the gate tab form at least one gate region on the substrate. The variable-thickness gate dielectric includes a thick gate dielectric region disposed over a first portion of the active area, and a thin gate dielectric region disposed over a second portion of the active area.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 27, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai