Abstract: A signal receiving circuit and a noise filtering method thereof are provided. The signal receiving circuit includes an operational amplifier circuit and a voltage offset adjustment circuit. A first input terminal and a second input terminal of the operational amplifier circuit receive a differential signal, a third input terminal receives a reference voltage, and the operational amplifier circuit compares the differential signal with the reference voltage to generate an output signal. The voltage offset adjustment circuit is coupled to the third input terminal of the operational amplifier circuit, and provides an offset voltage to adjust the reference voltage.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure extending along a first direction and electrically connected to a first transistor, a second gate structure extending along the first direction and electrically connected to a second transistor, a first active region extending along a second direction different from the first direction and across the first gate structure and the second gate structure, and a first conductive element extending along the second direction and disposed on the first active region. The first conductive element is electrically connected to the first active region. The first conductive element is electrically connected to the first active region, such that a short circuit between the first active region and the third transistor is formed. The first gate structure and the first active region form a first fuse element, and the second gate structure and the first active region form a second fuse element.

Abstract: The present application provides an optical semiconductor device with a composite intervening structure. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. The intervening structure is disposed on the back surface of the memory die.

Abstract: An off-chip driving device and a driving capability enhancement method thereof are provided. Detecting a rising edge and a falling edge of an input data signal. A first enhancement circuit is controlled to provide a first enhancement signal to an input/output pad according to the rising edge and the falling edge of the input data signal.

Abstract: An electronic device and phase detector are provided. The phase detector includes a first input terminal, a second input terminal, a first input buffer, and a second input buffer. The first input buffer is electrically connected to the first input terminal. The second input buffer is electrically connected to the second input terminal.

Abstract: A time-to-digital converter apparatus and a converting method thereof are provided. An output signal of a first ring oscillator circuit is counted to generate a first digital code. An output signal of a second ring oscillator circuit is counted to generate a second digital code. A corresponding third digital code is generated according to a time point of phase coincidence between one of outputs of a plurality of first delay stages of the first ring oscillator circuit and one of outputs of a plurality of second delay stages of the second ring oscillator circuit.

Abstract: The present application provides a method for manufacturing a capacitor array. The method includes steps of depositing a sacrificial layer on a bottom electrode; depositing an insulative layer on the sacrificial layer; forming a polysilicon hardmask on the insulative layer; etching the insulative layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hardmask to form channels; depositing a metal film on the polysilicon hardmask and in the channels; depositing a passivation film on the metal film; depositing a conductive material in the channels and in contact with the insulative layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulative layer.

Abstract: An interconnect structure includes first, second, and third insulating layers, first, second, and third conductive lines, and first, second, third, and fourth conductive vias. The first conductive line is embedded in the first insulating layer. The second conductive line is embedded in the second insulating layer and comprises a first portion, a second portion, and a third portion. The third conductive line is embedded in the third insulating layer. The first and second conductive via are embedded in the first insulating layer. The third and fourth conductive via are embedded in the second insulating layer. A first cross-sectional area surrounded by the first conductive line, the first conductive via, the second conductive via, the first portion, and the second portion is substantially equal to a second cross-sectional area surrounded by the first portion, the third portion, the third conductive via, the fourth conductive via, and the third conductive line.

Abstract: A semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. A portion of the bonding pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. The portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.

Abstract: The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Abstract: A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.

Abstract: The present disclosure provides a gas purge device and a gas purge method for purging a wafer container to clean wafers. The gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.

Abstract: A method of manufacturing a semiconductor device includes providing a precursor structure including a first capacitor and a second capacitor on a substrate; forming a first vertical transistor and a second vertical transistor respectively over the first capacitor and the second capacitor, in which the first vertical transistor includes a first word line having a first top width and a first bottom width smaller than the first top width, the second vertical transistor includes a second word line having a second top width and a second bottom width smaller than the second top width; and forming an air gap between the first vertical transistor and the second vertical transistor.

Abstract: A transmission device is provided. The transmission device includes a voltage generator, a convertor, a voltage buffer and a transmission element. The voltage generator generates a first voltage signal according to a first current. The convertor generates a second current using a source current proportional to a temperature, generates a third current according to the first voltage signal, and converts a sum of the second current and the third current to a second voltage signal. The voltage buffer generates a driving voltage proportional to the temperature according to the second voltage signal. The transmission element operates based on the driving voltage.

Abstract: The present application provides a memory device having a bit line (BL) with a stepped profile. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

Abstract: The present disclosure provides an electronic system with defect identification function and a method of qualifying a photoresist pattern formed using a lithography process. The electronic system includes an inspection apparatus and a processor associated with the inspection apparatus. The inspection apparatus is used for acquiring at least one image of the specimen on which a photoresist pattern is formed using a lithography process. The processor is configured to automatically apply machine learning processes implemented through one or more neural networks to identify at least one defect present in the photoresist pattern.

Abstract: The present disclosure provides a semiconductor structure with a single side capacitor. The semiconductor structure includes a substrate having a first landing pad therein, and a first capacitor disposed over the substrate. The first capacitor includes: a first electrode, disposed over and extending vertically away from the first landing pad; a first dielectric layer, at least partially surrounding the first electrode, wherein the first electrode is shorter than the first dielectric layer; and a second electrode, surrounding the first dielectric layer and the first electrode.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor die, a package substrate and bonding wires. The semiconductor die has I/O pads arranged at an active side. The package substrate is provided with a first side attached to the active side of the semiconductor die and a second side facing away from the semiconductor die, and has an opening penetrating through the package substrate. The I/O pads are overlapped with the opening. A width of the opening at the second side of the package substrate is greater than a width of the opening at the first side of the package substrate. The bonding wires connect the I/O pads to the second side of the package substrate through the opening of the package substrate.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device comprises a substrate, a plurality of isolation regions in the substrate and an active region surrounded by the isolation regions. A p-type doped region is interposed between two n-type doped regions in the substrate. A buried gate structure is formed in the substrate and disposed between the p-type doped region and the n-type doped region. The buried gate structure comprises a gate conductive material, a gate insulating layer disposed over the gate conductive material and a gate liner surrounding the gate conductive material and the gate insulating layer. A plurality of contact plugs are formed on the p-type doped region and the plurality of n-type doped regions.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate; a plug structure including a bottom conductive layer positioned on the substrate, a middle conductive layer positioned on the bottom conductive layer, a top conductive layer positioned on the middle conductive layer, and an insulating covering layer covering a sidewall of the middle conductive layer and positioned between the bottom conductive layer and the top conductive layer; and a first dielectric layer positioned on the substrate and surrounding the plug structure. A width of the bottom conductive layer is greater than a width of the middle conductive layer. A width of the top conductive layer is greater than the width of the middle conductive layer.