DEVICES WITH DIFFERENT ELECTRICAL GATE DIELECTRIC THICKNESSES BUT WITH SUBSTANTIALLY SIMILAR PHYSICAL CONFIGURATIONS
An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.
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This application is a continuation of co-pending application Ser. No. 10/886,215 filed Jul. 6, 2004, the contents of which are herein incorporated by reference as if set forth in their entirety.
BACKGROUNDThe present invention generally relates to integrated circuits (IC), and more particularly to logic and memory ICs that utilize a multi-stage doping methodology to electrically adjust characteristics of a metal-oxide-semiconductor field effect transistor (MOSFET) and for reducing the size of the same.
As MOSFETs continuously downscale, the thermal budget, source/drain junction depth and dopant concentration are reduced for alleviating short channel effects. However, there is a limit to this trend of reduction. If the limit is exceeded, the lower poly gate doping profile can change, which may induce an undesirable depletion region between the gate electrode and the gate dielectric layer. If the gate dopant concentration does not saturate enough, it will increase the electrical gate dielectric thickness and degrade the MOSFET saturation current. The electrical gate dielectric thickness is the equivalent thickness of the gate dielectric layer under certain electrical conditions. Two MOSFETs with the same physical gate dielectric thickness may have different electrical gate dielectric thickness. For example, those two MOSFETs operating under different electrical conditions, e.g., with different gate dopant concentrations, can have significantly unmatched electrical gate dielectric thickness. In general, one of the MOSFETs may have a “thinner” electrical gate dielectric thickness than the other if it has a greater gate dopant concentration. As such, an insufficiently doped gate electrode usually results in an undesirably thick electrical gate dielectric thickness.
Conventionally, only a single-stage doping is performed for the gate structures of logic devices and memory cells in fabrication of an IC, such as SRAM and DRAM. For example, in an SRAM cell design, a pass gate device usually requires a narrower channel width and a longer channel length than a pull-down device, in order to obtain a high β ratio and static noise margin (SNM). However, such design will cause an inverse narrow width effect and decrease the β ratio in a low voltage operation. The long channel length design particularly causes the size of the memory cell to increase. An optimal design for an SRAM circuit should have a pass gate device with a higher threshold voltage and lower saturation current when compared to a pull-down device. As such, the electrical characteristics of the pass gate device and the pull-down device should be different.
A DRAM cell often includes a pass gate device coupled with a capacitor. In a DRAM cell design, the pass gate device leakage and capacitor gate leakage are the ones of major concerns. A lower gate leakage and sub-threshold leakage are desirable for a better data retention, reliability, and standby leakage current specification. In order to achieve these objectives, a thicker gate dielectric layer is needed for the pass gate device than other peripheral logic devices. This disparate thickness of gate dielectric layers complicates the fabrication process.
Desirable in the art of logic and memory devices fabrication are new MOSFETs with electrically adjusted gate structures that will result in minimal cell size while still meeting or exceeding the current electrical performance parameters.
SUMMARYIn view of the foregoing, an integrated circuit is disclosed having one or more devices having substantially similar physical gate dielectric thicknesses but different electrical gate dielectric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The construction of NMOS transistors 202 and 206 are identical except for their gate dopant concentrations. While the physical thicknesses of the first and second gate dielectric layers 205 and 209 are approximately the same, the gate dopant concentrations for the gate electrodes 204 and 208 are substantially different. The first gate electrode 204 has a first gate dopant concentration that is approximately 50% lower than a second gate dopant concentration of the second gate electrode 208. Typically, the physical gate dielectric thicknesses of the first and second gate dielectric layers 205 and 209 are less than about 20 Angstroms. However, the electrical performance of the first and second dielectric layers 205 and 209 are substantially different that results in at least an equivalent difference of a 2 Angstroms in the physical thickness due to the different dopant concentrations. In some cases, it can be more than 5 Angstroms in difference. It is understood that for the purpose of this invention, the electrical gate dielectric thickness is measured in terms of physical thickness.
In an IC that uses only the one-stage doping method, all MOSFETs within that IC will have the same gate dopant concentrations. In an IC that uses the proposed two-stage doping method, its MOSFETs would have different gate dopant concentrations as determined by operation needs for optimal IC device performance and reduced device size.
The two-stage gate doping methodology utilizes basically the same masks and same process steps as the conventional SRAM/DRAM. However, the two-stage gate doping utilizes an additional gate doping process for increasing the dopant concentration on selected devices. For example, a gate dielectric layer is first formed on a conducting channel between the source and drain by a chemical vapor deposition (CVD) process. A polysilicon layer is then formed atop the gate dielectric layer by a process, such as CVD and sputtering. This polysilicon layer is doped with N-type impurities for improving its conductivity. Thereafter, a second-stage doping is performed on selected devices. The second-stage doping results in a higher dopant concentration in the gate structures than those doped in the one-stage process. In NMOS transistors as shown in
As an another embodiment of this invention, more than two stage dopings may be implemented to create multiple gate dopant concentrations in devices, such as memory cells and logic devices. This would electrically adjust device characteristics to accommodate various operation needs. After the first and second gate doping processes are completed, more rounds of gate doping processes are performed on selected devices within an IC in order to form even more heavily doped gate structures.
This invention has an advantage of creating two devices with two different electrical gate dielectric thicknesses without altering the physical gate dielectric thickness. Thus, no additional mask is required to form a dielectric layer with different thicknesses in various areas. The lightly doped gate electrode has a higher threshold voltage, while the heavily doped gate electrode has a lower threshold voltage. By selecting devices for the different dopant concentrations, they may accommodate various operational needs. For example, a memory cell, such as an SRAM cell and a DRAM cell, often have devices requiring various threshold voltages.
The present two-stage doped gate structure can be implemented on the SRAM cell 400 by applying the two-stage gate doping process on selected devices, while all other devices would utilize the one-stage gate doping process. In this embodiment, the pass gate devices 404, 406 and Pull-up PMOS transistors 408, 412 will remain as one-stage, lightly doped devices due to their low gate leakage requirements. The Pull-down NMOS transistors 410, 414, and other peripheral logic devices (not shown in this figure) such as decoder circuits, NAND devices, NOR devices, inverter devices, selector circuits, sense amplifier circuits, etc., as well as other high performance devices (not shown in this figure) such as decoder circuits, NAND devices, NOR devices, inverter devices, would incorporate the two-stage doping process for reducing their gate channel length, and therefore, the device physical size. Typically the thicknesses of the gate dielectric layers for the pass gate devices 404, 406, Pull-up PMOS transistors 408, 412, Pull-down NMOS transistors 410, 414 and peripheral logic devices are less than 15 Angstroms. The physical gate dielectric thickness of all those devices are substantially the same, while the gate dopant concentration of the Pull-down NMOS transistors 410, 414 are substantially higher than the Pull-up PMOS transistors 408, 412 and the pass gate devices 404, 406. In addition, the gate dopant concentration of the peripheral logical devices and high performance devices are substantially greater than the Pull-down NMOS transistors 410, 414. The higher gate dopant concentration is about 50% greater than the lower gate dopant concentration. This results in the Pull-down NMOS transistors-410, 414 having electrical gate dielectric thicknesses substantially thinner than the pull-up PMOS transistors 408, 412 and the pass gate device 404, 406. The peripheral logic devices and high performance devices have electrical gate dielectric thicknesses substantially thinner than the pull-down NMOS transistors 410, 414.
The two-stage gate doping process would reduce the electrical gate dielectric thickness of these heavily doped devices, while leaving the pass gate devices 404, 406 and pull-up PMOS transistors 408 and 412 to be manufactured using the one-stage doping method on these devices. The advantage of using the two-stage gate doping process on the pull-down NMOS transistors and peripheral logic devices would result in a higher P ratio, a higher SNM at lower operational voltages, a higher threshold voltage, and most importantly, a smaller device physical size. These advantages are gained without additional masks or costs that would have incurred if a gate dielectric layer with various thicknesses are implemented.
It is noted that the present invention does not require any additional mask for implementing the additional doping process to form different gate dopant concentrations. In other words, multiple-dopant-concentration gate structures are created among different transistors on their interface between Si and gate dielectric layers. As such, the process effectively creates two or more classes of effective core gate dielectric thickness with no additional mask needed. As any additional masks can cost significantly for the manufacturing, the present invention provides an economical solution for fabrication. In addition, since the same mask set is used, the only additional process added for altering the electrical characteristics is the additional doping process (es), there is no additional cost for adding the extra doping steps to the regular manufacturing process flow. Furthermore, due to the different electrical thicknesses available by using different doping concentrations, pass gate device leakage or capacitor leakages are reduced. The beta ratio and static noise margin at lower operating voltage are improved.
The above invention provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and processes are described to help clarify the invention. These are, of course, merely examples and are not intended to limit the invention from that described in the claims.
Although illustrative embodiments of the invention have been shown and described, other modifications, changes, and substitutions are intended in the foregoing invention. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.
Claims
1. A memory circuit having one or more devices having substantially similar physical gate dielectric thicknesses but different electrical gate dielectric thicknesses, the memory circuit comprising:
- a first device comprising: a first gate dielectric layer, having a first physical gate dielectric thickness, formed on a substrate; a first gate electrode, having a first dopant concentration, formed atop the first gate dielectric layer;
- a second device comprising: a second gate dielectric layer, having a second physical gate dielectric thickness, formed on the substrate; a second gate electrode, having a second dopant concentration, formed atop the second gate dielectric layer,
- wherein the first physical gate dielectric thickness is substantially the same as the second physical gate dielectric thickness, and the first dopant concentration is made substantially greater than the second dopant concentration by at least one predetermined doping process after the first device has undergone a prior doping process with the second device to cause the first physical gate dielectric thickness to be thinner than the second physical gate dielectric thickness by no less than two Angstroms.
2. The memory circuit of claim 1 wherein the second physical gate dielectric thickness is at least 5 Angstroms greater than the first physical gate dielectric thickness.
3. The memory circuit of claim 1 wherein the first and second device have sub-micron channel lengths.
4. The memory circuit of claim 1 wherein the first physical gate dielectric thickness and the second physical gate dielectric thickness are less than about 20 Angstroms.
5. The memory circuit of claim 1 wherein the first dopant concentration is at least 50% greater than the second dopant concentration.
6. The memory circuit of claim 1 wherein the first gate electrode and the second gate electrode are doped with one or more N-type impurities.
7. The memory circuit of claim 1 wherein the first gate electrode and the second gate electrode are doped with one or more P-type impurities.
8. A DRAM circuit module comprising:
- a capacitance device for data storage;
- a pass gate device for selectively enabling the capacitance device to be electrically charged, wherein the pass gate device comprises: a first gate dielectric layer, having a first physical gate dielectric thickness, formed on a substrate; a first gate electrode, having a first dopant concentration, formed atop the first gate dielectric layer;
- a peripheral logical device for operating with the pass gate device, wherein the peripheral logical device comprises: a second gate dielectric layer, having a second physical gate dielectric thickness, formed on the substrate; a second gate electrode, having a second dopant concentration, formed atop the second gate dielectric layer,
- wherein the first physical gate dielectric thickness is substantially the same as the second physical gate dielectric thickness, and the second dopant concentration is made substantially greater than the first dopant concentration by at least one predetermined doping process after the pass gate device has undergone a prior doping process with the peripheral device.
9. The DRAM circuit module of claim 8 wherein the pass gate device has a first electrical gate dielectric thickness substantially greater than a second electrical gate dielectric thickness of the peripheral logic device.
10. The DRAM circuit module of claim 8 wherein the first physical gate dielectric thickness and the second physical gate dielectric thickness are less than 20 Angstroms.
11. The DRAM circuit module of claim 10 wherein the second dopant concentration is at least 50% greater than the first dopant concentration.
12. (canceled)
13. (canceled)
14. (canceled)
15. (canceled)
16. (canceled)
17. (canceled)
18. (canceled)
Type: Application
Filed: Aug 11, 2006
Publication Date: Feb 15, 2007
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu)
Inventor: Jhon Jhy Liaw (Hsin-Chu)
Application Number: 11/464,035
International Classification: H01L 29/94 (20060101);