Stacked chip package using warp preventing insulative material and manufacturing method thereof
In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.
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This application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2005-0080655 filed on Aug. 31, 2005, the content of which is incorporated herein by reference in its entirety. This application is related to U.S. patent application Ser. No. ______, entitled “Stacked Chip Package Using Photosensitive Polymer and Manufacturing Method Thereof”, by Yong-Chai Kwon, et al., filed of even date herewith and commonly owned with the present application, the content of which is incorporated herein by reference, in its entirety.
FIELD OF THE INVENTIONThe present invention relates to semiconductor device packages including a stacked chip package configuration that utilizes a photosensitive polymer including adhesive and warp prevention properties, and manufacturing methods thereof.
BACKGROUND OF THE INVENTIONSemiconductor manufacturing and packaging technology has evolved to the point where device packages can include multiple integrated circuit chips that are bonded together in a stacked, three-dimensional relationship. Such packages provide a smaller form factor and higher integration density at the package level. The chip stack configuration is amenable to high-speed operation, higher fan-out of signals, reduced noise levels for signal transmission between chips, low power operation, and enhanced functionality within a single package.
Three-dimensional bonding technology continues to progress. In a package level bonding configuration, devices are formed on a semiconductor wafer, and diced into chips. The individual chips are packaged in separate packages, and the packages are stacked and bonded together to form a multiple stack package (MSP). The resulting MSPs enjoyed widespread use in the past, but are relatively bulky and cumbersome for modern applications.
In a chip level bonding configuration, devices are formed on a semiconductor wafer, and diced into chips. The individual chips are stacked and bonded, and the chip stack is packaged within a single, common, package to form a multiple chip package (MCP) or a three-dimensional chip stack package (CSP). The resulting MCPs have characteristically high yield, however, process throughput is a problem, as each individual chip needs to be handled during alignment and bonding processes.
Recently, wafer level bonding configurations have become popular. In a wafer level bonding configuration, devices are formed on a semiconductor wafer, and multiple wafers are stacked so that their corresponding chips are aligned. The wafer stack is bonded together, and then diced into chip stacks. The chip stacks are each packaged within a single, common, package to form a wafer-level three-dimensional chip stack package (WL CSP). The resulting WL CSPs suffer from low yield. However, process throughput is high, as handling of each individual chip is not required, since the chips are stacked at the wafer level.
Chip level bonding and wafer level bonding are generally complicated and unstable manufacturing processes. In such bonding approaches, the individual chips transfer signals to each other in a vertical direction using inter-chip, vertical vias. The inter-chip vias pass through the respective chip substrates, and include a landing pad feature at a top portion thereof and a bump feature at a bottom portion thereof. When a bump of one chip is bonded with a pad of another chip according to the conventional approach, electrical bonding of the bump and pad first takes place, for example using a thermo-compression process at a temperature at least equal to the bonding eutectic point of the materials employed at the junction, and is followed by an underfill injection process for filling the gap between the chip substrates, to secure mechanical bonding. The underfill process is unreliable, since the gap between the lower and upper chip substrates is small, for example on the order of 20 μm. If the underfill process does not result in a complete and uniform fill of the gap, then any resulting voids can increase the likelihood of future generation of cracks. Such cracks can propagate during future heating and cooling cycles, decreasing the reliability of the resulting chip stack device.
In addition, mechanical stress can develop between layers of a chip or between adjacent chips of a package. Such stress is typically caused by a mismatch in coefficient of thermal expansion (CTE) between two adjacent layers. In the above chip stack configuration, the chip substrate, the metal of the landing pad, and the bonding material all have different CTE values. Such CTE mismatch can cause further cracking and delamination when subjected to numerous heating and cooling thermal cycles, negatively affecting device yield during manufacture, and device reliability during operation.
SUMMARY OF THE INVENTIONThe present invention is directed to semiconductor device packages including a stacked chip stack configuration that utilizes a photosensitive polymer layer that includes adhesive and warp prevention properties, and manufacturing methods thereof.
The present invention provides for a stacked chip package configuration, and manufacturing methods thereof, wherein the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids, and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with cracking and delamination. This leads to an improvement in device yield and device reliability.
In one aspect, the present invention is directed to a method of manufacturing a semiconductor device comprising: forming a first semiconductor device on a first substrate, the first semiconductor device including a first bonding pad on a first surface of the first substrate in a device region of the first semiconductor device; forming a first interconnect on the first surface of the first substrate, the first interconnect electrically coupled to the first bonding pad, and forming a conductive via through the first substrate, the conductive via being electrically coupled to the first interconnect and extending through a second surface of the first substrate opposite the first surface; forming a second semiconductor device on a second substrate, the second semiconductor device including a second bonding pad on a first surface of the second substrate in a device region of the second semiconductor device; forming a second interconnect on the first surface of the second substrate, the second interconnect electrically coupled to the second bonding pad; providing a photosensitive polymer layer on the second surface of the first substrate, a portion of the conductive via being exposed through the photosensitive polymer layer; and applying the second surface of the first substrate including the photosensitive polymer layer to the first surface of the second substrate and aligning the second interconnect of the second substrate with the exposed portion of the conductive via to electrically couple the first bonding pad to the second bonding pad.
In one embodiment, providing the photosensitive polymer layer further comprises patterning the photosensitive polymer layer to expose the portion of the conductive via.
In another embodiment, the first interconnect extends across the first surface of the first substrate in a direction toward an outer edge of the first substrate and wherein the second interconnect extends across the first surface of the second substrate in a direction toward an outer edge of the second substrate.
In another embodiment, the conductive via is formed in a scribe lane region of the first semiconductor device. In another embodiment, the conductive via is formed in a device region of the first semiconductor device.
In another embodiment, the method further comprises partially curing the photosensitive polymer layer prior to applying and aligning the first substrate to the second substrate.
In another embodiment, the method further comprises curing the photosensitive polymer layer following applying and aligning the first substrate to the second substrate.
In another embodiment, the photosensitive polymer layer comprises an insulating photosensitive polymer layer and providing the photosensitive polymer layer on the second surface of the first substrate comprises: removing substrate material from the second surface of the first substrate to expose a lower end of the conductive via; providing the insulating photosensitive polymer layer on the second surface of the first substrate; patterning the insulating photosensitive polymer layer to expose a lower end of the conductive via and to cover lower sidewall portions of the conductive via; and curing the insulating photosensitive polymer layer.
In another embodiment, the method further comprises: providing an adhesive photosensitive polymer layer on the insulating photosensitive polymer layer; partially curing the adhesive photosensitive polymer layer prior to applying and aligning the first substrate to the second substrate; and curing the adhesive photosensitive polymer layer following applying and aligning the first substrate to the second substrate.
In another embodiment, the method further comprises patterning the adhesive photosensitive polymer layer to expose the lower end of the conductive via.
In another embodiment, the method further comprises applying a conductive layer to an upper surface of the second interconnect.
In another embodiment, forming a conductive via through the first substrate comprises: forming a via hole in the first substrate that extends through the first surface of the first substrate and partially into the first substrate; providing an insulating layer that lines sidewalls of the via hole; filling the via hole with conductive material to form the conductive via; and removing substrate material from the second surface of the first substrate to expose a lower end of the conductive via.
In another embodiment, removing the substrate material comprises: grinding the second surface of the first substrate to remove substrate material; and etching the second surface of the first substrate and a portion of the insulating layer to expose the lower end of the conductive via and a lower portion of sidewalls of a lower end of the conductive via.
In another embodiment, the first semiconductor device on the first substrate and the second semiconductor device on the second substrate are formed on a common semiconductor wafer.
In another embodiment, the first semiconductor device on the first substrate and the second semiconductor device on the second substrate are formed on separate first and second semiconductor wafers.
In another embodiment, the conductive via comprises a first conductive via and the photosensitive polymer layer comprises a first photosensitive polymer layer and further comprising: forming a second conductive via through the second substrate, the second conductive via being electrically coupled to the second interconnect and extending through a second surface of the second substrate opposite the first surface; providing a second photosensitive polymer layer on the second surface of the second substrate, a portion of the second conductive via being exposed through the second photosensitive polymer layer; forming a third substrate including a third bonding pad on a first surface of the third substrate; applying the second surface of the second substrate including the second photosensitive polymer layer to the first surface of the third substrate and aligning the third bonding pad of the third substrate with the exposed portion of the second conductive via to electrically couple the second bonding pad to the third bonding pad.
In another embodiment, providing the second photosensitive polymer layer further comprises patterning the second photosensitive polymer layer to expose the portion of the second conductive via.
In another embodiment, the third substrate comprises a substrate selected from the group consisting of: printed circuit board (PCB), semiconductor device substrate, and package interposer.
In another embodiment, the method of claim 16 further comprises: partially curing the first photosensitive polymer layer prior to applying and aligning the first substrate to the second substrate; partially curing the second photosensitive polymer layer prior to applying and aligning the second substrate to the third substrate; and curing the first and second photosensitive polymer layers at the same time following applying and aligning the first substrate to the second substrate and following applying and aligning the second substrate to the third substrate.
In another embodiment, the second photosensitive polymer layer comprises an insulating second photosensitive polymer layer and providing the second photosensitive polymer layer on the second surface of the second substrate comprises: removing substrate material from the second surface of the second substrate to expose a lower end of the second conductive via; providing the insulating second photosensitive polymer layer on the second surface of the second substrate; patterning the insulating second photosensitive polymer layer to expose the lower end of the second conductive via and to cover lower sidewall portions of the second conductive via; and curing the insulating second photosensitive polymer layer.
In another embodiment, the method further comprises: providing an adhesive second photosensitive polymer layer on the insulating second photosensitive polymer layer; partially curing the adhesive second photosensitive polymer layer prior to applying and aligning the second substrate to the third substrate; and curing the adhesive second photosensitive polymer layer following applying and aligning the second substrate to the third substrate.
In another embodiment, the method further comprises patterning the adhesive second photosensitive polymer layer to expose the lower end of the second conductive via.
In another embodiment, forming the first semiconductor device on the first substrate comprises forming multiple first semiconductor devices on a common wafer, each of the multiple first semiconductor devices having a corresponding first interconnect and a corresponding conductive via, and further comprising scribing the multiple first semiconductor devices to separate the multiple first semiconductor devices prior to applying and aligning one of multiple first substrates to each of the second substrates.
In another embodiment, forming the second semiconductor device comprises forming multiple second semiconductor devices on a common wafer, each of the multiple second semiconductor devices having a corresponding second interconnect, and further comprising scribing the multiple second semiconductor devices to separate the multiple second semiconductor devices prior to applying and aligning one of the multiple second substrates to each of the first substrates.
In another embodiment, providing a photosensitive polymer layer on the first surface of the second substrate is performed before scribing the multiple second semiconductor devices.
In another embodiment, the method further comprises partially curing the photosensitive polymer layer prior to applying and aligning the second substrate to the first substrate.
In another embodiment, the method further comprises curing the photosensitive polymer layer following applying and aligning the second substrate to the first substrate.
In another embodiment, forming the first semiconductor device on the first substrate comprises forming multiple first semiconductor devices on a common first wafer, each of the multiple first semiconductor devices having a corresponding first interconnect and a corresponding conductive via, and forming the second semiconductor device comprises forming multiple second semiconductor devices on a common second wafer, each of the multiple second semiconductor devices having a corresponding second interconnect and wherein applying and aligning the second substrate to the first substrate comprises contemporaneously applying and aligning the multiple second semiconductor devices on the second wafer to the multiple first semiconductor devices on the first wafer.
In another embodiment, the method further comprises scribing the first and second wafers to separate the multiple corresponding first and second semiconductor devices following contemporaneously applying and aligning the multiple second semiconductor devices on the second wafer to the multiple first semiconductor devices on the first wafer.
In another embodiment, providing a photosensitive polymer layer on the first surface of the second substrate is performed before scribing the first and second wafers.
In another embodiment, the method further comprises partially curing the photosensitive polymer layer prior to applying and aligning the multiple second semiconductor devices of the second wafer to the multiple first semiconductor devices of the second wafer of the first wafer.
In another embodiment, the method further comprises curing the photosensitive polymer layer following applying and aligning the multiple second semiconductor devices of the second wafer to the multiple first semiconductor devices of the second wafer of the first wafer.
In another embodiment, the photosensitive polymer layer is a material selected from the group consisting of: polymide, poly-benz-oxazole (PBO), benzo-cyclo-butene (BCB), epoxy, novolak, melamine-phenol, acrylate, and elastomer.
In another embodiment, the photosensitive polymer layer includes a photo active component and a bonding agent.
In another embodiment, the photosensitive polymer layer has a first coefficient of thermal expansion that is higher than a second coefficient of thermal expansion of the substrate.
In another embodiment, the first coefficient of thermal expansion of the photosensitive polymer layer being higher than the second coefficient of thermal expansion of the substrate compensates for active devices formed on a top portion of the substrate opposite the photosensitive polymer layer having a third coefficient of thermal expansion that is higher than the second coefficient of thermal expansion of the substrate, to prevent warping of the semiconductor device during subsequent thermal cycles of the semiconductor device.
In another aspect, the present invention is directed to a semiconductor device comprising: a first semiconductor device on a first substrate, the first semiconductor device including a first bonding pad on a first surface of the first substrate in a device region of the first semiconductor device; forming a first interconnect on the first surface of the first substrate, the first interconnect electrically coupled to the first bonding pad; a first conductive via through the first substrate, the conductive via being electrically coupled to the first interconnect and extending through a second surface of the first substrate opposite the first surface; a second substrate including a second bonding pad on a first surface of the second substrate; and a first photosensitive polymer layer between the second surface of the first substrate and the first surface of the second substrate that bonds the first and second substrates, at least one of the second bonding pad and the first conductive via extending through the first photosensitive polymer layer and contacting the other of the second bonding pad and the first conductive via to electrically couple the first bonding pad to the second bonding pad.
In one embodiment, the device further comprises a first insulating layer between the second surface of the first substrate and the first photosensitive polymer layer, the first conductive via extending through the first insulating layer to contact the second bonding pad of the second substrate.
In another embodiment, the first insulating layer covers side walls of a bottom portion of the first conductive via.
In another embodiment, the device further comprises: a second semiconductor device on a third substrate, the second semiconductor device including a third bonding pad on a first surface of the third substrate in a device region of the second semiconductor device; a second interconnect on the first surface of the third substrate, the second interconnect electrically coupled to the third bonding pad; a second conductive via through the third substrate, the second conductive via being electrically coupled to the second interconnect and extending through a second surface of the third substrate opposite the first surface; and a second photosensitive polymer layer between the second surface of the third substrate and the first surface of the first substrate that bonds the third and first substrates, at least one of the first bonding pad and the second conductive via extending through the second photosensitive polymer layer and contacting the other of the first bonding pad and the second conductive via to electrically couple the first bonding pad to the third bonding pad.
In another embodiment, the device further comprises a first insulating layer between the second surface of the first substrate and the first photosensitive polymer layer, the first conductive via extending through the first insulating layer to contact the second bonding pad of the second substrate, and a second insulating layer between the second surface of the third substrate and the second photosensitive polymer layer, the second conductive via extending through the second insulating layer to contact the first bonding pad of the first substrate.
In another embodiment, the first insulating layer covers side walls of a bottom portion of the first conductive via, and wherein the second insulating layer covers side walls of a bottom portion of the second conductive via.
In another embodiment, the first photosensitive polymer layer is patterned to expose a portion of the first conductive via to enable contact with the second bonding pad, and wherein the second photosensitive polymer layer is patterned to expose a portion of the second conductive via to enable contact with the first bonding pad.
In another embodiment, the first interconnect extends across the first surface of the first substrate in a direction toward an outer edge of the first substrate and wherein the second interconnect extends across the first surface of the third substrate in a direction toward an outer edge of the third substrate.
In another embodiment, the first and second conductive vias are positioned in scribe lane regions of the respective first and second semiconductor devices.
In another embodiment, the first and second conductive vias are positioned in device regions of the respective first and second semiconductor devices.
In another embodiment, a distal end and a portion of distal sidewalls of each of the first and second conductive vias extend beyond the second surface of the first substrate and second substrate respectively.
In another embodiment, the first semiconductor device on the first substrate and the second semiconductor device on the third substrate are formed on a common semiconductor wafer.
In another embodiment, the first semiconductor device on the first substrate and the second semiconductor device on the third substrate are formed on separate first and second semiconductor wafers.
In another embodiment, the device further comprises a conductive layer on an upper surface of the first interconnect.
In another embodiment, the second substrate comprises a substrate selected from the group consisting of: printed circuit board (PCB), semiconductor device substrate, and package interposer.
In another embodiment, the first photosensitive polymer layer is a material selected from the group consisting of: polymide, poly-benz-oxazole (PBO), benzo-cyclo-butene (BCB), epoxy, novolak, melamine-phenol, acrylate, and elastomer.
In another embodiment, the first photosensitive polymer layer has a first coefficient of thermal expansion that is higher than a second coefficient of thermal expansion of the first substrate.
In another embodiment, the first coefficient of thermal expansion of the first photosensitive polymer layer being higher than the second coefficient of thermal expansion of the first substrate compensates for active devices formed on a top portion of the first substrate opposite the first photosensitive polymer layer having a third coefficient of thermal expansion that is higher than the second coefficient of thermal expansion of the first substrate, to prevent warping of the semiconductor device during subsequent thermal cycles of the semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGSThe foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. In the drawings and related description, if a first layer is referred to as being “on” another layer, the first layer can be directly on the other layer, or intervening layers may be present. Like numbers refer to like elements throughout the specification.
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In addition, the insulator layer 122 is selected for coefficient of thermal expansion matching (CTE-matching) qualities, to prevent bowing or bending of the wafer 50 during subsequent processing activities. For example, the dielectric layer 54 and the front-end-of-line (FEOL) and back-end-of-line (BEOL) components at a top surface of the substrate 52 have a relatively high CTE parameter value, while the substrate 52 itself has a low CTE value. By selecting the insulator layer 122 at the bottom surface 59 of the substrate to have a relatively high CTE value, the high CTE value of the components and layers at the top surface is offset by the high CTE value of the layer 122 at the bottom surface. Therefore, at a later stage of processing, when the supporting board 120 is removed, warping of the wafer 50 is avoided through proper selection of the insulator layer 122.
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In a manner similar to the formation and dicing of the chips 51 from the common wafer 50, other chips can be formed and diced from another common wafer. For the purpose of the remainder of the present discussion, such other chips are referred to as first chips 21 that are formed and diced from a common first wafer 20, while chips 51 are referred to as second chips 51 that are formed and diced from a common second wafer 50.
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A thermo-compression bonding process can optionally be performed at this time, in order to obtain a full cure, and therefore full adhesion, of the photosensitive polymer adhesive layer 123 between the first chip 21 and the printed circuit board 10. At the same time, electrical bonding between the connecting bumps 36 of the first chip 21 with the conductive pads 125 and chip bonding pads 14 of the printed circuit board 10 occurs as a result of the thermo-compression process. To perform thermo-compression bonding, after the wafers or chips are stacked in a stacked structure, the structure is mounted on a bonder chuck, and the bonder is heated to a pre-determined bonding peak temperature. When the pre-determined temperature is reached, the structure is exposed to the heated environment for a predetermined time period under pressure from the compressive force of a piston. The bonding peak temperature and time period are determined according to the desired extent of curing of the polymer layer and according to the desired flow of the compound of the conductive layers 65. Following the heating stage of the bonding process, the pressure of the piston is released and the stacked structure is cooled. Prior to the thermo-compression process, the photosensitive polymer adhesive layer 123 and neighboring surfaces include dangling bonds. The thermo-compression process operates to connect the dangling bonds and to accelerate the bonding process.
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Additional chips can optionally be stacked on the second and first chips 51, 21, and a thermo-compression process performed following stacking of each chip layer to sequentially bond each layer, as described above. Alternatively, the thermo-compression process can be deferred until all chips are aligned and stacked, and when the chip stacking process is completed, a single thermo-compression bonding process can be performed, in order to obtain a full cure of all photosensitive polymer adhesive layers 122 of each chip 21, 51 simultaneously. At the same time, the electrical bonding between the connecting bumps 36 with the underlying conductive layers 65 or underlying conductive pads 125 occurs as a result of the thermo-compression process.
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Although stacking of two chips, namely first and second chips 21, 51, is shown and described in connection with the above example, the present invention is applicable to stacking of more than two chips. In addition, although the chip stack shown above is applied to a printed circuit board, other types of package bases are equally applicable to the present invention, including, for example, a semiconductor device substrate or a package interposer.
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In a manner similar to the formation and dicing of the chips 51 from the common wafer 50, other chips can be formed and diced from another common wafer, in accordance with the second embodiment described above. For the purpose of the remainder of the present discussion, such other chips are referred to as first chips 21 that are formed and diced from a common first wafer 20, while chips 51 are referred to as second chips 51 that are formed and diced from a common second wafer 50.
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The connecting bumps 36 in the openings 176 of the second chip 51 are aligned with a portion of the conductive interconnects of the first chip 21 and bonded together. During stacking of the second chip 51 on the first chip 21, the photosensitive polymer layer 129 of the second chip 51 completely fills the gap, or space, between the second chip 51 and the first chip 21, and, at the same time, prevents the conductive interconnects 64 of the first chip 21 from contacting the substrate 52 of the second chip 51. A thermo-compression bonding process can optionally be performed at this time, in order to obtain a full cure of the photosensitive polymer layer 123 between the second chip 51 and the first chip 21. At the same time, electrical bonding between the connecting bumps 36 of the second chip 51 with the conductive layer 65 and conductive interconnects 64 of the first chip 21 occurs as a result of the thermo-compression process.
Additional chips can optionally be stacked on the second and first chips 51, 21, and a thermo-compression process performed following stacking of each chip layer, as described above. Alternatively, the thermo-compression process can be deferred until all chips are aligned and stacked, and when the chip stacking process is completed, a single thermo-compression bonding process can be performed, in order to obtain a full cure of all photosensitive polymer adhesive layers 122 of each chip 21, 51 simultaneously. At the same time, the electrical bonding between the connecting bumps 36 with the underlying conductive layers 65 or underlying conductive pads 125 occurs as a result of the thermo-compression process.
Further processing of the resulting chip stack 101 continues, as described above, including formation of an encapsulating material 82 over the chip stack 101. In addition, as described above, although stacking of two chips, namely first and second chips 21, 51 is shown and described in connection with the above example, the present invention is applicable to stacking of more than two chips. In addition, although the chip stack shown above is applied to a printed circuit board, other types of bases are equally applicable to the present invention, including, for example, a semiconductor device substrate or a package interposer.
In the first and second embodiments above, separated chips are individually aligned and stacked on a substrate to form chip stack packages in a manner that is consistent with a chip level bonding configuration. In the following third embodiment, entire wafers including multiple chips, or segments of such wafers including multiple chips, are aligned and stacked, and applied to a substrate, prior to dicing of the chips in a manner that is consistent with a wafer level bonding configuration.
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Additional wafers can optionally be stacked on the second and first wafers 50, 20, and a thermo-compression process performed following stacking of each wafer, as described above. Alternatively, the thermo-compression process can be deferred until all wafers are aligned and stacked, and when the wafer stacking process is completed, a single thermo-compression bonding process can be performed, in order to obtain a full cure of all photosensitive polymer adhesive layers 123 between each wafer 20, 50 simultaneously. At the same time, the electrical bonding between the connecting bumps 36 with the underlying conductive layers 65 or underlying conductive pads 125 of the base substrate or printed circuit board occurs as a result of the thermo-compression process.
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In the present embodiment as described herein, the supporting board 120 remains on the second wafer 50 during the stacking procedure for stacking additional wafers below the second wafer 50 and the supporting board is then removed. In an alternative embodiment, the first wafer 20 can retain the bulk of its base substrate 22 and the second wafer 50 can be applied and bonded to a top surface of the first wafer 20. The supporting board of the second wafer is then removed, and a third wafer and optional subsequent wafers, with supporting boards, are applied and bonded to a top surface of the second wafer 50. The supporting board of the third wafer is then removed.
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In further processing of the chip stack, an encapsulating material 82 can be provided over the chip stacks, as described above.
In the present third embodiment as described, the stacked wafers are fully bonded at each layer application. In alternative embodiments, multiple wafer layers that include a beta-stage adhesive layer can be cured and bonded simultaneously in a common thermo-compression process.
In the third embodiment described above, a wafer level bonding approach is utilized in which multiple wafers are first aligned and bonded, prior to dicing of the chip stacks. In the third embodiment, a dual layered film including an insulating layer 122 and a photosensitive polymer adhesive layer 123 is interposed between wafers for providing insulation and adhesion functions between chip layers. In an optional fourth embodiment, a single photosensitive polymer layer having both adhesive and insulative properties is used to provide for wafer level bonding. The single layer 129 is applied in a manner similar to the process described in
In this manner, the present invention provides for a stacked chip configuration, and manufacturing methods thereof, wherein the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.
While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims
1. A method of manufacturing a semiconductor device comprising:
- forming a first semiconductor device on a first substrate, the first semiconductor device including a first bonding pad on a first surface of the first substrate in a device region of the first semiconductor device;
- forming a first interconnect on the first surface of the first substrate, the first interconnect electrically coupled to the first bonding pad, and forming a conductive via through the first substrate, the conductive via being electrically coupled to the first interconnect and extending through a second surface of the first substrate opposite the first surface;
- forming a second semiconductor device on a second substrate, the second semiconductor device including a second bonding pad on a first surface of the second substrate in a device region of the second semiconductor device;
- forming a second interconnect on the first surface of the second substrate, the second interconnect electrically coupled to the second bonding pad;
- providing a photosensitive polymer layer on the second surface of the first substrate, a portion of the conductive via being exposed through the photosensitive polymer layer; and
- applying the second surface of the first substrate including the photosensitive polymer layer to the first surface of the second substrate and aligning the second interconnect of the second substrate with the exposed portion of the conductive via to electrically couple the first bonding pad to the second bonding pad.
2. The method of claim 1 wherein providing the photosensitive polymer layer further comprises patterning the photosensitive polymer layer to expose the portion of the conductive via.
3. The method of claim 1 wherein the first interconnect extends across the first surface of the first substrate in a direction toward an outer edge of the first substrate and wherein the second interconnect extends across the first surface of the second substrate in a direction toward an outer edge of the second substrate.
4. The method of claim 1 wherein the conductive via is formed in a scribe lane region of the first semiconductor device.
5. The method of claim 1 wherein the conductive via is formed in a device region of the first semiconductor device.
6. The method of claim 1 further comprising partially curing the photosensitive polymer layer prior to applying and aligning the first substrate to the second substrate.
7. The method of claim 6 further comprising curing the photosensitive polymer layer following applying and aligning the first substrate to the second substrate.
8. The method of claim 1 wherein the photosensitive polymer layer comprises an insulating photosensitive polymer layer and wherein providing the photosensitive polymer layer on the second surface of the first substrate comprises:
- removing substrate material from the second surface of the first substrate to expose a lower end of the conductive via;
- providing the insulating photosensitive polymer layer on the second surface of the first substrate;
- patterning the insulating photosensitive polymer layer to expose a lower end of the conductive via and to cover lower sidewall portions of the conductive via; and
- curing the insulating photosensitive polymer layer.
9. The method of claim 8 further comprising:
- providing an adhesive photosensitive polymer layer on the insulating photosensitive polymer layer;
- partially curing the adhesive photosensitive polymer layer prior to applying and aligning the first substrate to the second substrate; and
- curing the adhesive photosensitive polymer layer following applying and aligning the first substrate to the second substrate.
10. The method of claim 9 further comprising patterning the adhesive photosensitive polymer layer to expose the lower end of the conductive via.
11. The method of claim 1 further comprising applying a conductive layer to an upper surface of the second interconnect.
12. The method of claim 1 wherein forming a conductive via through the first substrate comprises:
- forming a via hole in the first substrate that extends through the first surface of the first substrate and partially into the first substrate;
- providing an insulating layer that lines sidewalls of the via hole;
- filling the via hole with conductive material to form the conductive via; and
- removing substrate material from the second surface of the first substrate to expose a lower end of the conductive via.
13. The method of claim 12 wherein removing the substrate material comprises:
- grinding the second surface of the first substrate to remove substrate material; and
- etching the second surface of the first substrate and a portion of the insulating layer to expose the lower end of the conductive via and a lower portion of sidewalls of a lower end of the conductive via.
14. The method of claim 1 wherein the first semiconductor device on the first substrate and the second semiconductor device on the second substrate are formed on a common semiconductor wafer.
15. The method of claim 1 wherein the first semiconductor device on the first substrate and the second semiconductor device on the second substrate are formed on separate first and second semiconductor wafers.
16. The method of claim 1 wherein the conductive via comprises a first conductive via and wherein the photosensitive polymer layer comprises a first photosensitive polymer layer and further comprising:
- forming a second conductive via through the second substrate, the second conductive via being electrically coupled to the second interconnect and extending through a second surface of the second substrate opposite the first surface;
- providing a second photosensitive polymer layer on the second surface of the second substrate, a portion of the second conductive via being exposed through the second photosensitive polymer layer;
- forming a third substrate including a third bonding pad on a first surface of the third substrate;
- applying the second surface of the second substrate including the second photosensitive polymer layer to the first surface of the third substrate and aligning the third bonding pad of the third substrate with the exposed portion of the second conductive via to electrically couple the second bonding pad to the third bonding pad.
17. The method of claim 16 wherein providing the second photosensitive polymer layer further comprises patterning the second photosensitive polymer layer to expose the portion of the second conductive via.
18. The method of claim 16 wherein the third substrate comprises a substrate selected from the group consisting of: printed circuit board (PCB), semiconductor device substrate, and package interposer.
19. The method of claim 16 further comprising:
- partially curing the first photosensitive polymer layer prior to applying and aligning the first substrate to the second substrate;
- partially curing the second photosensitive polymer layer prior to applying and aligning the second substrate to the third substrate; and
- curing the first and second photosensitive polymer layers at the same time following applying and aligning the first substrate to the second substrate and following applying and aligning the second substrate to the third substrate.
20. The method of claim 16 wherein the second photosensitive polymer layer comprises an insulating second photosensitive polymer layer and wherein providing the second photosensitive polymer layer on the second surface of the second substrate comprises:
- removing substrate material from the second surface of the second substrate to expose a lower end of the second conductive via;
- providing the insulating second photosensitive polymer layer on the second surface of the second substrate,
- patterning the insulating second photosensitive polymer layer to expose the lower end of the second conductive via and to cover lower sidewall portions of the second conductive via; and
- curing the insulating second photosensitive polymer layer.
21. The method of claim 20 further comprising:
- providing an adhesive second photosensitive polymer layer on the insulating second photosensitive polymer layer;
- partially curing the adhesive second photosensitive polymer layer prior to applying and aligning the second substrate to the third substrate; and
- curing the adhesive second photosensitive polymer layer following applying and aligning the second substrate to the third substrate.
22. The method of claim 21 further comprising patterning the adhesive second photosensitive polymer layer to expose the lower end of the second conductive via.
23. The method of claim 1 wherein forming the first semiconductor device on the first substrate comprises forming multiple first semiconductor devices on a common wafer, each of the multiple first semiconductor devices having a corresponding first interconnect and a corresponding conductive via, and further comprising scribing the multiple first semiconductor devices to separate the multiple first semiconductor devices prior to applying and aligning one of multiple first substrates to each of the second substrates.
24. The method of claim 23 wherein forming the second semiconductor device comprises forming multiple second semiconductor devices on a common wafer, each of the multiple second semiconductor devices having a corresponding second interconnect, and further comprising scribing the multiple second semiconductor devices to separate the multiple second semiconductor devices prior to applying and aligning one of the multiple second substrates to each of the first substrates.
25. The method of claim 24 wherein providing a photosensitive polymer layer on the first surface of the second substrate is performed before scribing the multiple second semiconductor devices.
26. The method of claim 25 further comprising partially curing the photosensitive polymer layer prior to applying and aligning the second substrate to the first substrate.
27. The method of claim 26 further comprising curing the photosensitive polymer layer following applying and aligning the second substrate to the first substrate.
28. The method of claim 1 wherein forming the first semiconductor device on the first substrate comprises forming multiple first semiconductor devices on a common first wafer, each of the multiple first semiconductor devices having a corresponding first interconnect and a corresponding conductive via, and wherein forming the second semiconductor device comprises forming multiple second semiconductor devices on a common second wafer, each of the multiple second semiconductor devices having a corresponding second interconnect and wherein applying and aligning the second substrate to the first substrate comprises contemporaneously applying and, aligning the multiple second semiconductor devices on the second wafer to the multiple first semiconductor devices on the first wafer.
29. The method of claim 28 further comprising scribing the first and second wafers to separate the multiple corresponding first and second semiconductor devices following contemporaneously applying and aligning the multiple second semiconductor devices on the second wafer to the multiple first semiconductor devices on the first wafer.
30. The method of claim 29 wherein providing a photosensitive polymer layer on the first surface of the second substrate is performed before scribing the first and second wafers.
31. The method of claim 30 further comprising partially curing the photosensitive polymer layer prior to applying and aligning the multiple second semiconductor devices of the second wafer to the multiple first semiconductor devices of the second wafer of the first wafer.
32. The method of claim 31 further comprising curing the photosensitive polymer layer following applying and aligning the multiple second semiconductor devices of the second wafer to the multiple first semiconductor devices of the second wafer of the first wafer.
33. The method of claim 1 wherein the photosensitive polymer layer is a material selected from the group consisting of: polymide, poly-benz-oxazole (PBO), benzo-cyclo-butene (BCB), epoxy, novolak, melamine-phenol, acrylate, and elastomer.
34. The method of claim 1 wherein the photosensitive polymer layer includes a photo active component and a bonding agent.
35. The method of claim 1 wherein the photosensitive polymer layer has a first coefficient of thermal expansion that is higher than a second coefficient of thermal expansion of the substrate.
36. The method of claim 35 wherein the first coefficient of thermal expansion of the photosensitive polymer layer being higher than the second coefficient of thermal expansion of the substrate compensates for active devices formed on a top portion of the substrate opposite the photosensitive polymer layer having a third coefficient of thermal expansion that is higher than the second coefficient of thermal expansion of the substrate, to prevent warping of the semiconductor device during subsequent thermal cycles of the semiconductor device.
37. A semiconductor device comprising:
- a first semiconductor device on a first substrate, the first semiconductor device including a first bonding pad on a first surface of the first substrate in a device region of the first semiconductor device;
- forming a first interconnect on the first surface of the first substrate, the first interconnect electrically coupled to the first bonding pad;
- a first conductive via through the first substrate, the conductive via being electrically coupled to the first interconnect and extending through a second surface of the first substrate opposite the first surface;
- a second substrate including a second bonding pad on a first surface of the second substrate; and
- a first photosensitive polymer layer between the second surface of the first substrate and the first surface of the second substrate that bonds the first and second substrates, at least one of the second bonding pad and the first conductive via extending through the first photosensitive polymer layer and contacting the other of the second bonding pad and the first conductive via to electrically couple the first bonding pad to the second bonding pad.
38. The device of claim 37 further comprising a first insulating layer between the second surface of the first substrate and the first photosensitive polymer layer, the first conductive via extending through the first insulating layer to contact the second bonding pad of the second substrate.
39. The device of claim 38 wherein the first insulating layer covers side walls of a bottom portion of the first conductive via.
40. The device of claim 37 further comprising:
- a second semiconductor device on a third substrate, the second semiconductor device including a third bonding pad on a first surface of the third substrate in a device region of the second semiconductor device;
- a second interconnect on the first surface of the third substrate, the second interconnect electrically coupled to the third bonding pad,
- a second conductive via through the third substrate, the second conductive via being electrically coupled to the second interconnect and extending through a second surface of the third substrate opposite the first surface; and
- a second photosensitive polymer layer between the second surface of the third substrate and the first surface of the first substrate that bonds the third and first substrates, at least one of the first bonding pad and the second conductive via extending through the second photosensitive polymer layer and contacting the other of the first bonding pad and the second conductive via to electrically couple the first bonding pad to the third bonding pad.
41. The device of claim 40 further comprising a first insulating layer between the second surface of the first substrate and the first photosensitive polymer layer, the first conductive via extending through the first insulating layer to contact the second bonding pad of the second substrate, and a second insulating layer between the second surface of the third substrate and the second photosensitive polymer layer, the second conductive via extending through the second insulating layer to contact the first bonding pad of the first substrate.
42. The device of claim 41 wherein the first insulating layer covers side walls of a bottom portion of the first conductive via, and wherein the second insulating layer covers side walls of a bottom portion of the second conductive via.
43. The device of claim 40 wherein the first photosensitive polymer layer is patterned to expose a portion of the first conductive via to enable contact with the second bonding pad, and wherein the second photosensitive polymer layer is patterned to expose a portion of the second conductive via to enable contact with the first bonding pad.
44. The device of claim 40 wherein the first interconnect extends across the first surface of the first substrate in a direction toward an outer edge of the first substrate and wherein the second interconnect extends across the first surface of the third substrate in a direction toward an outer edge of the third substrate.
45. The device of claim 40 wherein the first and second conductive vias are positioned in scribe lane regions of the respective first and second semiconductor devices.
46. The device of claim 40 wherein the first and second conductive vias are positioned in device regions of the respective first and second semiconductor devices.
47. The device of claim 40 wherein a distal end and a portion of distal sidewalls of each of the first and second conductive vias extend beyond the second surface of the first substrate and second substrate respectively.
48. The device of claim 40 wherein the first semiconductor device on the first substrate and the second semiconductor device on the third substrate are formed on a common semiconductor wafer.
49. The device of claim 37 wherein the first semiconductor device on the first substrate and the second semiconductor device on the third substrate are formed on separate first and second semiconductor wafers.
50. The device of claim 37 further comprising a conductive layer on an upper surface of the first interconnect.
51. The device of claim 37 wherein the second substrate comprises a substrate selected from the group consisting of: printed circuit board (PCB), semiconductor device substrate, and package interposer.
52. The device of claim 37 wherein the first photosensitive polymer layer is a material selected from the group consisting of: polymide, poly-benz-oxazole (PBO), benzo-cyclo-butene (BCB), epoxy, novolak, and elastomer.
53. The device of claim 37 wherein the first photosensitive polymer layer has a first coefficient of thermal expansion that is higher than a second coefficient of thermal expansion of the first substrate.
54. The device of claim 53 wherein the first coefficient of thermal expansion of the first photosensitive polymer layer being higher than the second coefficient of thermal expansion of the first substrate compensates for active devices formed on a top portion of the first substrate opposite the first photosensitive polymer layer having a third coefficient of thermal expansion that is higher than the second coefficient of thermal expansion of the first substrate, to prevent warping of the semiconductor device during subsequent thermal cycles of the semiconductor device.
Type: Application
Filed: May 18, 2006
Publication Date: Mar 1, 2007
Applicant:
Inventors: Yong-Chai Kwon (Suwon-City), Kang-Wook Lee (Suwon-City), Keum-Hee Ma (Andong-City), Seong-Il Han (Suwon-City), Dong-Ho Lee (Seongnam-City)
Application Number: 11/436,822
International Classification: H01L 23/48 (20060101);