SIGNAL CONVERTERS WITH MULTIPLE GATE DEVICES
An analog to digital converter including a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width, channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. A digital to analog converter including a plurality of MIGFETs is also provided.
A related, copending application is entitled “Method and Circuit for Multiplying Signals With a Transistor Having More Than One Independent Gate Structure,” by Yang Du et al., application Ser. No. 10/728,621, assigned to Freescale Semiconductor, Inc., and was filed on Dec. 5, 2003.
A related, copending application is entitled “Fully Programmable Phase Locked Loop,” by Hector Sanchez et al., application Ser. No. 11/069,664, assigned to Freescale Semiconductor, Inc., and was filed on Mar. 1, 2005.
A related application is entitled “Voltage Controlled Oscillator with a Multiple Gate Transistor and Method Therefor,” by Sriram Kalpat et al., Attorney Docket No. SC14354TP, assigned to Freescale Semiconductor, Inc. and filed simultaneously herewith.
A related application is entitled “Voltage Controlled Oscillator Having Digitally Controlled Phase Adjustment and Method Therefor,” by Hector Sanchez et al., Attorney Docket No. SC14378TC, assigned to Freescale Semiconductor, Inc. and filed simultaneously herewith.
FIELD OF THE INVENTIONThe present invention relates generally to signal converters, and more particularly to signal converters with multiple gate devices.
RELATED ARTTraditionally, signal converters, such as analog to digital converters (ADCs) and digital to analog converters (DACs) have used resistor banks and comparators to convert an analog signal to a digital signal and vice versa. The use of resistor banks and comparators in such signal converters presents several problems. For example, process variations or thermal effects may result in resistor banks that provide inaccurate voltage division. This is because it is difficult to fabricate high precision resistors in an integrated circuit. Thus, use of traditional resistor banks in signal converters may result in errors in signal conversion.
Furthermore, use of comparators raises the implementation complexity of signal converter circuits. In particular, each comparator may be implemented using approximately 15 transistors. A typical 32 level signal converter, such as an ADC, may then need approximately 480 transistors. Thus, there is a need for signal converters that result in lower errors during signal conversion and are less complex.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTSA signal converter, whether analog to digital or digital to analog, may use multiple independent gate FETs (MIGFETs) with different threshold voltages to provide the conversion. The MIGFETs may have different threshold voltages based preferably on body width and channel length to provide the number of different conversions required. This takes advantage of the relatively linear change in threshold voltage with body width change. Thus many different threshold voltages may be available by altering the body width by the corresponding amounts. This is similarly true for channel length change for MIGFETs. The combination of body width and channel length may make for a large number of different threshold voltages. Threshold voltage may further be adjustable with the second independent gate of the MIGFETs. This may be useful for establishing an offset for the threshold voltages to be calibrated relative to an independently determined reference voltage.
In one aspect, an analog to digital converter comprising a plurality of multiple independent gate field effect transistors (MIGFET) that provide a plurality of digital output signals, is provided. Each MIGFET of the plurality of MIGFETs may have a first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals. Each MIGFET of the plurality of MIGFETs may have a combination of body width and channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs. Each MIGFET may have a second current electrode coupled to a ground terminal.
In another aspect, an analog to digital converter comprising a plurality of FETs that provides a plurality of digital output signals, is provided. Each FET of the plurality FETs may have a first gate for receiving an analog signal and a current electrode for providing a digital output signal of a plurality of the digital output signals. Each FET of the plurality of FETs may have a threshold voltage that is unique among the plurality of FETs.
In yet another aspect, a digital to analog converter comprising a plurality of FETs that provides an analog signal at a summing node is provided. Each FET of the plurality of FETs may have a first gate for receiving a different digital signal from among a plurality of digital signals, and a current electrode coupled to the summing node. Each FET of the plurality of FETs may have a threshold voltage that is unique among the plurality of FETs.
Digital signals need not be linear in relation to the analog input value. By way of example, digital signals may be a logarithmic function, a non-linear function, or any other user-desirable function of the analog input value. Although not shown in
Multiple gate devices 14, 16, 18, and 20 may be implemented using a multiple independent gate field effect transistor (MIGFET), FinFET, or any other suitable multiple gate transistor. Load elements 22, 24, 26, and 28 may be implemented using a resistor, MIGFET, FinFET, or any other suitable transistor. Each of these transistors may be N-channel or P-channel. Further, each of these transistors may be planar or non-planar. In addition, the transistors corresponding to the load elements may have tunable impedances.
The threshold voltage of these multiple gate devices determines which one of these will be turned on when a certain value of the sampled analog signal is applied. In general, when a particular multiple gate device is turned on, the output current increases for that particular multiple gate device. This would result in a first voltage output value corresponding to that multiple gate device, as the increased output current flows through the load element (22, for example). In contrast, when a particular multiple gate device is turned off, the output current decreases substantially for that particular multiple gate device. This would result in a second voltage output value corresponding to that multiple gate device, as the decreased output current flows through the load element (22, for example). A particular multiple gate device may be turned on when the input sampled analog signal value exceeds the threshold voltage of the particular multiple gate device. As shown in
Referring again to
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims
1. An analog to digital converter comprising:
- a plurality of multiple independent gate FETs (MIGFETs) that provides a plurality of digital output signals, wherein
- each MIGFET of the plurality of MIGFETs has a first gate for receiving an analog signal, a second gate for being biased, and a current electrode for providing a digital output signal from among the plurality of the digital output signals; and
- each MIGFET of the plurality of MIGFETs has a combination of body width and channel length that is unique among the plurality of MIGFETs to result in a threshold voltage that is unique among the plurality of MIGFETs.
2. The analog to digital converter of claim 1, wherein the plurality of MIGFETs comprises:
- a first MIGFET having a first body width and a first channel length;
- a second MIGFET having a second body width and a second channel length;
- a third MIGFET having a third body width and a third channel length; and
- a fourth MIGFET having a fourth body width and a fourth channel length.
3. The analog to digital converter of claim 1, wherein each of the MIGFETS of the plurality of MIGFETs is further characterized as having a second current electrode coupled to a ground terminal.
4. The analog to digital converter of claim 1 further comprising a bias circuit coupled to each of the second gates of the plurality of MIGFETs.
5. The analog to digital converter of claim 4, wherein the bias circuit provides a bias voltage that alters the threshold voltage of each of the MIGFETs of the plurality of MIGFETs.
6. The analog to digital converter of claim 5, wherein the bias circuit is further characterized as being programmable.
7. The analog to digital converter of claim 1, wherein the MIGFETs are further characterized as being N channel.
8. An analog to digital converter comprising:
- a plurality of FETs that provides a plurality of digital output signals, wherein the plurality of FETS comprising a plurality of MIGFETs, and wherein
- each FET of the plurality of FETs has a first gate for receiving an analog signal and a current electrode for providing a digital output signal of a plurality of the digital output signals; and
- each FET of the plurality of FETs has a threshold voltage that is unique among the plurality of FETs.
9. (canceled)
10. The analog to digital converter of claim 8, wherein the plurality of MIGFETs have at least four different body widths.
11. The analog to digital converter of claim 10, wherein the plurality of MIGFETs have at least four different channel lengths.
12. The analog to digital converter of claim 11, further comprising a programmable bias circuit, wherein each MIGFET of the plurality of MIGFETs has a second gate coupled to the programmable bias circuit to alter the threshold voltage of each of the MIGFETs of the plurality of MIGFETs.
13. The analog to digital converter of claim 12, further comprising load devices coupled to the current electrodes of the MIGFETs, wherein the load devices comprise MIGFETs that have tunable impedances.
14. A digital to analog converter, comprising:
- a plurality of FETs that provides an analog signal at a summing node, wherein the plurality of FETS comprising a plurality of MIGFETs, and wherein
- each FET of the plurality of FETs has a first gate for receiving a different digital signal from among a plurality of digital signals, and a current electrode coupled to the summing node; and
- each FET of the plurality of FETs has a threshold voltage that is unique among the plurality of FETs.
15. (canceled)
16. The digital to analog converter of claim 14, wherein the plurality of MIGFETs have at least four different body widths.
17. The digital to analog converter of claim 16, wherein the plurality of MIGFETs have at least four different channel lengths.
18. The digital to analog converter of claim 17, wherein each MIGFET of the plurality of MIGFETs has a second gate for being biased to alter the threshold voltage of each of the MIGFETs of the plurality of MIGFETs.
19. The digital to analog converter of claim 18, further comprising a programmable bias circuit coupled to the second gates of the plurality of MIGFETs.
20. The digital to analog converter of claim 14, further comprising a current to voltage converter coupled to the summing node.
Type: Application
Filed: Oct 14, 2005
Publication Date: Apr 19, 2007
Inventors: Mohamed Moosa (Round Rock, TX), Sriram Kalpat (Austin, TX), Leo Mathew (Austin, TX)
Application Number: 11/250,993
International Classification: H03M 1/12 (20060101);