Patents by Inventor Leo Mathew

Leo Mathew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10325876
    Abstract: The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventors: Varughese Mathew, Burton J. Carpenter, Leo M. Higgins, III, Chu-Chung Lee, Tu-Anh N. Tran
  • Patent number: 8643066
    Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Byoung L. Min, James D. Burnett, Leo Mathew
  • Patent number: 8575588
    Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Dharmesh Jawarani, Tushar P. Merchant, Ramachandran Muralidhar
  • Patent number: 8563355
    Abstract: A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: October 22, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Tushar P. Merchant, Ramachandran Muralidhar, Rajesh A. Rao
  • Patent number: 8513066
    Abstract: A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: August 20, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Rode R. Mora
  • Patent number: 8498140
    Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: July 30, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Leo Mathew, Michael Sadd, Vishal P. Trivedi
  • Patent number: 8258035
    Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 4, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
  • Publication number: 20120045866
    Abstract: A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.
    Type: Application
    Filed: November 2, 2011
    Publication date: February 23, 2012
    Applicant: AstroWatt, Inc.
    Inventors: Leo Mathew, Dharmesh Jawarani
  • Publication number: 20120007031
    Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 12, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: LEO MATHEW, DHARMESH JAWARANI, TUSHAR P. MERCHANT, RAMACHANDRAN MURALIDHAR
  • Patent number: 8088657
    Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: January 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
  • Patent number: 8076215
    Abstract: A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: December 13, 2011
    Assignee: AstroWatt, Inc.
    Inventors: Leo Mathew, Dharmesh Jawarani
  • Patent number: 8043888
    Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: October 25, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Dharmesh Jawarani, Tushar P. Merchant, Ramachandran Muralidhar
  • Patent number: 7998822
    Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: August 16, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dharmesh Jawarani, John R. Alvis, Michael G. Harrison, Leo Mathew, John E. Moore, Rode R. Mora
  • Patent number: 7910482
    Abstract: A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 22, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tab A. Stephens, Leo Mathew, Lakshmanna Vishnubholta, Bruce E. White
  • Publication number: 20100329043
    Abstract: Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
    Type: Application
    Filed: October 1, 2008
    Publication date: December 30, 2010
    Applicant: University of Florida Research Foundation, Inc.
    Inventors: Jerry G. Fossum, Leo Mathew, Michael Sadd, Vishal P. Trivedi
  • Patent number: 7829447
    Abstract: Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: November 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Rode R. Mora, Tab A. Stephens, Tien Ying Luo
  • Patent number: 7820491
    Abstract: A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Leo Mathew, Ramachandran Muralidhar, Bruce E. White
  • Patent number: 7817387
    Abstract: An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: October 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael G. Khazhinsky, Leo Mathew, James W. Miller
  • Patent number: 7811889
    Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal P. Trivedi, Leo Mathew
  • Patent number: 7803670
    Abstract: A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ted R. White, Leo Mathew, Bich-Yen Nguyen, Zhonghai Shi, Voon-Yew Thean, Mariam G. Sadaka