Hardware device for genetic algorithms
A hardware device is for performing crossover and mutation operations based upon a genetic algorithm. The hardware device may include a random or pseudo-random number generator, and a crossover block, conditioned with a random crossover index, for generating output crossover bit-strings from current bit-strings. The device may also include a mutation block, conditioned with a random mutation index, for generating output bit-strings by switching at least one bit of each input bit-string pointed to by the mutation index. A memory may temporarily store the current bit-strings and the output bit-strings. In addition, the hardware device may include a control unit, interfaced with the random number generator, the crossover block, the mutation block and the memory and managing their functioning by generating respective control signals therefor.
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This invention relates to a hardware device for performing via hardware the crossover and mutation operations of a genetic algorithm over a set of bit-strings representing the “population” of “individuals” to be processed.
BACKGROUND OF THE INVENTIONGenetic algorithms (or, more briefly, GAs) are global search and optimization algorithms based on the principles of natural selection. The GAs operate on a set (a “population”) of “individuals”, generally composed of strings of bits, and generate a new “population of individuals” by performing the operations of selection, crossover and mutation on the current “population”.
The steps of a genetic algorithm are now briefly illustrated referring to a practical case, for better clarifying the field of this invention.
Let us consider the problem of maximizing the output of a device by switching an array of five input switches. For each configuration “s” of the switches, the device generates a certain output signal F(s). The objective to be reached includes finding a configuration of switches for which the output signal is maximized.
This optimization problem may be solved with a genetic algorithm by encoding each configuration with a string of five bits, wherein an active bit (1) represents a switch in a conduction state, while a null bit (0) represents an off switch. For example, the bit-string 11110 represents a configuration in which four switches of the array are on, while the fifth switch is off.
The first step includes choosing an initial “population” of “individuals”, that is an initial set of bit-strings, such as for instance the set composed of the following bit strings:
As an alternative, the individuals may be integer numbers ranging from 0 to 31 corresponding to strings of five bits.
It is worth noticing that a set of independent variables can be encoded in a bit-string, even if they are not binary, by encoding each variable with a corresponding bit-string and merging all the bit-strings of the parameters in a single bit-string, as schematically shown in
Starting from a “population”, for each “individual” a fitness value is calculated, that determining the probability of reproducing the same “individual” in the next generation. In practice, “individuals” with a larger fitness value have a larger probability of being present in the next “population”.
Let us suppose that the fitness function be given by the following equation:
F(s)=s2
Therefore, the four above mentioned bit strings are associated to the following fitness values and probabilities:
Once a new group of individuals is generated according to the above probabilities, the new strings are generated with the crossover operation. In practice, two “sons” bit-strings are generated by exchanging a random portion of two “parents” bit-strings. This is done as illustrated in the following table:
In the above case the two least significant bits are exchanged, but it is possible to exchange any number of bits, such as the least and the most significant bits, or the first two (or even more than two) most significant bits, and so on.
A new “population” is obtained by applying the mutation operator over the set of “son” strings. The mutation operator may change randomly any bit of any “son” string with a certain probability.
This last operator is important because, using only the crossover and the selection operators, there could be bit-strings that would never be generated. A too large mutation probability could make the genetic algorithm never converge towards a solution, while a too small mutation probability could make the GA converge to local minima (or maxima) and not to global minima (maxima).
The fitness values for individuals of the generated population are calculated and, if a stop condition is verified, the algorithm is stopped and a result is output.
Genetic algorithms are very powerful tools for controlling the evolution of systems, especially of systems the time evolution of which cannot be formulated analytically. Indeed, the main advantage in using genetic algorithms is that it is not necessary to know analytical formulas describing the evolution of a system for implementing them.
Typically, genetic algorithms are performed using a software executed by a computer. Unfortunately, for complex systems it is necessary to carry out many operations for implementing a control method based on GAs. As a consequence, software implemented control methods based upon GAs are relatively slow and cannot be used for controlling systems evolving with relatively fast dynamics.
U.S. Pat. No. 5,971,579 discloses a method for determining gains of a PID (Proportional, Integral, Differential) controller using a specifically designed genetic algorithm. The unit disclosed therein uses a Random Number Generator including an analog amplifier for amplifying an input noise and of a block that converts the amplitude of the noise in a corresponding bit-string.
SUMMARY OF THE INVENTIONThe present invention is directed to a hardware device for performing the crossover and mutation operations of any genetic algorithm at an outstandingly high speed. The device preferably comprises programmable logic gates, that generate a result much faster than a microprocessor running software.
The hardware device receives input bit-strings representing “individuals” of a “population” to be processed and the multiplicity of each “individual” in the “population”. Then it obtains an initial population to be processed by storing in an internal memory as many replicas of the bit-string representing a same individual as the multiplicity thereof. The crossover and mutation operators are applied to these bit-strings representing the initial “population” for generating a new set of bit-strings representing a new “population of individuals”.
The bit-strings of the generated “population” are transmitted to an external fitness calculation system that calculates the fitness value associated to each “individual” and the multiplicity thereof in the next “population”.
In practice, the selection operation is in part performed by this external system, which calculates the fitness of each individual and calculates the multiplicity thereof, and in part by the hardware device, that generates an initial “population” by replicating each “individual” by the multiplicity thereof.
Preferably, the external fitness calculation system is a personal computer (PC) that executes a software code.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention is described referring to the attached drawings, wherein:
FIGS. 21 to 24 are state diagrams that illustrate the functioning of the control block of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTSThe hardware device of this invention for carrying out genetic algorithms will be described supposing that the variables to be optimized are four, such as the parameters of a PID regulator. Further, it is supposed that each “population” includes only 128 “individuals”, each identified by 8 bytes. Obviously, what will be stated hereinafter holds, mutatis mutandis, also if there are more than four variables to be controlled, or if there are more than 128 “individuals” in each “population”, or if each bit-strings includes more than 8 bytes.
A scheme of the hardware device of this invention that carries out a genetic algorithm for optimizing the values of the four parameters of a PID regulator is shown in
This hardware is interfaced with an external fitness calculation system, which is typically a Personal Computer (PC), that calculates the fitness value of each “individual” and its multiplicity. Then the PC transmits each individual with its multiplicity to the hardware device.
Parallel_Interface
This block is a parallel interface for connecting the hardware device with the external system that calculates the fitness values (PC). It receives 80 bits words—each representing an “individual” with its multiplicity—sent by the fitness calculation system preferably byte per byte, through a parallel port, and that are successively stored in the DPRAM. The interface is shown in
The fitness calculation system sends to the hardware architecture a certain number of “individuals”, the number of copies of each of them and the respective fitness value. The parallel interface shown in
When data are sent to or from the interface, a control flag control_INTERFACE is switched active, as shown in
Let us suppose that data are to be sent from the fitness calculation system to the hardware architecture of this invention. One byte of data is sent on the bus dataIN(7:0), then the flag control_INTERFACE switches high and the flag RW switches null for signaling that data are being read from the fitness calculation system. When the hardware acquires the byte, the flag status_INTERFACE switches high and for acknowledging that a byte has been read.
When the fitness calculation system receives a logically high flag status_INTERFACE, it switches low the flag control_INTERFACE and sends another byte on the bus DIN(7:0). In the meanwhile, the hardware architecture of this invention switches low the flag status_INTERFACE and is ready to read another byte.
The same procedure takes place when data are being sent from the hardware to the fitness calculation system.
According to a preferred embodiment, the parallel interface communicates with the fitness calculation system through a tristate output buffer, such as the one shown in
A block diagram that describes the functioning of the finite state machine, that receives data from the fitness calculation system (PC), is shown in
As far as the flag control_INTERFACE is logically null, the finite state machine remains idle. When this flag switches high and the flag RW is null (control_INTERFACE=‘1’ & control_RW=‘0’), one byte at the time is written in the bus
When a byte is in the bus
The bytes transferred through the bus DATABUS are counted (
When the flag status_INTERFACE switches low again, the bits of another “individual” are sent to the interface.
A block diagram that illustrates the sequence of steps to be performed for transferring a bit-string from the interface to the external fitness calculation system (PC) is shown in
A full bit-string (80 bits in the considered case) of an “individual” is read (R
Evidently, the parallel interface may assume one of six states, namely I
DPRAM
The internal memory of the hardware architecture is preferably organized as shown in
The DPRAM (Dual Port RAM) is depicted in
The block RNG, shown in
The output of this block is a random variable that is used for choosing the number of bits of “individuals” that are involved in the crossover operation, the pair of individuals for performing the crossover operation, for choosing the bit (or bits) of “individuals” that will be subject to the mutation operation and the probability with which this bit (or bits) is to be inverted.
Many pseudo-random bit generators use the following recursive formula:
xn+1=(A1xn+A2)mod N (1)
wherein A1, A2 and N are pre-established parameters fixed by the user, together with the seed x0 of the sequence, xn is the present output and xn+1 is the next output. For instance, if x0=79, A1=273, A2=71 and N=100, the “present value—next value” map depicted in
Evidently, the maps represented in
It has been noticed that, by using the same parameters A1, A2, N of the map of
According to an aspect of the invention, a sequence of pseudo-random numbers is generated by using the recursive formula (1) and by changing the seed of the sequence when a certain number of iterations have been carried out.
According to an embodiment, the seed of each pseudo-random sequence may be generated with a Free Running Timer (FRT), which may be a 31 bit counter (if the number N equals 2147483647).
The value of A1 is 16807 and it is encoded with a bit-string of 15 bits. At most 31 bits are needed for encoding a value xn, because N=2147483647. Therefore, the result of the multiplication A1xn modulo N is simply obtained by considering only the 31 least significant bits of the multiplication A1xn.
The number of selected bits of output random bit-strings RNG is seven when a random address is to be generated, while it is six when random crossover or mutation indexes (defined hereinafter) are to be generated.
Preferably, not the same group of bits of the generated random bit-strings are considered for obtaining the random addresses and random indexes. For this reason, the block RNG includes a logic circuit (not depicted) that selects from time to time a different group bits of interest, preferably according to a circular order. This means that, for example, a first random address could be provided by the 7 least significant bits, then a second address could include the bits from the eighth least significant to the bit before the last significant bit, and so on as far as the seven most significant bits are selected. Then the successive address could include the least significant bit followed by the six most significant bits, and so on.
XOVER
The crossover block XOVER, shown in
The crossover index P(5:0) indicates the group of bits to be exchanged between two “parent” bit strings. In practice, according to the preferred embodiment, only a group of least significant bits are exchanged, and P is the pointer to the most significant bit of this group of bits.
The group of bits of the “individuals” to which the crossover is to be performed are randomly determined by the RNG block, and are provided to the circuit block CORE. The crossover operation is schematically exemplified in
The flag
More in detail, the crossover operation starts in correspondence with the leading edge of the flag
By contrast, if P is non null, the following steps are performed:
the whole input bit-string chroml(63:0) is copied into a temporary register of the crossover block (state C
all bits from P-1 down to 0 of the input bit-string chrom2(63:0) are written in order in the temporary register over the previously stored bits for generating the first output bit-string chrom1_out(63:0) (operation
all bits from 63 down to P of the input bit-string chrom1(63:0) are written in order in the temporary register over the previously stored bits for generating the second output bit-string chrom2_out(63:0) (operation
when the operation
Mutation
The block MUTATION depicted in
The output bit-string chrom_MUT_OUT is generated by switching a bit, of the input bit-string chrom_MUT_IN, the position of which is pointed to by the mutation index column_MUT (generated by the block RNG) according to the scheme of
The functioning of the block MUTATION is illustrated in
CORE
The control block CORE manages all other circuit blocks included in the hardware architecture of the illustrated embodiment. It is shown in
This control block is substantially a state machine that performs the operations illustrated in the flow charts of FIGS. 21 to 24. As shown in
The first operation to be performed by the control block CORE is the selection operation, that is started by switching active the command ctrl_START_GENETIC.
The steps to be carried out for managing the execution of the selection operation are shown in
The bits of the “individuals” to be copied are read in a first half portion (through the port A) of the DPRAM, while they are written in the other half portion (through port B). Two internal registers address_R and address_W (not shown in
As stated hereinafter, a portion of this string identifies an “individual” while the remaining portion identifies the number of copies N_copies to be made of this “individual”. If the number of copies is null, the “individuals” shall not be reproduced, thus the address address_R is incremented and a new string is read from the DPRAM. If the number of copies is non null, the “individual” is to be replicated (state R
If the control block CORE is in the state R
By contrast, if N copies is null, as it may happen when returning from the state REPLICATION to the state A
address_W<255: the selection operation is not yet completed, thus the CORE enters the state A
address_W=255: the selection operation is ended and the state R
In the state ADDRESS_W the number of copies to be generated is decremented and the writing address is increased. Indeed, a copy of the current “individual” has been already carried out in the state R
In the state A
The flow chart of the steps performed by the CORE during the crossover operation is depicted in
The state R
As highlighted above while describing the replication operation, the 16 least significant bits (that encode the number of copies) are reset, for using at least a bit F
The state A
if the internal signal F
if the signal F
if the signal F
In the first two cases it is necessary to enable a memory write operation for updating the internal signals FLAG of each “individual”, to increment the counting CONT of an internal counter, to verify whether this counting is smaller than two (
In the state U
the signal F
the second flag is updated, thus all data to be input to the block XOVER are stored in the three internal temporary registers ADDRESS_1, ADDRESS_2 and P: in this case the signal
In the state A
Then the state W
A flow chart that describes the steps to be performed by the CORE during a mutation operation is shown in
When the crossover is ended (end_CROSSOVER), the CORE enters the state R
When the state
The next state W
Then the state E
To prevent that the signal ctrl_START_GENETIC remains active and begins a new cycle of the genetic algorithm before the DPRAM has been read, the CORE waits that the signal CONTROL, that is forced by the fitness calculation system after having detected the leading edge of the signal status_END_GENETIC switches null. Then, also the signal status_END_GENETIC is switched low and the CORE returns into the state I
Claims
1. A hardware device for generating an output set of bit-strings by performing crossover and mutation operations of a genetic algorithm on a current set of bit-strings, comprising:
- a random or pseudo-random number generator;
- a crossover block, conditioned with a random crossover index, and to which a pair of bit-strings of the current set of bit-strings are fed for generating a corresponding output pair of crossover bit-strings;
- a mutation block, conditioned with a random mutation index, and to which an input bit-string to be mutated is fed for generating a corresponding bit-string of an output set of bit-strings by switching a bit of the input bit-string pointed to by the mutation index;
- a memory for temporarily storing bit-strings of the current set of bit-strings and of the output set of bit-strings;
- an output bus; and
- a control unit, interfaced with said crossover block, said mutation block and said memory and managing their functioning by generating respective control signals, said control unit being input with random numbers generated by said random number generator and generating the random crossover index and random mutation index, with bit-strings of the current set with their respective multiplicity, sending the bit-strings of the current set to the crossover block together with the random crossover index, receiving from the crossover block its output crossover bit-strings and sending them together with a respective mutation index to said mutation block, and receiving the bit-strings of the output set generated by said mutation block, and making them available on said output bus.
2. The hardware device according to claim 1 further comprising a parallel interface controlled by said control unit, and being input with bit-strings of the current set and their respective multiplicity for transferring them to said control unit, and receiving from said control unit bit-strings of the new set.
3. The hardware device according to claim 1 wherein said pseudo-random number generator comprises:
- a multiplier being input with a bit-string representing a seed or a previously generated pseudo-random number and a constant fixed bit-string, and generating a new pseudo-random bit-string including a fixed number of least significant bits of a product of the input bit-string by the constant fixed bit-string; and
- a free running timer generating seeds for said multiplier at time intervals.
4. The hardware device according to claim 1 wherein said memory comprises a dual port random access memory including a first port being dedicated for receiving/sending bit-strings of the current set and a second port being dedicated for receiving/sending bit-strings of the output set.
5. A hardware device for performing crossover and mutation operations based upon a genetic algorithm comprising:
- a random or pseudo-random number generator;
- a crossover block, conditioned with a random crossover index, for generating output crossover bit-strings from current bit-strings;
- a mutation block, conditioned with a random mutation index, for generating output bit-strings by switching at least one bit of each input bit-string pointed to by the mutation index;
- a memory for temporarily storing the current bit-strings and the output bit-strings; and
- a control unit, interfaced with said random number generator, said crossover block, said mutation block and said memory and managing their functioning by generating respective control signals therefor.
6. The hardware device according to claim 5 further comprising a parallel interface controlled by said control unit.
7. The hardware device according to claim 5 wherein said pseudo-random number generator comprises:
- a multiplier being input with a bit-string representing a seed or a previously generated pseudo-random number and a constant fixed bit-string, and generating a new pseudo-random bit-string including a fixed number of least significant bits of a product of the input bit-string by the constant fixed bit-string; and
- a free running timer generating seeds for said multiplier at time intervals.
8. The hardware device according to claim 5 wherein said memory comprises a dual port random access memory including a first port being dedicated for receiving/sending bit-strings of the current bit strings and a second port being dedicated for receiving/sending output bit-strings.
9. A proportional, integral, derivative (PID) controller comprising:
- a hardware device for determining at least one PID controller gain based upon performing crossover and mutation operations based upon a genetic algorithm comprising a random or pseudo-random number generator, a crossover block, conditioned with a random crossover index, for generating output crossover bit-strings from current bit-strings, a mutation block, conditioned with a random mutation index, for generating output bit-strings by switching at least one bit of each input bit-string pointed to by the mutation index, a memory for temporarily storing the current bit-strings and the output bit-strings, and a control unit, interfaced with said random number generator, said crossover block, said mutation block and said memory for managing their functioning by generating respective control signals therefor.
10. The PID controller according to claim 9 further comprising a parallel interface controlled by said control unit.
11. The PID controller according to claim 9 wherein said pseudo-random number generator comprises:
- a multiplier being input with a bit-string representing a seed or a previously generated pseudo-random number and a constant fixed bit-string, and generating a new pseudo-random bit-string including a fixed number of least significant bits of a product of the input bit-string by the constant fixed bit-string; and
- a free running timer generating seeds for said multiplier at time intervals.
12. The PID controller according to claim 9 wherein said memory comprises a dual port random access memory including a first port being dedicated for receiving/sending bit-strings of the current bit strings and a second port being dedicated for receiving/sending output bit-strings.
13. A method for performing crossover and mutation operations based upon a genetic algorithm and in a hardware device, the method comprising:
- operating a random or pseudo-random number generator of the hardware device;
- generating output crossover bit-strings from current bit-strings using a crossover block of the hardware device conditioned with a random crossover index;
- generating output bit-strings by switching at least one bit of each input bit-string pointed to by a mutation index using a mutation block of the hardware device;
- temporarily storing in a memory of the hardware device current bit-strings and the output bit-strings; and
- generating respective control signals for the random number generator, the crossover block, the mutation block and the memory using a control unit of the hardware device.
14. The method according to claim 13 further comprising a parallel interface controlled by the control unit.
15. The method according to claim 13 wherein the pseudo-random number generator comprises:
- a multiplier being input with a bit-string representing a seed or a previously generated pseudo-random number and a constant fixed bit-string, and generating a new pseudo-random bit-string including a fixed number of least significant bits of a product of the input bit-string by the constant fixed bit-string; and
- a free running timer generating seeds for the multiplier at time intervals.
16. The method according to claim 13 wherein the memory comprises a dual port random access memory including a first port being dedicated for receiving/sending bit-strings of the current bit strings and a second port being dedicated for receiving/sending output bit-strings.
Type: Application
Filed: Jul 27, 2005
Publication Date: Apr 26, 2007
Applicant: STMicroelectronics S.r.l. (Agrate Brianza (MI))
Inventors: Antonino Calabro (Ficarazzi di Aci Castello), Federico Rivoli (Messina), Fabio Tripodi (Villa San Giovanni)
Application Number: 11/190,744
International Classification: G06N 3/12 (20060101);