Abstract: Various embodiments provide a device for measuring the flow of fluid inside a tube moved by a peristaltic pump is provided with: a detection electrode arrangement coupled to the tube to detect an electrostatic charge variation originated by the mechanical action of the peristaltic pump on the tube; a signal processing stage, electrically coupled to the detection electrode arrangement to generate an electrical charge variation signal; and a processing unit, coupled to the signal processing stage to receive and process in the frequency domain the electrical charge variation signal to obtain information on the flow of a fluid that flows through the tube based on the analysis of frequency characteristics of the electrical charge variation signal.

Abstract: An electro-acoustical transducer such as a Piezoelectric Micromachined Ultrasonic Transducers is coupled with an adjustable load circuit having a set of adjustable load parameters including resistance and inductance parameters. Starting from at least one resonance frequency or at least one ring-down parameter of the electro-acoustical transducer a set of model parameters is calculated for a Butterworth-Van Dyke (BVD) model of the electro-acoustical transducer. The BVD model includes an equivalent circuit network having a constant capacitance coupled to a RLC branch and the adjustable load circuit is coupled with the electro-acoustical transducer at an input port of the equivalent circuit network of the model of the electro-acoustical transducer. The adjustable load parameters are adjusted as a function of the set of model parameters calculated for the BVD model of the electro-acoustic transducer to increase the bandwidth or the sensitivity of the electro-acoustic transducer.

Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.

Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

Abstract: A method for method of setting up a processing system includes determining availability of user-provided platform information indicative of a first memory platform out of a plurality of memory platforms. In response to determining that the user-provided platform information is available at the first memory platform, a boot loader code is read from the first memory platform. In response to determining that the user-provided platform information is not available, test availability of the boot loader code in another memory platform of the plurality of memory platforms, and read the boot loader code from the another memory platform upon testing the availability of the boot loader code in the another memory platform.

Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Abstract: A MEMS device is formed in a die of semiconductor material having a cavity defined therein and having an anchorage portion. A tiltable structure is elastically suspended over the cavity and has a main extension in a horizontal plane. First and second supporting arms extend between the anchorage portion and opposite sides of the tiltable structure. First and second resonant piezoelectric actuation structures are intended to be biased to thereby cause rotation of the tiltable structure about a rotation axis. The first supporting arm is formed by first and second torsion springs, which are rigid to movements out of the horizontal plane and compliant to torsion about the rotation axis and are coupled together at a constraint region. The first and second resonant piezoelectric actuation structures extend between the anchorage portion and the constraint structure, on first and second sides of the first supporting arm.

Abstract: A PWM controlled multi-phase resonant voltage converter may include a plurality of primary windings powered through respective half-bridges, and as many secondary windings connected to an output terminal of the converter and magnetically coupled to the respective primary windings. The primary or secondary windings may be connected such that a real or virtual neutral point is floating.

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: ? ? i ? [ 1 ; N ] ? { r ? ( l ) = ? j = 1 K ? A ? ( i , j ) * p ? ( j ) R ? ( i ) = ? j = 1 K ? A ? ( i , j ) * P ? ( j ) , wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.

Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal is applied to the sensing capacitor during a reset phase of a sensing circuit coupled to the sensing capacitor. The test signal is configured to cause an electrostatic force which produces a physical displacement of the mobile mass corresponding to a desired acceleration value. Then, during a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the physical displacement of the mobile mass is sensed. This sensed variation in capacitance is converted to a sensed acceleration value. A comparison of the sensed acceleration value to the desired acceleration value provides an indication of an error in operation of the MEMS accelerometer sensor if the sensed acceleration value and desired acceleration value are not substantially equal.

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.

Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

Abstract: Various embodiments provide an ejection device for a fluid. The ejection device includes a first semiconductor wafer, housing, on a first side thereof, a piezoelectric actuator and an outlet channel for the fluid alongside the piezoelectric actuator; a second semiconductor wafer having, on a first side thereof, a recess and, on a second side thereof opposite to the first side, at least one inlet channel for said fluid fluidically coupled to the recess; and a dry-film coupled to a second side, opposite to the first side, of the first wafer. The first and the second wafers are coupled together so that the piezoelectric actuator and the outlet channel are set directly facing, and completely contained in, the recess that forms a reservoir for the fluid. The dry-film has an ejection nozzle.

Abstract: A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer.

Abstract: A method can be used for the generation of personalized Profile Package data in integrate circuit cards. A table includes data records corresponding to subscriptions to be generated. Each record includes personalization fields to store different types of personalization values. For a given subscription, a file for the Profile Package is in an ASCII format and includes fields to be personalized corresponding to one or more of the fields to store different types of personalization values. The file for the Profile Package in the ASCII format is converted into a hexadecimal code. An offset table is calculated for the given subscription indicating for each field to be personalized a corresponding offset in the hexadecimal profile. The personalization values from the personalization fields are substituted in the corresponding personalization fields to be personalized.

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.