Patents Assigned to STMicroelectronics S.r.l.
  • Publication number: 20240240945
    Abstract: A driving circuit is implemented for a driving resonator stage of a MEMS gyroscope including at least a first and a second electrode and a movable mass The driving circuit includes a synchronization stage which receives an electrical position signal indicative of the position of the movable mass and generates a reference signal phase- and frequency-locked with the electrical position signal; a driving stage which generates, on the basis of the reference signal, a first and a second driving signal, which are applied to the first and, respectively, the second electrodes, so that the movable mass is subject to a first and a second electrostatic force which cause the movable mass to oscillate.
    Type: Application
    Filed: January 3, 2024
    Publication date: July 18, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Gabriele GATTERE, Marco GARBARINO
  • Publication number: 20240243739
    Abstract: A half-bridge driver circuit is provided. The circuit includes a detector circuit that generates a signal indicating whether a floating reference voltage is greater than a second supply voltage. The detector circuit includes a first circuit, a second circuit and combinational logic circuit. A first comparator circuit of the first circuit monitors a voltage drop at a resistance and sets a first control signal to a first logic level when the monitored voltage drop is smaller than a first threshold. A second comparator circuit of the second circuit monitors a current provided by an output transistor of a current mirror and sets a second control signal to a first logic level when the monitored current is greater than a second threshold. The combinational logic circuit asserts the signal when the first control signal has the respective first logic level or the second control signal has the respective first logic level.
    Type: Application
    Filed: January 9, 2024
    Publication date: July 18, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventor: Marco Giovanni FONTANA
  • Publication number: 20240239648
    Abstract: The MEMS device has: a sensor body having a functional structure configured to transduce a physical or chemical quantity into a corresponding electrical quantity; and a cap bonded to the sensor body and having a first cavity overlying the functional structure. The cap has a supporting portion and a cover portion that form the first cavity. The supporting portion is bonded to the sensor body. The cover portion is bonded to the supporting portion and has an inner wall delimiting on a side the first cavity and facing the functional structure. The MEMS device further has a first coating that extends within the first cavity on the inner wall of the cover portion.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 18, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Silvia NICOLI, Lorenzo TENTORI, Giuseppe BRUNO
  • Publication number: 20240243122
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 18, 2024
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe SAGGIO, Simone RASCUNÁ
  • Publication number: 20240244406
    Abstract: In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 18, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC.
    Inventors: Karimuddin SAYED, Chandandeep Singh PABLA, Lorenzo BRACCO, Federico RIZZARDINI
  • Patent number: 12038471
    Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mirko Dondini, Roberto Crisafulli, Calogero Andrea Trecarichi, Vincenzo Randazzo
  • Patent number: 12040263
    Abstract: A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Roberto Tiziani
  • Patent number: 12038454
    Abstract: A MEMS inertial sensor includes a supporting structure and an inertial structure. The inertial structure includes at least one inertial mass, an elastic structure, and a stopper structure. The elastic structure is mechanically coupled to the inertial mass and to the supporting structure so as to enable a movement of the inertial mass in a direction parallel to a first direction, when the supporting structure is subjected to an acceleration parallel to the first direction. The stopper structure is fixed with respect to the supporting structure and includes at least one primary stopper element and one secondary stopper element. If the acceleration exceeds a first threshold value, the inertial mass abuts against the primary stopper element and subsequently rotates about an axis of rotation defined by the primary stopper element. If the acceleration exceeds a second threshold value, rotation of the inertial mass terminates when the inertial mass abuts against the secondary stopper element.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Rizzini, Gabriele Gattere, Sarah Zerbini
  • Patent number: 12038283
    Abstract: A frequency modulation MEMS triaxial gyroscope, having two mobile masses; a first and a second driving body coupled to the mobile masses through elastic elements rigid in a first direction and compliant in a second direction transverse to the first direction; and a third and a fourth driving body coupled to the mobile masses through elastic elements rigid in the second direction and compliant in the first direction. A first and a second driving element are coupled to the first and second driving bodies for causing the mobile masses to translate in the first direction in phase opposition. A third and a fourth driving element are coupled to the third and fourth driving bodies for causing the mobile masses to translate in the second direction and in phase opposition. An out-of-plane driving element is coupled to the first and second mobile masses for causing a translation in a third direction, in phase opposition.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: July 16, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alessandro Tocchio, Luca Giuseppe Falorni, Claudia Comi, Valentina Zega
  • Patent number: 12040722
    Abstract: In an embodiment, a method for controlling a synchronous rectifier (SR) transistor of a flyback converter includes: determining a first voltage across conduction terminals of the SR transistor; asserting a turn-on signal when a body diode of the SR transistor is conducting current; asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold; generating a gating signal based on an output voltage of the flyback converter and on the first voltage; turning on the SR transistor based on the turn-on signal and on the gating signal; and turning off the SR transistor based on the turn-off signal.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: July 16, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Claudio Adragna
  • Patent number: 12038799
    Abstract: A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: July 16, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Luigi Sole, Rossella Gaudiano, Marta Cantarini, Nicola Errico, Antonio Giordano
  • Patent number: 12037158
    Abstract: Tray for containing electronic components formed by a bearing body, substantially planar, having a first and a second face. First holding structures extend from the first face of the bearing body and second holding structures extend from the second face of the bearing body. Each second holding structure is aligned with a respective first holding structure in a vertical direction perpendicular to the first and the second faces of the bearing body. Each first holding structure is formed by first protrusions mutually spaced by first spaces and arranged along a first closed line; each second holding structure is formed by second protrusions mutually spaced by second spaces and arranged along a second closed line. Each second protrusion is aligned, in parallel with the vertical direction, with the first spaces and each first protrusion is aligned, in parallel with the vertical direction, with the second spaces.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: July 16, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Massimiliano Pesaturo, Massimo Greppi
  • Publication number: 20240230596
    Abstract: An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.
    Type: Application
    Filed: October 18, 2023
    Publication date: July 11, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Domenico GIUSTI, Marco DEL SARTO, Fabio QUAGLIA, Enri DUQI
  • Publication number: 20240234263
    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
    Type: Application
    Filed: October 24, 2023
    Publication date: July 11, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio RUSSO
  • Patent number: 12032460
    Abstract: A method to test an asynchronous finite state machine for faults, the method including disabling state transitions out of a state of the asynchronous finite state machine and inputting test data to the AFSM to trigger a transition from the state to an expected state. The method further including enabling transitions out of the state of the asynchronous finite state machine, and determining whether the asynchronous finite state machine has performed a successful transition to the expected state.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: July 9, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enea Dimroci, Francesca Giacoma Mignemi, Roberta Priolo, Marco Leo, Francesco Battini
  • Patent number: 12033663
    Abstract: A circuit includes a set of input nodes configured to be coupled to respective ones of the windings of a spindle motor in a hard disk drive to sense the voltages applied to the windings. A set of output nodes is configured to provide output signals indicative of direction of flow of the currents through the windings. Level shifters are coupled to respective input nodes in the set of input nodes and have level-shifted output nodes configured to provide down-shifted replicas of the voltages at the respective input nodes in the set of input nodes. Flip-flops have inputs coupled to respective ones of the level-shifted output nodes of the level shifters and outputs configured to provide the output signals coupled to respective output nodes.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: July 9, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Ezio Galbiati
  • Patent number: 12033926
    Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: July 9, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20240222424
    Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
    Type: Application
    Filed: September 8, 2023
    Publication date: July 4, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Angelo MAGRI', Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20240220278
    Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task.
    Type: Application
    Filed: February 28, 2023
    Publication date: July 4, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Paolo Sergio ZAMBOTTI, Thomas BOESCH, Giuseppe DESOLI, Wolfgang Johann BETZ, David SIORPAES
  • Publication number: 20240220777
    Abstract: A hardware accelerator includes functional circuits and streaming engines. An interface is coupled to the plurality of streaming engines. The interface, in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator may include configuration registers to store configuration information indicating a respective security state associated with functional circuits and streaming engine of the hardware accelerator, which may be used to control performance of operations by the hardware accelerator.
    Type: Application
    Filed: February 28, 2023
    Publication date: July 4, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Francesca GIRARDI, Giuseppe DESOLI, Ruggero SUSELLA, Thomas BOESCH, Paolo Sergio ZAMBOTTI