METHOD OF MAKING A MULTI-BIT NANOCRYSTAL MEMORY
A manufacturing method for an improved memory cell having a pair of non-volatile memory transistors with each transistor using a nanocrystal gate structure, the transistor pair constructed between a pair of bit line polysilicon depositions. Between the pair of non-volatile memory transistors, a word line device is interposed, allowing serial linkage of the pair of non-volatile memory transistors.
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This is a divisional application of pending U.S. patent application Ser. No. 11/001,936 filed Dec. 2, 2004.
TECHNICAL FIELDThe invention relates to non-volatile memory transistor construction, and, more specifically, to a manufacturing method for a transistor employing nanocrystals.
BACKGROUND ARTNon-volatile memory designs continue to improve with technological advancements. Floating gate and MONOS (metal/polysilicon oxide nitride oxide silicon) are types of non-volatile memories. In conventional floating gate structures, charge is stored on to a floating gate, by either Fowler-Nordheim tunneling or by source side injection. The cell operation is governed by electron charge storage on an electrically isolated floating gate. The amount of charge stored modulates the memory cell's transistor characteristic. Because the only electrical connection to the floating gate is through capacitors, the memory cell can be thought of as a linear capacitor network with an attached N-channel transistor. Any charge present on the floating gate is retained due to the inherent Si-SiO2 energy barrier height, leading to the non-volatile nature of the memory cell.
MONOS memory cells, in comparison to standard floating gate cells, may have faster program times and higher densities. In MONOS memory cells using sidewall spacer structures, a source side electron injection approach is faster and may require lower voltages than electron tunneling methods used for a standard floating gate design. U.S. Pat. No. 6,686,632, to Ogura et al. describes a dual bit MONOS memory having a twin cell structure. The cell structure is realized by placing sidewall control gates over a composite of oxide nitride oxide (ONO). Both sides of a word gate and control gates are formed using a disposable sidewall process. During construction of this device, a sidewall spacer is required for the word gate to accommodate the ONO and source side injection structure.
Newer processes that may be used in non-volatile memory designs also continue to be developed. For example, metal nanocrystal memories have been utilized to enhance the performance of memory cell devices to improve the work function. In a nanocrystal non-volatile storage device, charge is not stored on a continuous floating gate layer. Instead, a large number of discrete mutually isolated nanocrystals are contained on a semiconductor layer. Nanocrystals may be employed in storing small amounts of electrical charge, even being able to store a single, or a small number, of atoms. In theory, smaller transistors may be made because structures containing nanocrystal charge storage “dots” might be made exceedingly small.
A downside to using nanocrystals has been high power consumption due to refresh requirements, short retention time, and high capacitance. U.S. Pat. No. 6,165,842, to Shin et al. describes a method for fabricating a nonvolatile memory device using crystal dots. A tunneling dielectric, a thin amorphous silicon film, a polysilicon layer having nanocrystals, a dielectric layer, and a polysilicon film are formed. The method develops a nonvolatile memory cell gate structure having dimensions limited by the resolution of optics or photoresist materials used in photolithography and must develop a multitude of layers to support and construct a nanocrystal layer.
Such devices are therefore difficult to manufacture because nanocrystals are many times smaller than photolithography resolution limits currently used in manufacturing integrated circuits.
SUMMARY OF THE INVENTIONThe present invention is a manufacturing method for an improved memory cell device employing nanocrystals to reduce an overall size of each memory cell gate, and therefore reduce the overall integrated circuit or die size of a memory circuit. In accordance with the present invention, a nanocrystal layer is used in the construction of a dual bit non-volatile memory structure. A plurality of trenches are developed to reduce the gate area or each memory cell which uses a nanocrystal charge storage region. Charge is transferred through a thin tunneling barrier to the nanocrystals. The method forms a memory cell gate using a plurality of offset trenches to expose and remove a portion of a nanocrystal layer to develop a nanocrystal gate area having at least one dimension that is smaller than current photolithography resolution limits.
BRIEF DESCRIPTION OF THE DRAWINGS
Collectively, individual nanocrystals in a nanocrystal memory gate can control the channel conductivity of a memory cell. Each nanocrystal individually stores a small number of electrons. One of the advantages of a nanocrystal charge storage gate is an ability to use thinner tunnel oxides and shorter channel lengths and therefore, a smaller cell area may be developed. In addition, the stored charge (electrons) in a nanocrystal charge storage gate may be directed to a specific area within the storage gate area and can be configured to store a single logic state (bit) or multiple logic states (bits) within a given cell.
With reference to an exemplary process beginning with
The nanocrystals may be comprised of any material such as a silicon, germanium, Si-Ge, or metal, and the nanocrystal layer will typically have an approximate 50% to 75% area coverage of nanocrystals. In a specific embodiment, the nanocrystal area coverage will be approximately 60%. The nanocrystal layer 22 may be fabricated by various techniques including chemical vapor deposition, low energy implantation, or by aerosol formation.
With reference again to
Above the first polysilicon layer 30 a third oxide layer 40, a nitride layer 41, and a fourth oxide layer 42 are formed. Referring to
In reference to
Next, several steps will be used to develop channel, source, and drain areas for a dual cell memory structure. With reference to
Next, referring to
Referring to
Next, with reference to
Referring to
With reference to
Next, a cleaning operation may be performed to prepare the wafer surface for a subsequent oxidation step. With continued reference to
A basic non-volatile dual memory cell structure of
Presented in this description is an exemplary structure and fabrication method for a dual multi-bit memory cell. It is to be understood that the above description is intended to be illustrative, and not restrictive. Those of skill in the art will recognize that the invention can be practiced with modification and alteration within the spirit and scope of the appended claims and many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The procedures for formation, for example, the formation of shallow trench isolation areas, p-well, and n-well are similar to conventional CMOS processing and, although not shown or described, these processes or structures may be used with the invention described. Other processes such as the formation of oxides, polysilicon layers, or nitride layers may be performed by other processes not described but known to one of skill in the art. Masking processes with exposures, development, and vertical or horizontal etching of layers may be performed by a variety of processes including chemical etching or ion milling. The description is thus to be regarded as illustrative rather than limiting. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which said claims are entitled.
Claims
1. A method of fabricating a nonvolatile memory cell device, the method comprising:
- forming a nanocrystal layer over a substrate;
- forming a first polysilicon layer over said nanocrystal layer;
- removing a first portion of said first polysilicon layer, thereby forming a first trench in said first polysilicon layer;
- removing a first portion of said nanocrystal layer, said first portion of said nanocrystal layer substantially within an area circumscribed by said first trench;
- removing a second portion of said first polysilicon layer, said second portion offset from said first trench location by a distance less than a photolithography resolution limit in an optical process, thereby forming a second trench in said first polysilicon layer;
- removing a second portion of said nanocrystal layer, said second portion of said nanocrystal layer substantially within an area circumscribed by said second trench, thereby forming a nanocrystal gate area having a width that is smaller than a photolithography resolution limit in an optical process; and
- forming a plurality of doped areas in said substrates.
2. The method of fabricating the nonvolatile memory cell device of claim 1 wherein said nanocrystal layer has an approximate thickness between 20 Angstroms and 60 Angstroms.
3. The method of fabricating the nonvolatile memory cell device of claim 1 wherein a tunnel oxide layer is formed before forming said nanocrystal layer and a control oxide layer is formed after forming said nanocrystal layer.
4. The method of fabricating the nonvolatile memory cell device of claim 3 wherein an average summed thickness of said tunnel oxide layer, said nanocrystal layer, and said nanocrystal layer is between approximately 120 Angstroms and 180 Angstroms.
5. The method of fabricating the nonvolatile memory cell device of claim 1 wherein the step of forming said plurality of doped areas in said substrate is performed before removing said first portion of said nanocrystal layer.
6. The method of fabricating the nonvolatile memory cell device of claim 1 wherein the step of forming said plurality of doped areas in said substrate is performed after removing said first portion of said nanocrystal layer.
7. The method of fabricating the nonvolatile memory cell device of claim 1 wherein the step of forming said plurality of doped areas in said substrate further comprises forming at least one doped area before removing said first portion of said nanocrystal layer, and forming at least one other doped area in said substrate after removing said first portion of said nanocrystal layer.
8. The method of fabricating the nonvolatile memory cell device of claim 1 wherein a second polysilicon layer is formed filling said first trench in said first polysilicon layer.
9. The method of fabricating the nonvolatile memory cell device of claim 8 wherein a third polysilicon layer is formed filling said second trench in said first polysilicon layer.
10. A method for fabricating a nonvolatile dual memory cell device comprising:
- forming a tunnel oxide layer a nanocrystal layer and a control oxide layer sequentially on a face of an underlying substrate thereby forming a nanocrystal stack layer;
- forming a first polysilicon layer over said nanocrystal stack layer;
- forming an oxide-nitride-oxide stack layer over said first polysilicon layer;
- removing a portion of said oxide-nitride-oxide stack layer thereby forming a patterned oxide-nitride-oxide stack layer and exposing a portion of said first polysilicon layer;
- removing said exposed portion of said first polysilicon layer, forming a first trench in said first polysilicon layer and exposing a first portion of said nanocrystal stack layer;
- forming at least one doped area in said underlying substrate substantially beneath said first trench;
- removing said first exposed portion of said nanocrystal stack layer;
- forming a second polysilicon layer thereby filling said first trench in said first polysilicon layer;
- removing a portion of said second polysilicon layer thereby exposing a sidewall portion of said first trench;
- forming an additional oxide layer over said second polysilicon layer and over said exposed sidewall portion of said first trench;
- removing a portion of said additional oxide layer using said nitride in said patterned oxide-nitride-oxide stack layer as a stop;
- removing a second portion of said additional oxide layer and removing a second portion of said first polysilicon layer, said second portion of said additional oxide layer and said second portion of said first polysilicon layer being offset from said first trench location by a distance less than a photolithography resolution limit in an optical process, thereby forming a second trench in said first polysilicon layer and exposing a second portion of said nanocrystal stack layer; and
- removing said exposed second portion of nanocrystal stack layer, said second portion of said nanocrystal layer substantially within an area circumscribed by said second trench thereby forming a nanocrystal gate area having a width that is smaller than a photolithography resolution limit in an optical process.
11. The method of fabricating the nonvolatile memory cell device of claim 10 wherein said nanocrystal layer has an approximate thickness between 20 Angstroms and 60 Angstroms.
12. The method of fabricating the nonvolatile dual memory cell device of claim 10 wherein an average summed thickness of said tunnel oxide layer said nanocrystal layer, and said nanocrystal layer is between approximately 120 Angstroms and 180 Angstroms.
13. The method of fabricating the nonvolatile dual memory cell device of claim 10 wherein the step of forming said at least one doped area in said underlying substrate is performed before removing said first exposed portion of said nanocrystal stack layer.
14. The method of fabricating the nonvolatile dual memory cell device of claim 10 wherein the step of forming said at least one doped area in said underlying substrate is performed after removing said first exposed portion of said nanocrystal stack layer.
15. The method of fabricating the nonvolatile dual memory cell device of claim 10 wherein forming said at least one doped area in said underlying substrate further comprises forming a doped area before removing said first exposed portion of said nanocrystal stack layer and also forming at least one other doped area after removing said first exposed portion of said nanocrystal stack layer.
16. The method of fabricating the nonvolatile dual memory cell device of claim 10 wherein a third polysilicon layer is formed thereby filling said second trench in said first polysilicon layer.
Type: Application
Filed: Jan 12, 2007
Publication Date: May 17, 2007
Applicant: ATMEL CORPORATION (San Jose, CA)
Inventor: Bohumil Lojek (Colorado Springs, CO)
Application Number: 11/622,774
International Classification: H01L 21/336 (20060101);