THREE-DIMENSIONAL MULTI-GATE DEVICE AND FABRICATING METHOD THEREOF
A three-dimensional multi-gate device has a silicon fin, a gate structure, and a stress-adjusting layer. The gate structure contacts with three surface of the silicon fin to form a three-dimensional gate structure. The stress-adjusting layer is disposed on the gate structure to provide stress along the direction parallel to the channel length of the gate structure. The stress helps promote the mobility of the charges in the channel region under the gate structure and improve the electrical performance such as drive current and DIBL of the three-dimensional multi-gate device.
This application is a divisional of application Ser. No. 11/161,950 filed Aug. 23, 2005.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a three-dimensional multi-gate device and a fabricating method thereof, and more particularly, to a three-dimensional multi-gate device having a stress-adjusting layer and a fabricating method thereof.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various three-dimensional multi-gate devices have been developed. The three-dimensional multi-gate device is advantageous for the following reasons. First, the manufacturing processes of three-dimensional multi-gate devices can be integrated into the traditional logic device processes, and thus are more compatible. Furthermore, due to the structural particularity of the three-dimensional multi-gate device, traditional shallow trench isolation is not required. In addition, since the three-dimensional structure increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer under the same gate length. Therefore, the current between the source and the drain is increased.
Although the three-dimensional multi-gate device is advantageous for many reasons, the carrier mobility still requires to be improved.
SUMMARY OF THE INVENTIONIt is therefore one of the objects of the claimed invention to provide a three-dimensional multi-gate device and a fabricating method thereof to solve the aforementioned problems.
According to the claimed invention, a three-dimensional multi-gate device is disclosed. The three-dimensional multi-gate structure has a semiconductor substrate; a silicon fin disposed on the semiconductor substrate, the silicon fin having a top surface and two side surfaces; a gate structure disposed on the silicon fin and partially covering the top surface and the two side surfaces of the silicon fin; two doped regions disposed in the silicon fin under both sides of the gate structure; and a stress-adjusting layer covering the gate structure.
According to the claimed invention, a method for fabricating a three-dimensional multi-gate device is also disclosed. The method includes the following steps:
(a) providing a semiconductor substrate and forming a silicon fin on the semiconductor substrate, the silicon fin having a top surface and two side surfaces;
(b) forming a gate structure on the silicon fin, the gate structure partially covering the top surface and the two side surfaces of the silicon fin;
(c) forming two doped regions in the silicon fin under both sides of the gate structure; and
(d) forming a stress-adjusting layer covering the gate structure.
The three-dimensional multi-gate device according to the claimed invention features the stress-adjusting layer. The stress-adjusting layer provides the gate structure with stress through a direction parallel to the length of the channel, such that the carrier mobility in the channel region under the gate structure is raised and the electrical performance of the device is improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
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By virtue of the stress-adjusting layer, the carrier mobility and the drive current characteristic of the three-dimensional multi-gate device are improved. It is to be noted that the aforementioned embodiment is illustrated with an N type three-dimensional multi-gate device, thus silicon nitride that can provide a high tensile stress is adopted. If a P type three-dimensional multi-gate device is desired, the stress-adjusting layer can be selected from other materials that provide a high compressed stress. For example, the stress-adjusting layer can be made of silicon oxide, silicon oxynitride, or other suitable materials.
In comparison with the prior art, the three-dimensional multi-gate device of the present invention has better electrical performance resulted from the stress-adjusting layer.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A three-dimensional multi-gate device comprising:
- a semiconductor substrate;
- a silicon fin disposed on the semiconductor substrate, the silicon fin having a top surface and two side surfaces;
- a gate structure disposed on the silicon fin and partially covering the top surface and the two side surfaces of the silicon fin;
- two doped regions disposed in the silicon fin under both sides of the gate structure; and
- a stress-adjusting layer covering the gate structure.
2. The three-dimensional multi-gate device of claim 1, further comprising a plurality of salicide layers disposed on the gate structure and the two doped regions.
3. The three-dimensional multi-gate device of claim 1, wherein the salicide layers comprise cobalt salicide layers, nickel salicide layers, titanium salicide layers or platinum salicide layers.
4. The three-dimensional multi-gate device of claim 1, wherein the stress-adjusting layer comprises a silicon nitride layer, a silicon oxide layer or a silicon oxynitride layer.
5. The three-dimensional multi-gate device of claim 1, wherein the stress-adjusting layer has a thickness ranging between 100 Å to 2000 Å.
6. The three-dimensional multi-gate device of claim 1, further comprising a dielectric layer disposed on the stress-adjusting layer.
7. The three-dimensional multi-gate device of claim 1, further comprising a plurality of via holes passing through the dielectric layer and the stress-adjusting layer.
8. The three-dimensional multi-gate device of claim 1, wherein the three-dimensional multi-gate device is N type, and the stress-adjusting layer provides a tensile stress.
9. The three-dimensional multi-gate device of claim 1, wherein the three-dimensional multi-gate device is P type, and the stress-adjusting layer provides a compressed stress.
Type: Application
Filed: Mar 30, 2007
Publication Date: Jul 19, 2007
Inventors: Wen-Shiang Liao (Miao- Li Hsien), Wei-Tsun Shiau (Kao-Hsiung Hsien)
Application Number: 11/693,739
International Classification: H01L 29/80 (20060101);