Abstract: A semiconductor package includes a semiconductor die, an encapsulation layer and at least one antenna structure. The encapsulation layer laterally encapsulates the semiconductor die. The at least one antenna structure is embedded in the encapsulation layer aside the semiconductor die. The at least one antenna structure includes a dielectric bulk, and a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer.

Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Abstract: A package structure and a formation method are provided. The package structure includes a chip structure bonded to a substrate through dielectric-to-dielectric bonding and metal-to-metal bonding and interconnect dielectric layers formed over the chip structure. The package structure further includes interconnect conductive structures formed in the interconnect dielectric layers and a transmission line formed in the interconnect dielectric layers. The package structure further includes a magnetic structure formed in the interconnect dielectric layers and separated from the transmission line by the interconnect dielectric layers. In addition, the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structures.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Abstract: A semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. The semiconductor substrate includes an optical reflective layer. The first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. The grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.

Abstract: A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.

Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Abstract: A method includes following steps. A silicon oxide layer is formed on a temporary carrier. The silicon oxide layer is etched to form through vias (TVs) penetrating through the silicon oxide layer. The TVs are filled with a conductive material to form conductive TVs. The temporary carrier from a first surface of the silicon oxide layer. An under bump metallurgy (UBM) layer is formed contacting a first surface of the conductive material. An interface between the UBM layer and the conductive material is coplanar with the first surface of the silicon oxide layer.

Abstract: A method for forming a silicon oxide interposer includes following steps. A spin on glass (SOG) or spin on dielectric (SOD) material is spin coated on a temporary carrier. The SOG or SOD material is cured to form a silicon oxide layer on the temporary carrier. The silicon oxide layer is etched to form through via holes penetrating through the silicon oxide layer. The step of etching the silicon oxide layer stops when bottoms of the through via holes reach a top surface of the temporary carrier. The through via holes are filled with a conductive material to form conductive through vias (TVs). The temporary carrier is removed from a bottom surface of the silicon oxide layer. An under bump metallurgy (UBM) layer is formed interfacing the conductive material and the bottom surface of the silicon oxide layer.

Abstract: A semiconductor device includes a silicon substrate having a first region and a second region. The semiconductor device includes a silicon lens formed in the first region and along a surface of the silicon substrate on a first side of the silicon substrate. The semiconductor device includes a photonic die disposed in the first region and on a second side of the silicon substrate, the second side being opposite to the first side. The semiconductor device includes a waveguide disposed on the second side of the silicon substrate and having a grating coupler.

Abstract: A method of forming a semiconductor structure includes the following steps. An antenna pad is formed. A plurality of conductive vias are formed over the antenna pad to electrically connect to the antenna pad, wherein the conductive vias are arranged to surround an area of the antenna pad. A plurality of first conductive patterns are formed over the conductive vias, to form a ground plane, wherein the first conductive patterns are overlapped with the area of the antenna pad and electrically isolated from the conductive vias.

Abstract: A package includes a die, an inductor, and a permalloy core. The die has an active surface and a rear surface opposite to the active surface. The inductor includes a first portion, a second portion, and a third portion. The first portion is above the active surface of the die. The third portion is below the rear surface of the die. The second portion is aside the die. The second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor.

Abstract: Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.

Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Abstract: An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.

Abstract: A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.

Abstract: A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A conductive coil is formed over a substrate, and the conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed in the middle metal layer through a pick and place operation before forming the top metal layer of the conductive coil. A semiconductor die is bonded to the interposer die. The permalloy device has a polygonal ring shape wrapped with the conductive coil.

Abstract: A package structure and a formation method of a package structure are provided. The method includes surrounding a semiconductor chip with a protective layer. The protective layer has a first dielectric constant. The method also includes partially removing the protective layer to form an opening. The method further includes forming a dielectric structure partially or completely filling the opening. The dielectric structure has a second dielectric constant, and the second dielectric constant is higher than the first dielectric constant. The method further includes forming a redistribution structure over the semiconductor chip, the protective layer, and the dielectric structure.

Abstract: An optical attenuating structure is provided. The optical attenuating structure includes a substrate, a waveguide, doping regions, an optical attenuating member, and a dielectric layer. The waveguide is extended over the substrate. The doping regions are disposed over the substrate, and include a first doping region, a second doping region opposite to the first doping region and separated from the first doping region by the waveguide, a first electrode extended over the substrate and in the first doping region, and a second electrode extended over the substrate and in the second doping region. The first optical attenuating member is coupled with the waveguide and disposed between the waveguide and the first electrode. The dielectric layer is disposed over the substrate and covers the waveguide, the doping regions and the first optical attenuating member.