Abstract: A package structure includes a first insulating layer, a second insulating layer, a magnetic element, a molding material, and a third insulating layer. The first insulating layer is formed on a substrate, and a first conductive feature is formed in the first insulating layer. The second insulating layer is formed on the first insulating layer. The magnetic element is disposed on the second insulating layer and includes a plurality of dielectric layers and magnetic permeable layers that are alternatively stacked. The molding material covers the magnetic element and the conductive feature, and conductive vias penetrate the second insulating layer and the molding material. The third insulating layer is formed on the molding material, and a second conductive feature is formed in the third insulating layer. The first conductive feature, the conductive vias, and the second conductive feature are electrically connected to form a coil surrounding the magnetic element.

Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.

Abstract: A package structure and a formation method are provided. The method includes receiving a first chip structure, and the first chip structure has multiple conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. Top surfaces of the conductive bonding structures and the dielectric bonding structure are coplanar. The method also includes bonding a second chip structure to the dielectric bonding structure and the conductive bonding structures through dielectric-to-dielectric bonding and metal-to-metal bonding. The method further includes forming an insulating layer over the first chip structure, and the insulating layer laterally surrounds the first chip structure. In addition, the method includes forming a capacitor element laterally spaced apart from the second chip structure, and the insulating layer partially surrounds the capacitor element.

Abstract: A semiconductor package includes a semiconductor die, an encapsulation layer and at least one antenna structure. The encapsulation layer laterally encapsulates the semiconductor die. The at least one antenna structure is embedded in the encapsulation layer aside the semiconductor die. The at least one antenna structure includes a dielectric bulk, and a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Abstract: A method includes: forming an interconnect structure over a semiconductor substrate. The interconnect structure includes: a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the horizontally-extending conductive lines, wherein the magnetic core and the conductive coil are arranged in an inductor zone of the interconnect structure; and a connecting metal line adjacent to and on an outside of the inductor zone, the connecting metal line being electrical isolated from the inductor zone. The vertically-extending conductive vias include first conductive vias, second conductive vias, and a third conductive via between the first conductive vias and the second conductive vias.

Abstract: A semiconductor package includes a die, a first thermal pattern and an interposer. The first thermal pattern is disposed aside the die. The interposer is bonded to the die and includes a substrate, a wiring structure between the substrate and the die and a second thermal pattern. The second thermal pattern is thermally coupled to the first thermal pattern.

Abstract: A semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. The semiconductor substrate includes an optical reflective layer. The first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. The grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.

Abstract: A semiconductor package includes a semiconductor die, an encapsulation layer and at least one antenna structure. The encapsulation layer laterally encapsulates the semiconductor die. The at least one antenna structure is embedded in the encapsulation layer aside the semiconductor die. The at least one antenna structure includes a dielectric bulk, and a dielectric constant of the dielectric bulk is higher than a dielectric constant of the encapsulation layer.

Abstract: A package structure includes a first die, a second die over and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material, and a plurality of first conductive pillars extending through the insulating material, wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Abstract: A package structure and a formation method are provided. The package structure includes a chip structure bonded to a substrate through dielectric-to-dielectric bonding and metal-to-metal bonding and interconnect dielectric layers formed over the chip structure. The package structure further includes interconnect conductive structures formed in the interconnect dielectric layers and a transmission line formed in the interconnect dielectric layers. The package structure further includes a magnetic structure formed in the interconnect dielectric layers and separated from the transmission line by the interconnect dielectric layers. In addition, the magnetic structure is electrically isolated from the chip structure and the interconnect conductive structures.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Abstract: A semiconductor structure including a semiconductor substrate, a first patterned dielectric layer, a grating coupler and a waveguide is provided. The semiconductor substrate includes an optical reflective layer. The first patterned dielectric layer is disposed on the semiconductor substrate and covers a portion of the optical reflective layer. The grating coupler and the waveguide are disposed on the first patterned dielectric layer, wherein the grating coupler and the waveguide are located over the optical reflective layer.

Abstract: A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.

Abstract: A method includes following steps. A silicon oxide layer is formed on a temporary carrier. The silicon oxide layer is etched to form through vias (TVs) penetrating through the silicon oxide layer. The TVs are filled with a conductive material to form conductive TVs. The temporary carrier from a first surface of the silicon oxide layer. An under bump metallurgy (UBM) layer is formed contacting a first surface of the conductive material. An interface between the UBM layer and the conductive material is coplanar with the first surface of the silicon oxide layer.

Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Abstract: A method for forming a silicon oxide interposer includes following steps. A spin on glass (SOG) or spin on dielectric (SOD) material is spin coated on a temporary carrier. The SOG or SOD material is cured to form a silicon oxide layer on the temporary carrier. The silicon oxide layer is etched to form through via holes penetrating through the silicon oxide layer. The step of etching the silicon oxide layer stops when bottoms of the through via holes reach a top surface of the temporary carrier. The through via holes are filled with a conductive material to form conductive through vias (TVs). The temporary carrier is removed from a bottom surface of the silicon oxide layer. An under bump metallurgy (UBM) layer is formed interfacing the conductive material and the bottom surface of the silicon oxide layer.

Abstract: A semiconductor device includes a silicon substrate having a first region and a second region. The semiconductor device includes a silicon lens formed in the first region and along a surface of the silicon substrate on a first side of the silicon substrate. The semiconductor device includes a photonic die disposed in the first region and on a second side of the silicon substrate, the second side being opposite to the first side. The semiconductor device includes a waveguide disposed on the second side of the silicon substrate and having a grating coupler.

Abstract: A method of forming a semiconductor structure includes the following steps. An antenna pad is formed. A plurality of conductive vias are formed over the antenna pad to electrically connect to the antenna pad, wherein the conductive vias are arranged to surround an area of the antenna pad. A plurality of first conductive patterns are formed over the conductive vias, to form a ground plane, wherein the first conductive patterns are overlapped with the area of the antenna pad and electrically isolated from the conductive vias.