Semiconductor device and method for manufacturing the semiconductor device

Abstract

A method is used for manufacturing a semiconductor device including a circuit-fabricated side on which an encapsulation layer is formed. The method includes the following steps. A semiconductor wafer is placed on the suction surface of a suction stage, the suction surface having a diameter in the range of 99 to 100.5% of a diameter of the semiconductor wafer. The semiconductor wafer is held on the suction surface of the suction stage by suction. A back surface of the semiconductor wafer is ground. The back surface of the semiconductor wafer is ground such that a surface roughness of the ground back surface is not greater than 5 nm. The encapsulation layer has a flexural modulus not smaller than 12 Gpa and not larger than 18 Gpa.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a method for manufacturing small semiconductor devices such as a wafer level chip size package (WCSP) in which a plurality of circuit elements are formed on a semiconductor wafer and then the semiconductor wafer is sliced into individual dice.

2. Description of the Related Art

Recently, there have been strong demands in the field of electronic equipment towards miniaturized and thinner packages. The thickness of passive components such as capacitors and resistors mounted On a circuit board has been reduced to about 200 μm. This trend has also placed demands on active components such as memories and CPUs having as small a thickness as the capacitors and resistors.

WCSP type semiconductor devices are generally of the construction in which circuits are fabricated on one side of a semiconductor substrate (e.g., Si) and are sealed with a sealing layer of resin. Because the encapsulation layer and the semiconductor substrate have different physical values (primarily thermal expansion coefficient), when they are laminated, the semiconductor substrate tends to extend outward. One problem with grinding a semiconductor wafer at its back side surface is that a thinner wafer causes the semiconductor substrate to tend to extend further outward.

A thin semiconductor wafer may be manufactured by grinding the back surface of the semiconductor wafer while maintaining the semiconductor flat in the following way. A protection tape is attached to the circuit side of the semiconductor wafer. Then, the semiconductor wafer is mounted on a suction stage with the protection tape between the semiconductor wafer and the suction stage. After grinding, the semiconductor wafer is transferred to the next process with the protection tape attached to the semiconductor wafer. Then, a die bonding film is attached to the side of the wafer opposite to the protection tape, and then the protection tape is removed from the semiconductor wafer. In this manner, warpage of a semiconductor wafer is prevented.

Alternatively, a thin semiconductor wafer may be manufactured by grinding the back surface of the semiconductor wafer while maintaining the semiconductor flat in the following way. After coarse grinding, the ground wafer is sucked to a suction pad that is as large as the outer geometry of the wafer, and then the semiconductor wafer is released from the suction stage. Subsequently, the semiconductor wafer is transferred to a fine grinding apparatus. This allows the wafer to be maintained flat during the coarse grinding and fine grinding. In this manner, warpage of a semiconductor wafer after fine grinding may be minimized.

The aforementioned techniques are used for grinding the back surface of a semiconductor device while also maintaining the semiconductor wafer flat, enabling manufacturing of a thin semiconductor device. For a laminated structure of a semiconductor wafer and an encapsulation layer of resin, warpage of the semiconductor wafer is due to the difference in thermal expansion coefficient between the wafer and the encapsulation layer. Thus, once the semiconductor wafer is released from the device for maintaining the wafer flat, the semiconductor wafer tends to be warped excessively.

Careful investigation of various conditions for grinding the back surface of a semiconductor wafer revealed the following facts.

(1) Warpage of a semiconductor wafer is enhanced if chipping (e.g., larger than 100 μm) occurs at many locations on the circumference of the wafer. Poor surface roughness of the wafer due to the chipping impairs the resistance of the wafer to warpage, promoting further warpage.

(2) Warpage of a semiconductor wafer depends on the surface roughness of a wafer after grinding. High surface roughness impairs the resistance of the back surface of wafer to warpage, promoting warpage of the wafer.

(3) Warpage of a semiconductor wafer depends on the flexural modulus of an encapsulation layer at room temperature. There exists an optimum value of flexural modulus regardless of the thickness of a semiconductor substrate.

SUMMARY OF THE INVENTION

An object of the invention is to provide a method for minimizing the warpage of a semiconductor wafer during a grinding stage of the manufacturing process of a semiconductor device.

Another object of the invention is to provide a semiconductor device having minimum warpage.

A method is used for manufacturing a semiconductor device including a circuit-fabricated side on which an encapsulation layer is formed.

The method includes the following steps:

placing a semiconductor wafer on a suction surface of a suction stage, the suction surface having a diameter in the range of 99 to 100.5% of a diameter of the semiconductor wafer;

holding the semiconductor wafer on the suction surface of the suction stage by suction; and

grinding a back surface of the semiconductor wafer.

The grinding is performed such that a surface roughness of the ground back surface is not greater than 5 nm.

The method further includes forming the encapsulation layer having a flexural modulus not smaller than 12 Gpa and not larger than 18 Gpa.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limiting the present invention, and wherein:

FIG. 1 is a fragmentary cross-sectional side view of a semiconductor wafer of an embodiment according to the present invention, illustrating a method for manufacturing the semiconductor wafer;

FIG. 2 illustrates the method for manufacturing the semiconductor wafer of the embodiment;

FIG. 3 is a fragmentary cross-sectional side view illustrating a back surface grinding apparatus used at Process #8;

FIG. 4 illustrates the relation between the suction surface and the warpage of a semiconductor wafer;

FIG. 5 illustrates the relationship between the surface roughness and the warpage of the semiconductor wafer;

FIG. 6 illustrates the relationship between the warpage of the semiconductor wafer and the flexural modulus of a resin material for an encapsulation layer; and

FIG. 7 illustrates the relationship between the flexural modulus of the resin material and the flexural strength of a semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of a method of manufacturing a semiconductor wafer according to the present invention will be described with reference to the accompanying drawings.

Embodiment

FIG. 1 is a fragmentary cross-sectional side view of a semiconductor wafer 1 illustrating a method for manufacturing the semiconductor wafer. FIG. 2 is another cross-sectional side view of the semiconductor wafer illustrating the method. FIG. 3 is a fragmentary cross-sectional view illustrating a back surface grinding apparatus used at Process #8, which will be described later.

FIG. 1 is a side view of the semiconductor wafer with a partial cross-sectional view, and illustrates the vicinity of electrode pads formed on a semiconductor wafer and post electrodes connected to the electrode pads via rerouting traces. Referring to FIGS. 1 and 2, the semiconductor wafer 1 is an 8-in disc-shaped semiconductor wafer on which a plurality of WCPS type semiconductor devices are formed simultaneously.

A semiconductor substrate 2 is bulk silicon, which is a part of the semiconductor wafer 1. The semiconductor substrate 2 has a thickness in the range of 0.5 to 1 mm. A plurality of circuit elements are formed on the front surface (i.e., circuit surface 3) of the semiconductor substrate 2, being interconnected by wiring. An insulating layer 4 is formed of an insulating material such as silicone dioxide (SiO₂), and is formed on the circuit surface 3. Contact holes are formed over the respective circuit elements on the semiconductor substrate 2.

Electrode pads 5 (only one is shown in FIG. 1) are formed by etching an electrically conductive layer of aluminum (Al) or titanium (Ti) formed on the insulating layer 4. The electrode pad 5 is electrically connected to a part of a circuit element via a conductor buried in the contact hole formed in the insulating layer 4. A surface protection film 6 covers both the electrode pad 5 and the insulating layer 4 formed of an insulating material such as silicon nitride (Si₃N₄).

An interlayer dielectric film 7 is formed of an insulating material such as polyimide, and is formed on the surface protection film 6. The interlayer dielectric film 7 is etched away at a portion over the electrode pad 5 to form a through-hole 8 to the electrode pad 5. A thin metal layer 9 takes the form of a multi-layer of electrically conductive materials such as titanium (Ti), titanium nitride (TiN), copper (Cu) and the like. The thin metal layer 9 covers the entire front surface of the semiconductor wafer 1. The thin metal layer 9 covers the interlayer dielectric film 7, the inner surface of the through-hole 8, and the electrode pad 5.

A rerouting trace 10 is a rerouting element of, for example, copper formed on the electrode pad 5, and extends to an electrode region 12 in which a post electrode 11 is formed. The rerouting trace 10 is connected to the electrode pad 5 via an underlying metal layer 9, thereby making electrical connection between the post electrode 11 and the electrode pad 5.

The post electrode 11 is a cylindrical projection formed of the same material as the rerouting trace 10, and has a height of about 100 μm. A bump electrode 13 is a hemispherical electrode of, for example, solder. The bump electrode 13 is formed on a top end surface of the post electrode 11, and serve as a terminal for connecting the semiconductor device to an external circuit. The post electrode 11 is connected to the wiring terminal on a circuit board on which the semiconductor device is mounted. The circuit elements on the semiconductor substrate 2 are connected to extend through the electrode pad 5, metal layer 9, rerouting trace 10, post electrode 11, and bump electrode 13.

An encapsulation layer 15 is an insulating layer having a thickness of about 100 μm. The encapsulation layer 15 is formed of a sealing resin (e.g., thermosetting epoxy resin) deposited on the front surface of the semiconductor wafer 1 and thermally cured. The encapsulation layer 15 protects the semiconductor device 30 from humidity in the environment. A protection tape 17 has flexibility such that the protection tape 17 has a side surface that accommodates the ridges and follows of the bump electrodes 13 and that may be cured when it is exposed to ultraviolet light. The protection tape 17 is a single-sided tape having a sticky layer on its one side. The sticky layer is softened when it is irradiated with ultraviolet light. During a grinding process of the back surface of the semiconductor wafer 1, the protection tape 17 protects the front surface of the semiconductor wafer 1 on which circuits are fabricated.

A resist mask 18 is formed by means of photolithography in which a resist is applied to the front surface of the semiconductor wafer 1, is then exposed to light, and is finally developed into a mask.

FIG. 3 illustrates a back surface grinding apparatus 20. When the back surface 1a of the semiconductor ware 1 is ground, the protection tape 17 attached to the semiconductor wafer 1 is directly sucked onto a suction stage 21 and the suction stage 21 rotates with the semiconductor wafer 1 mounted there on. The suction stage 21 has a negative pressure chamber 22 formed in its central portion, a negative pressure being supplied to the pressure chamber 22 to hold the semiconductor ware 1 by suction.

A suction plate 23 is formed of a porous ceramic material in the shape of a disc that has a suction surface 23a and almost the same diameter as the semiconductor wafer 1. The suction plate 23 is mounted to an upper opening of the negative pressure chamber 22 such that the upper surface of the suction plate 23 is flush with the upper surface of the suction stage 21. A grinder 25 includes a grindstone 26 in which hard abrasive grains such as diamond and a non-organic filler are compressed into a ring-shape with the aid of a resin material and/or a metal and are then sintered. The grinder 25 rotates at high speed to grind the back surface 1a of the semiconductor wafer 1. The grinder 25 is positioned relative to the semiconductor wafer 1 such that the grinding surface 26a of the grindstone 26 extends in a direction that passes through the substantially the central portion of the semiconductor wafer 1.

For an 8-in semiconductor wafer, the suction surface 23a of the back surface grinding apparatus 20 has a diameter of about 200 mm as opposed to a conventional back surface grinding apparatus (e.g., Model DFG-841 available from Disco) having a suction surface with a diameter of 186 mm. Thus, the suction surface 23a is capable of sucking the entire surface of the semiconductor wafer 1. The method of manufacturing a semiconductor device of the embodiment will be described with reference to FIGS. 1 and 2.

Process #1: A plurality of circuit elements, not shown, are formed on the circuit surface 3 of the semiconductor substrate 2. Contact holes, not shown, are formed in the insulating layer 4 at locations over the respective circuit elements by chemical vapor deposition (CVD). An electrically conductive layer is formed on the insulating layer 4 by sputtering. Then, the insulating layer 4 is selectively etched away to form electrode pads 5 having a predetermined shape. The electrode pads 5 make electrical connection between the circuit elements.

After forming the electrode pads 5, a surface protection film 6 is formed of a silicon nitride by CVD, covering the electrode pads 5 and insulating layer 4. The surface protection film 6 is selectively etched so that the electrode pads 5 are exposed. Then, an interlayer dielectric film 7 is formed on the surface protection film 6 and the electrode pads 5, and then portions of the interlayer dielectric film 7 over the electrode pads 5 are etched away, thereby forming through-holes 8 in the interlayer dielectric film 7. Thus, the through-holes 8 extend as deep as the electrode pad 5.

Process #2: A base metal layer 9 is formed on the front surface of the semiconductor wafer 1 by sputtering. The base metal layer 9 includes a plurality of layers, and covers the interlayer dielectric film 7 and the electrode pad 5. A resist mask 18 is formed by means of photolithography, and covers an area except for the area of the base metal layer 9 from the electrode pad 5 to the electrode region 12. Then, a conductive material is electrocoated on the base metal layer 9 by electroplating, thereby forming the rerouting trace 10 that extends from the electrode pad 5 to the electrode region 12.

Process #3: The resist mask 18 formed in Process #2 is removed by a resist remover, and another resist mask 18 is formed by means of photolithography. The resist mask 18 covers the front surface of the semiconductor wafer 1 except for the electrode region 12 over the rerouting trace 10. Then, a conductive material is electrocoated on the rerouting trace 10 by electroplating, thereby forming the post electrode 11.

Process #4: The resist mask 18 formed in the Process 3 is removed by using a resist remover. Then, the base metal layer 9 is removed by wet etching except for an area of the rerouting trace 10 and the post electrode 11.

Process #5: The semiconductor wafer 1 is placed in an encapsulation mold, not shown, and a resin is introduced into a space above the front surface of the semiconductor wafer 1 in the encapsulation mold. The encapsulation mold presses the peripheral portion of the front surface of the semiconductor wafer 1 to prevent leakage of the resin and/or spreading around the back surface 1a of the semiconductor wafer 1. As a result, there will be a peripheral area 1b of the semiconductor wafer 1 where no encapsulation layer 15 is formed, creating a step. The peripheral portion 1b is about 2 mm wide which represents about 4% of the diameter of the semiconductor wafer 1.

Process #6: The semiconductor wafer 1 is taken out of the encapsulation mold. The front surface of the encapsulation layer 15 is ground so that top ends 11a of the post electrodes 11 are exposed to the front surface of the encapsulation layer 15 and are flush with the front surface of the encapsulation layer 15. The resulting encapsulation layer 15 has a thickness of about 100 μm.

Process #7: Solder is printed on the top end 11a and then the solder is melted, thereby forming a hemispherical bump electrode 13 that projects upwardly from the top end 11a.

Process #8: The protection tape 17 is attached to the semiconductor wafer 1 such that the adhesive-coated side of the protection tape 17 contacts the front surface of the semiconductor wafer 1 on which the bump electrodes 13 are formed. Then, the protection tape 17 is cut to substantially the same diameter as the semiconductor wafer 1. The semiconductor wafer 1 is then flipped over, and is placed on the suction stage 21 of the back surface grinding apparatus 20 with the protection tape 17 abutting the suction surface 23a. A negative pressure is supplied from a negative pressure source such as a vacuum pump to the negative pressure chamber 22 such that the entire surface of the semiconductor wafer 1 is sucked to the suction surface 23a.

The suction stage 21 and grinder 25 are rotated to grind the back surface 1a of the semiconductor substrate 2 until the semiconductor substrate 2 has a thickness in the range of 50-300 μm (e.g., 190 cm in the embodiment).

Process #9: After grinding the back surface 1a, the protection tape 17 on the semiconductor wafer 1 is irradiated with ultraviolet light so that the adhesive layer cures. Then, the protection tape 17 is peeled off from the semiconductor wafer 1. Then, a resilient tape 28 is attached to the front surface of the semiconductor wafer 1. Then, the semiconductor wafer 1 is cut along lines known as “street indices” provided on the front surface of the semiconductor wafer 1 by using a blade 29, thereby slicing the semiconductor wafer 1 into individual dice.

Process 10: The individual dice, i.e., WCSP type semiconductor devices 30 are each transferred onto a chip tray by means of, for example, a robot arm. In this manner, miniaturized WCSP type semiconductor devices 30 having a thickness not larger than 0.5 mm are manufactured.

During the aforementioned manufacturing process, in order to minimize warpage of the semiconductor wafer 1, it is vitally important to prevent chipping at a large number of locations of the peripheral portion 1b of the semiconductor substrate 2. The suction stage 21 usually has a small suction surface, and the stepped portion 1b surrounding the encapsulation layer 15 has low rigidity. Chipping at the peripheral portion 1b appears to occur due to the fact that the semiconductor substrate 2 flutters or vibrates at its stepped portion 1b during the grinding operation at Process #8.

FIG. 4 illustrates the relation between the suction surface of the suction stage and the warpage of the semiconductor wafer 1. FIG. 4 plots the ratio of diameter of the suction surface 23a to that of the semiconductor wafer 1 (i.e., diameter ratio) as the abscissa, and the warpage of the semiconductor wafer 1 as the ordinate.

The semiconductor wafer 1 under test has the following dimensions.

The semiconductor substrate 2 has a thickness of 190 μm. The encapsulation layer 15 has a thickness of 90 μm. The semiconductor wafer 1 has a diameter of 200 mm. Referring to FIG. 4, the warpage of the semiconductor wafer begins to decrease when the diameter ratio exceeds 97%. Warpage of the semiconductor wafer 1 remains low for diameter ratios in the range of 99-100.5%, and increases rapidly for diameters larger than 100.5%.

In other words, the diameter of the suction surface 23a is preferably not smaller than 99% and not more than 100.5%. For diameter ratios not larger than 99%, the suction surface is too small in area, causing the peripheral portion 1b of the semiconductor wafer 1 to flutter. For diameter ratios larger than 100.5%, areas of the suction surface 1a not covered by the semiconductor wafer 1 increase, and therefore a large fraction of the negative pressure escapes. This causes the peripheral portion 1b of the semiconductor wafer 1 to flutter.

When the front surface of the semiconductor wafer 1 is sucked to the suction surface 23a, the peripheral portion 1b does not flutter provided that the suction surface 23a has a diameter in the range of 99 to 100.5% of that of the semiconductor wafer 1. This prevents chipping from occurring at the peripheral portion 1b of the semiconductor wafer 1 that would otherwise cause a significant decrease in the force for holding the semiconductor wafer 1 against warpage. Thus, the semiconductor wafer 1 will not crack due to chipping at the peripheral portion 1b.

In order to sufficiently minimize warpage of the semiconductor wafer 1, it is important that the surface roughness of the back surface 1a of the semiconductor wafer 1 be improved. FIG. 5 illustrates the relationship between the surface roughness and the warpage of the wafer. FIG. 5 plots the surface roughness Ra as the abscissa and the warpage of the wafer as the ordinate.

The semiconductor wafer 1 under test has the following dimensions.

The semiconductor substrate 2 has a thickness of 190 μm. The encapsulation layer 15 has a thickness of 90 μm. The diameter of the semiconductor wafer 1 has a diameter of 200 mm.

Points E, F, and G denote grinding operation at Process #8 performed with the grindstones 26 of #8000, #5000, and #2000, respectively. The results in FIG. 5 reveal that the warpage of the semiconductor wafer 1 decreases with improvement of the surface roughness of the semiconductor wafer 1.

For reliable chucking of the semiconductor wafer 1 during transportation of the semiconductor wafer 1, and stability of the semiconductor wafer 1 when the semiconductor wafer 1 is accommodated in a magazine, the surface roughness of the back surface 1a of the semiconductor wafer 1 is preferably not more than Ra=5 nm. If the semiconductor wafer 1 is warped more than Ra=5 nm, the chucking performance of the semiconductor wafer 1 during transportation of the semiconductor wafer 1 decreases so that the semiconductor wafer 1 may drop to be damaged or the posture of the semiconductor wafer 1 becomes unstable when the semiconductor wafer 1 is accommodated in the magazine. This tends to cause crack in the semiconductor wafer 1.

The minimum surface roughness should preferably be not less than Ra=1 nm. A surface having a surface roughness less than 1 nm does not serve as an effective gettering site that collects unnecessary metal impurity in the active region in which circuit elements are formed, and therefore the electrical properties of semiconductor devices 30 deteriorate. Thus, controlling the surface roughness of the ground back surface 1a of the semiconductor wafer 1 to be not larger than 5 nm will decrease the roughness of the back surface 1a, improving the ability of the semiconductor wafer 1 to resist against warpage.

The flexural modulus of the encapsulation layer 15 in intimate contact with the semiconductor wafer 1 is another factor that determines the warpage of the semiconductor wafer 1. FIG. 6 illustrates the relationship between the warpage of the semiconductor wafer 1 and the flexural modulus of the resin material of the encapsulation layer 15. FIG. 6 plates the flexural modulus of the encapsulation layer 15 as the abscissa and the warpage of the semiconductor wafer 1 as the ordinate.

The semiconductor wafer 1 under test has the following dimensions.

The semiconductor substrate 2 has a thickness of 90 μm. The encapsulation layer 15 has a thickness of 90 μm. The diameter of the semiconductor wafer 1 has a diameter of 200 mm. The plot in FIG. 6 reveals that the warpage of the semiconductor wafer 1 is a minimum when the flexural modulus is 14 Gpa. The warpage increases for the values of flexural modulus larger than 14 Gpa and smaller than 14 Gpa.

The flexural modulus of the encapsulation layer 15 directly affects the flexural strength of the semiconductor device 30, and therefore the flexural strength is a crucial consideration. FIG. 7 illustrates the relation between the flexural modulus of the resin material for the encapsulation layer 15 and the flexural strength of the semiconductor device 30. FIG. 7 plots the flexural modulus of the encapsulation layer 15 at room temperature as the abscissa and the bending fracture stress of the semiconductor device 30 as the ordinate.

Referring to FIG. 7, the flexural strength is a maximum when the flexural modulus of the resin material for the encapsulation layer 15 is 18 Gpa, and decreases for values of flexural modulus of higher than 18 Gpa and lower than 18 Gpa. In order to minimize the warpage of the semiconductor wafer 1, the flexural modulus of the encapsulation layer is preferably not smaller than 12 Gpa and not greater than 18 Gpa. Flexural modulus less than 12 Gpa offers warpage of the semiconductor in a reasonable range but the flexural strength of the semiconductor device 30 is too low. Flexural modulus greater than 18 Gpa offers the flexural strength of the semiconductor device 30 in a reasonable range but warpage of the semiconductor is too large.

The sealing resin having a flexural modulus in the aforementioned range may be made by adjusting the amount of filler that is mixed in the encapsulation resin material. For example, the encapsulation layer 15 having a flexural modulus in the aforementioned range may be formed of a thermosetting epoxy resin that contains silica filler by 80 to 85%.

The aforementioned semiconductor device 30 has substantially the same thickness as neighboring passive components mounted on a circuit board, so that when circuit boards are stacked one over the other, the overall thickness of the stacked structure may be small enough, implementing a thin structure of electronic equipment. Although the semiconductor substrate of the semiconductor wafer has been described as a bulk substrate of silicon, the semiconductor wafer may also include those in the form of silicon on insulator (SOI) and silicon on sapphire (SOS).

Claims

1. A method for manufacturing a semiconductor device including a circuit-fabricated side on which an encapsulation layer is formed, the method comprising:

placing a disc-shaped semiconductor wafer on a suction surface of a suction stage, the sucking area having a diameter in the range of 99 to 100.5% of a diameter of the semiconductor wafer;

holding the semiconductor wafer on the suction surface of the suction stage by suction; and

grinding a back surface of the semiconductor wafer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein grinding is performed such that a surface roughness of the back surface is not greater than 5 nm.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising forming the encapsulation layer having a flexural modulus not smaller than 12 Gpa and not larger than 18 Gpa at room temperature.