Semiconductor device
An uppermost one of multilayered electrode pads, on which a bump and a plating coat will be formed, is made of metal having high ionization tendency, particularly, Al. On the other hand, an uppermost one of multilayered electrode pads, on which none of the bump and the plating coat will be formed, is made of metal having low ionization tendency, particularly, Cu.
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(1) Field of the Invention
The present invention relates to a structure of a semiconductor device in which, for example, a plurality of semiconductor chips and ascribe grid are formed on a wafer-shaped substrate. In particular, the present invention relates to structures of electrode pads provided on such semiconductor chip and scribe grid.
(2) Description of the Related Art
Conventionally, there is manufactured a semiconductor device having a structure in which, for example, a plurality of semiconductor chips, each having a semiconductor circuit integrated thereon, and a scribe grid are formed on a wafer-shaped substrate. Herein, a region called the scribe grid is used as a “spacing” along which the wafer is cut to obtain a semiconductor circuit as a semiconductor chip. In order to determine whether or not the semiconductor circuit in the semiconductor chip is formed without fail, a plurality of elements called process control modules (hereinafter, referred to as “scribe PCMs”) are formed on the scribe grid.
Hereinafter, a description will be given of a conventional semiconductor device (refer to, e.g., JP2001-332577A) with reference to the drawings.
Each scribe PCM 4 includes multilayered electrode pads 5 for external electrical connection. Formation of such scribe PCM 4 on the scribe grid 3 makes it possible to examine quality of the semiconductor device as the entire wafer 1, particularly, electrical quality thereof. Although not illustrated in the drawings, a plurality of multilayered electrode pads for external electrical connection are also provided on each semiconductor chip 2.
As illustrated in
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
As illustrated in
In the conventional semiconductor device, however, the structure of the electrode pad 5 illustrated in
If the dicing cutter 10 deviates from an appropriate position as illustrated in
Thus, it is possible to prevent the bump 8 from being partially left at the edge portion. However, since the width of the dicing cutter 10, that is, a width of a “spacing” becomes large, the scribe grid 3 must be made larger in width in conjunction. As a result, the scribe grid 3 formed on the wafer 1 is larger in width than the aforementioned scribe grid 3 illustrated in
The present invention is devised in order to solve the aforementioned conventional problems. An object of the present invention is to provide a semiconductor device having the following advantages. That is, it is possible to prevent a “left bump” from being generated upon performance of dicing on an electrode pad of a scribe PCM, thereby to prevent occurrence of electrical leakage from such “left bump”. Further, it is possible to suppress reduction in number of semiconductor chips to be obtained from one wafer due to a widening of a scribe grid.
In order to accomplish this object, according to a first aspect of the present invention, a semiconductor device includes: a substrate; a semiconductor chip and a scribe grid formed on the substrate; and a plurality of multilayered electrode pads provided on the semiconductor chip and the scribe grid, respectively. Herein, the uppermost one of the multilayered electrode pads, on which a bump and a plating coat will be formed, is made of metal having ionization tendency higher than those of materials for the bump and the plating coat. Further, the uppermost one of the multilayered electrode pads, on which none of the bump and the plating coat will be formed, is made of metal having ionization tendency lower than those of the materials for the bump and the plating coat.
According to a second aspect of the present invention, the bump and the plating coat are formed on the electrode pad provided on the semiconductor chip, but are not formed on the electrode pad provided on the scribe grid.
According to a third aspect of the present invention, the metal having high ionization tendency is Al, and the metal having low ionization tendency is Cu.
According to the present invention, as described above, it is possible to form a bump on an electrode pad of a semiconductor chip without forming a bump on an electrode pad of a scribe PCM on a spacing for dicing.
Therefore, it is possible to prevent a “left bump” from being generated upon performance of dicing on an electrode pad of a scribe PCM, thereby to prevent occurrence of electrical leakage from such “left bump”.
Unlike a conventional technique, moreover, it is possible to suppress reduction in number of semiconductor chips to be obtained from one wafer due to a widening of a scribe grid.
In addition, it is possible to selectively perform plating on a plurality of electrode pads even in an electroless manner.
Hereinafter, a specific description will be given of preferred embodiments of the present invention with reference to the drawings.
First EmbodimentFirst, a description will be given of a semiconductor device according to a first embodiment of the present invention.
On the scribe PCM 4, two electrode pads 5 are laminated in the vertical direction. Herein, the uppermost one of the electrode pads 5 of the scribe PCM 4 is made of Cu.
On the semiconductor chip 2, three electrode pads 6 are laminated in a vertical direction. Herein, the uppermost one of the electrode pads 6 of the semiconductor chip 2 is made of Al.
In other words, an uppermost one of electrode pads (herein, the electrode pad 6 of the semiconductor chip 2), on which a bump and a plating coat will be formed by electroless plating (to be described later), is made of Al, and an uppermost one of electrode pads (herein, the electrode pad 5 of the scribe PCM 4), on which none of the bump and the plating coat will be formed by electroless plating, is made of Cu.
First, as illustrated in
Herein, the electrode pad 5 of the scribe PCM 4 is made of Cu. Ionization tendency of Cu is considerably lower than that of Zn; therefore, Cu itself is not dissolved in the electroless Zn plating solution as Cu ions in the displacement plating performed as the electroless plating. Accordingly, the Zn ions 7a in the electroless Zn plating solution are not deposited on the electrode pad 5 of the scribe PCM 4. In other words, the Zn plating layer 7 is not formed on the electrode pad 5 of the scribe PCM 4.
Next, as illustrated in
Also herein, the Zn plating layer 7 is not formed on the electrode pad 5 of the scribe PCM 4. Further, ionization tendency of Cu is lower than that of Ni; therefore, the Ni bump 8 is not formed on the electrode pad 5 of the scribe PCM 4.
Next, as illustrated in
Also herein, the Ni bump 8 is not formed on the electrode pad 5 of the scribe PCM 4. Therefore, even in the electroless Au plating solution, the Au plating layer 9 is not formed on the electrode pad 5 of the scribe PCM 4.
The aforementioned method is an electroless plating process for forming a bump on the electrode pad 6 of the semiconductor chip 2 without forming a bump on the electrode pad 5 of the scribe PCM 4.
It is apparent from
According to the first embodiment, as illustrated in an upper side of
Accordingly, the scribe grid 3 on the wafer 1 is reduced in area. On the other hand, an area for formation of semiconductor chips 2 each having a semiconductor integrated circuit provided thereon is increased. Thus, it is possible to suppress reduction in number of semiconductor chips 2 to be obtained from one wafer.
Second EmbodimentNext, a description will be given of a semiconductor chip according to a second embodiment of the present invention.
As described above with reference to
Claims
1. A semiconductor device comprising:
- a substrate comprising a semiconductor chip and a scribe grid; and
- a plurality of multilayered electrode pads provided on the semiconductor chip and the scribe grid, respectively, wherein
- the uppermost one of the multilayered electrode pads, on which a bump is formed, is made of metal having ionization tendency higher than that of material for the bump, and
- the uppermost one of the multilayered electrode pads, on which the bump is not formed, is made of metal having ionization tendency lower than that of the material for the bump.
2. The semiconductor device according to claim 1, wherein
- the bump is formed on the electrode pad provided on the semiconductor chip, and the bump is not formed on the electrode pad provided on the scribe grid.
3. The semiconductor device according to claim 1, wherein
- the bump is formed on the electrode pad provided on the semiconductor chip, and the electrode pad provided on the scribe grid is exposed.
4. The semiconductor device according to claim 1, wherein
- the metal of the uppermost one of the multilayered electrode pads, on which the bump is formed, is Al, and the metal of the uppermost one of the multilayered electrode pads, on which the bump is not formed, is Cu.
5. The semiconductor device according to claim 3, wherein
- the metal of the uppermost one of the multilayered electrode pads, on which the bump is formed, is Al, and the metal of the uppermost one of the multilayered electrode pads, on which the bump is not formed, is Cu.
6. The semiconductor device according to claim 2, wherein
- the metal of the uppermost one of the multilayered electrode pads provided on the semiconductor chip is Al, and the metal of the uppermost one of the multilayered electrode pads provided on the scribe grid is Cu.
7. A semiconductor chip comprising:
- a substrate having a plurality of multilayered electrode pads thereon, wherein
- the uppermost one of the multilayered electrode pads, on which a bump is formed, is made of metal having ionization tendency higher than that of material for the bump, and
- the uppermost one of the multilayered electrode pads, on which the bump is not formed, is made of metal having ionization tendency lower than that of the material for the bump.
8. The semiconductor chip according to claim 7, wherein
- the metal of the uppermost one of the multilayered electrode pads, on which the bump is formed, is Al, and the metal of the uppermost one of the multilayered electrode pads, on which the bump is not formed, is Cu.
Type: Application
Filed: Apr 20, 2007
Publication Date: Nov 1, 2007
Applicant: Matsushita Electric Industrial Co., Ltd. (Kadoma-shi)
Inventor: Takeshi Matsumoto (Osaka)
Application Number: 11/785,845
International Classification: H01L 23/544 (20060101);