With Peripheral Feature Due To Separation Of Smaller Semiconductor Chip From Larger Wafer (e.g., Scribe Region, Or Means To Prevent Edge Effects Such As Leakage Current At Peripheral Chip Separation Area) Patents (Class 257/620)
  • Patent number: 11404384
    Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: August 2, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Hsih-Yang Chiu
  • Patent number: 11373970
    Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
  • Patent number: 11367720
    Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 21, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 11296035
    Abstract: According to one embodiment, a semiconductor wafer includes a plurality of chip regions, a plurality of chip regions, a device layer, a first structure, and a second structure. The device layer includes an integrated circuit formed in each of the chip regions. The first structure is formed in the kerf region by filling a first cavity with a first filling material. The first cavity extends vertically with respect to a surface of a semiconductor substrate. The second structure is formed in the device layer by filling a second cavity with a second filling material. The second cavity extends vertically with respect to the surface of the semiconductor substrate.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Kioxia Corporation
    Inventor: Mika Fujii
  • Patent number: 11244876
    Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: February 8, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Matthias Klein, Andreas Zakrzewski, Richard Gruenwald
  • Patent number: 11241865
    Abstract: Electrochromic device laminates and their method of manufacture are disclosed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 8, 2022
    Assignee: SAGE ELECTROCHROMICS, INC.
    Inventors: Neil L. Sbar, John E. Van Dine, Michael A. McCoy
  • Patent number: 11239152
    Abstract: The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Otto Andreas Torreiter, Thomas Gentner, Martin Eckert
  • Patent number: 11216139
    Abstract: Provided is a touch display device including a folding area in an active area. The same pattern of touch electrodes can be maintained in both a reference area and a folding area and cracks on touch electrodes in the folding area, by applying a pattern structure of a touch insulation film disposed in the folding area. Therefore, the degradation of touch sensing performance, caused by cracks on the touch electrodes in the folding area, can be prevented and touch sensing sensitivity can be uniform in the reference area and the folding area, thereby improving touch sensing performance of the touch display device including the folding area.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 4, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Yangsik Lee, HwiDeuk Lee, TaeWoo Kim, YongChan Park
  • Patent number: 11201124
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and a first deep trench isolation (DTI) structure filled with a dielectric material formed on the semiconductor substrate. The first DTI structure is disposed in the first seal ring region and is extended into the semiconductor substrate. The semiconductor substrate has a pixel array region and a first seal ring region. The first seal ring region is proximate to an edge of the semiconductor substrate and surrounds the pixel array region. The first DTI structure is formed in the first seal ring region and surrounds the pixel array region.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 14, 2021
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Chia-Ying Liu, Wu-Zang Yang, Chia-Jung Liu, Chi-Chih Huang
  • Patent number: 11177355
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Tsung-Yuan Yu, Min-Chien Hsiao, Chao-Wen Shih
  • Patent number: 11164819
    Abstract: A semiconductor package includes a first wafer, a second wafer, and an interconnect. The first wafer includes a first die, a first encapsulating material encapsulating the first die, and a first redistribution structure disposed over the first die and the first encapsulating material. The second wafer includes a second die, a second encapsulating material encapsulating the second die, and a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure faces the first redistribution structure. The interconnect is disposed between the first wafer and the second wafer and electrically connecting the first redistribution structure and the second redistribution structure, wherein the interconnect includes a substrate and a plurality of through vias extending through the substrate for connecting the first redistribution structure and the second redistribution structure.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Cheng Tseng, Hao-Yi Tsai, Tin-Hao Kuo, Chia-Hung Liu, Chi-Hui Lai
  • Patent number: 11158555
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ting Kuo, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Chih-Hsuan Tai, Ying-Cheng Tseng
  • Patent number: 11152387
    Abstract: A semiconductor memory device including: a common source line; a substrate on the common source line; a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulation films arranged among the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulation films in the first direction; and a plurality of residual sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of residual sacrificial films.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Geun-won Lim
  • Patent number: 11145601
    Abstract: A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Sung Kim, Yun Hee Kim, Byung Moon Bae, Hyun Su Sim, Jun Ho Yoon, Jung Ho Choi
  • Patent number: 11139199
    Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hoon Han, Seokhwan Kim, Joodong Kim, Junyong Noh, Jaewon Seo
  • Patent number: 11119137
    Abstract: A microelectronic device includes a deep trench test structure in semiconductor material of a substrate. The deep trench test structure has pad trench segments with a liner of electrically non-conductive material and a trench fill material on the liner, extending to tops of the pad trench segments. The pad trench segments extend across a probe pad region; at least 20 microns in every lateral direction. The trench fill material at the top of the pad trench segments occupies at least 25 percent of the probe pad region. The liner may electrically isolate the trench fill material from the semiconductor material, or the deep trench test structure may include a contact trench segment wherein the trench fill material contacts the semiconductor material. The deep trench test structure may be probed on the pad trench segments to measure an impedance between the trench fill material and the semiconductor material.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Edward Lillibridge, Neil L Gardner
  • Patent number: 11107773
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Patent number: 11094671
    Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
  • Patent number: 11088094
    Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Chiang Lin, Yueh-Ting Lin, Hua-Wei Tseng, Li-Hsien Huang, Yu-Hsiang Hu
  • Patent number: 11069639
    Abstract: In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Danny Clavette, Carsten von Koblinski
  • Patent number: 11069647
    Abstract: A semiconductor wafer, a bonding structure, and a wafer bonding method are provided. In the semiconductor wafer, a bonding pad which is electrically connected to the interconnection structure is formed in the top cover layer, and a bonding alignment mark formed by a point array is disposed in the top cover layer. In this way, the bonding alignment mark is disposed in the top cover layer, and the top cover layer is not covered by another material layer, thereby facilitating recognition of the alignment pattern by the bonding device and increasing the alignment window in bonding process. Moreover, the bonding alignment mark is formed by a point array, thereby facilitating integration of the process for forming the bonding alignment mark with the bonding hole process and avoiding defects such as the dishing phenomenon in the manufacturing process.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 20, 2021
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yunpeng Zhou, Wanli Guo, Xing Hu, Yuheng Huang
  • Patent number: 11062981
    Abstract: A bidirectional switch includes: a first lateral transistor including a first semiconductor layer on the surface of a first conductive layer; a second lateral transistor including a second semiconductor layer on the surface of a second conductive layer; a connection member; a first conductor member; and a second conductor member. The connection member connects the first lateral transistor and the second lateral transistor together in anti-series. The first conductor member electrically connects the first source electrode of the first lateral transistor to the first conductive layer. The second conductor member electrically connects the second source electrode of the second lateral transistor to the second conductive layer.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 13, 2021
    Assignee: Panasonic Corporation
    Inventors: Yusuke Kinoshita, Yasuhiro Yamada, Takashi Ichiryu, Hidekazu Umeda
  • Patent number: 11056442
    Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 6, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Po-Hao Wang, Chun-Tang Lin, Shou-Qi Chang, Yu-Hsiang Hsieh
  • Patent number: 11037888
    Abstract: The present invention relates to a nitride-based electronic device and a method for manufacturing same, the nitride-based electronic device comprising a substrate, a metal electrode and a plurality of protection layers, wherein, among the protection layers, at least two protection layers covering one portion of the electrode so that one portion of the upper part of the electrode is exposed are configured so that the upper protection layer covers the end part of the lower protection layer so as to prevent the end part of the lower protection layer from being exposed.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 15, 2021
    Assignee: WAVICE INC.
    Inventors: Sang Min Lee, Hwang Sub Koo, Hyun Je Kim, Hee seok Jung
  • Patent number: 11037854
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 11031357
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Patent number: 11018088
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10957594
    Abstract: A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Hong Wei, Hung-Sheng Chen
  • Patent number: 10937751
    Abstract: Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 2, 2021
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jin Kuk Lee
  • Patent number: 10930602
    Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 23, 2021
    Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
  • Patent number: 10916514
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Sairam Agraharam
  • Patent number: 10916509
    Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 9, 2021
    Inventors: Yun-Rae Cho, Sundae Kim, Hyunggil Baek, Namgyu Baek, Seunghun Shin, Donghoon Won
  • Patent number: 10910342
    Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 2, 2021
    Assignees: IMEC VZW, UNIVERSITEIT GENT
    Inventors: Maria Op de Beeck, Bjorn Vandecasteele
  • Patent number: 10886236
    Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Hsih-Yang Chiu
  • Patent number: 10872852
    Abstract: A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 10854466
    Abstract: An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 1, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Susumu Obata, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 10854517
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10840131
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Patent number: 10818613
    Abstract: In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second device in a semiconductor wafer, and forming a street trench within the semiconductor wafer and between the first and second devices. The method continues with forming a dielectric skeleton structure over the semiconductor wafer, the dielectric skeleton structure laterally extending to at least partially cover the first and second devices, while also substantially filling the street trench. The method continues with thinning the semiconductor wafer from a backside to expose the dielectric skeleton structure in the street trench to form a first ultra-thin semiconductor component having the first device, and a second ultra-thin semiconductor component having the second device. The method can conclude with cutting through the dielectric skeleton structure to singulate the first and second ultra-thin semiconductor components.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Robert Montgomery
  • Patent number: 10818612
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A semiconductor device having a first surface and a second surface opposite to the first surface is provided. A plurality of through semiconductor vias (TSV) embedded in the semiconductor device is formed. A first seal ring is formed over the first surface of the semiconductor device. The first seal ring is adjacent to edges of the first surface and is physically in contact with the TSVs. A second seal ring is formed over the second surface of the semiconductor device. The second seal ring is adjacent to edges of the second surface and is physically in contact with the TSVs.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Patent number: 10784228
    Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming sawing grooves by sawing a wafer along individual chip boundaries in a downward direction from a top surface of the wafer by a thickness less than a wafer thickness, filling the sawing grooves with a molding material, forming a redistribution pattern, a passivation pattern, and an under bump metal (UBM) pattern on the wafer, bonding solder balls onto the UBM pattern, thinning the wafer based on a backgrinding process, and dividing the wafer into individual chips by sawing the molding material filled in the sawing grooves, in a downward direction.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 22, 2020
    Assignee: LBSEMICON CO., LTD.
    Inventors: Do Hyung Kim, Sang Hoon An
  • Patent number: 10770331
    Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 10763230
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Yi Yan, Hau Nguyen
  • Patent number: 10699975
    Abstract: A semiconductor device having a conductive pad is provided, wherein the conductive pad includes a substrate, a dielectric layer, a plurality of vias, and a patterned conductive pad. The dielectric layer is overlying the substrate. The vias are disposed in the dielectric layer. The patterned conductive pad is disposed over the dielectric layer. The conductive pad includes, from a top view, at least three first conductive strips spaced apart from each other, arranged in different rows. The conductive strips in different rows are electrically and physically connected by a plurality of conductive strings. The conductive strings between different rows of the conductive strips are arranged in a staggered manner. The vias are disposed under the conductive strips.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 30, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Lun-Lun Chen, Hsiu-Han Liao, Yao-Ting Tsai
  • Patent number: 10692848
    Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao Chun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 10665523
    Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 26, 2020
    Assignee: ADVANCE SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 10658300
    Abstract: A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Lyong Kim, Seung-Duk Baek
  • Patent number: 10651105
    Abstract: Provided is a semiconductor chip capable of withstanding damage such as cracks created in the fabrication process. A semiconductor chip according to the inventive concept includes: a semiconductor substrate including a residual scribe lane surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, and a cover protection layer formed integrally with a buffering protection layer covering a portion of the residual scribe lane, wherein the buffering protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extending protection layer extending along the residual scribe lane from the corner protection layer and in contact with the cover protection layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hee Kim, Yoon-Sung Kim, Byung-Moon Bae, Hyun-Su Sim
  • Patent number: 10643958
    Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-dae Kim, Hyung-gil Baek, Yun-rae Cho, Nam-gyu Baek
  • Patent number: 10622317
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) formed on a die. The IC includes first one or more electronic circuits and a seal ring structure. The first one or more electronic circuits are disposed on a first semiconductor substrate. The first semiconductor substrate is diced from a semiconductor wafer. The seal ring structure is configured to surround the first one or more electronic circuits. The seal ring structure is formed by patterning one or more layers of metal compounds on the semiconductor wafer using two or more circuit formation process steps. The seal ring structure includes a remaining portion of a complete seal ring structure after a dicing process step that cuts the complete seal ring structure. The complete seal ring structure has been formed on the semiconductor wafer to surround the first one or more electronic circuits and at least second one or more electronic circuits on a second semiconductor substrate that is diced from the semiconductor wafer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Abed Tatour, Carol Pincu