With Peripheral Feature Due To Separation Of Smaller Semiconductor Chip From Larger Wafer (e.g., Scribe Region, Or Means To Prevent Edge Effects Such As Leakage Current At Peripheral Chip Separation Area) Patents (Class 257/620)
  • Patent number: 10957594
    Abstract: A manufacturing method of a semiconductor chip is provided. The method includes: forming a first metal pattern over a substrate and within a chip region and a scribe line region of the substrate, wherein the chip region is surrounded by the scribe line region; forming a metal material layer on the first metal pattern; patterning the metal material layer to remove substantially all portions of the metal material layer within the scribe line region and a portion of the metal material layer within the chip region, so as to form a second metal pattern within the chip region; forming a third metal pattern, wherein the second metal pattern within the chip region is covered by the third metal pattern, and the third metal pattern is located over the first metal pattern within the scribe line region; and performing singulation along the scribe line region, to form the semiconductor chip.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Hong Wei, Hung-Sheng Chen
  • Patent number: 10937751
    Abstract: Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 2, 2021
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jin Kuk Lee
  • Patent number: 10930602
    Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 23, 2021
    Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
  • Patent number: 10916514
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Sairam Agraharam
  • Patent number: 10916509
    Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 9, 2021
    Inventors: Yun-Rae Cho, Sundae Kim, Hyunggil Baek, Namgyu Baek, Seunghun Shin, Donghoon Won
  • Patent number: 10910342
    Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 2, 2021
    Assignees: IMEC VZW, UNIVERSITEIT GENT
    Inventors: Maria Op de Beeck, Bjorn Vandecasteele
  • Patent number: 10886236
    Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Cih Kang, Hsih-Yang Chiu
  • Patent number: 10872852
    Abstract: A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 10854466
    Abstract: An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 1, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Susumu Obata, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 10854517
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10840131
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Patent number: 10818613
    Abstract: In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second device in a semiconductor wafer, and forming a street trench within the semiconductor wafer and between the first and second devices. The method continues with forming a dielectric skeleton structure over the semiconductor wafer, the dielectric skeleton structure laterally extending to at least partially cover the first and second devices, while also substantially filling the street trench. The method continues with thinning the semiconductor wafer from a backside to expose the dielectric skeleton structure in the street trench to form a first ultra-thin semiconductor component having the first device, and a second ultra-thin semiconductor component having the second device. The method can conclude with cutting through the dielectric skeleton structure to singulate the first and second ultra-thin semiconductor components.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Robert Montgomery
  • Patent number: 10818612
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A semiconductor device having a first surface and a second surface opposite to the first surface is provided. A plurality of through semiconductor vias (TSV) embedded in the semiconductor device is formed. A first seal ring is formed over the first surface of the semiconductor device. The first seal ring is adjacent to edges of the first surface and is physically in contact with the TSVs. A second seal ring is formed over the second surface of the semiconductor device. The second seal ring is adjacent to edges of the second surface and is physically in contact with the TSVs.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rung-De Wang, Chen-Hsun Liu, Chin-Yu Ku, Te-Hsun Pang, Chia-Hua Wang, Pei-Shing Tsai, Po-Chang Lin
  • Patent number: 10784228
    Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming sawing grooves by sawing a wafer along individual chip boundaries in a downward direction from a top surface of the wafer by a thickness less than a wafer thickness, filling the sawing grooves with a molding material, forming a redistribution pattern, a passivation pattern, and an under bump metal (UBM) pattern on the wafer, bonding solder balls onto the UBM pattern, thinning the wafer based on a backgrinding process, and dividing the wafer into individual chips by sawing the molding material filled in the sawing grooves, in a downward direction.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 22, 2020
    Assignee: LBSEMICON CO., LTD.
    Inventors: Do Hyung Kim, Sang Hoon An
  • Patent number: 10770331
    Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Patent number: 10763230
    Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Yi Yan, Hau Nguyen
  • Patent number: 10699975
    Abstract: A semiconductor device having a conductive pad is provided, wherein the conductive pad includes a substrate, a dielectric layer, a plurality of vias, and a patterned conductive pad. The dielectric layer is overlying the substrate. The vias are disposed in the dielectric layer. The patterned conductive pad is disposed over the dielectric layer. The conductive pad includes, from a top view, at least three first conductive strips spaced apart from each other, arranged in different rows. The conductive strips in different rows are electrically and physically connected by a plurality of conductive strings. The conductive strings between different rows of the conductive strips are arranged in a staggered manner. The vias are disposed under the conductive strips.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 30, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Lun-Lun Chen, Hsiu-Han Liao, Yao-Ting Tsai
  • Patent number: 10692848
    Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao Chun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 10665523
    Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 26, 2020
    Assignee: ADVANCE SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 10658300
    Abstract: A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Lyong Kim, Seung-Duk Baek
  • Patent number: 10651105
    Abstract: Provided is a semiconductor chip capable of withstanding damage such as cracks created in the fabrication process. A semiconductor chip according to the inventive concept includes: a semiconductor substrate including a residual scribe lane surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, and a cover protection layer formed integrally with a buffering protection layer covering a portion of the residual scribe lane, wherein the buffering protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extending protection layer extending along the residual scribe lane from the corner protection layer and in contact with the cover protection layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hee Kim, Yoon-Sung Kim, Byung-Moon Bae, Hyun-Su Sim
  • Patent number: 10643958
    Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-dae Kim, Hyung-gil Baek, Yun-rae Cho, Nam-gyu Baek
  • Patent number: 10622297
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10622317
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) formed on a die. The IC includes first one or more electronic circuits and a seal ring structure. The first one or more electronic circuits are disposed on a first semiconductor substrate. The first semiconductor substrate is diced from a semiconductor wafer. The seal ring structure is configured to surround the first one or more electronic circuits. The seal ring structure is formed by patterning one or more layers of metal compounds on the semiconductor wafer using two or more circuit formation process steps. The seal ring structure includes a remaining portion of a complete seal ring structure after a dicing process step that cuts the complete seal ring structure. The complete seal ring structure has been formed on the semiconductor wafer to surround the first one or more electronic circuits and at least second one or more electronic circuits on a second semiconductor substrate that is diced from the semiconductor wafer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Abed Tatour, Carol Pincu
  • Patent number: 10593640
    Abstract: In a described example, an apparatus includes a semiconductor substrate and at least two pillar bumps formed on an active surface of the semiconductor substrate, the at least two pillar bumps extending away from the active surface and having ends spaced from the semiconductor substrate with solder material at the ends of the at least two pillar bumps. At least one spacer is formed on the active surface of the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A package substrate has a die mount area on a first surface including portions receiving the ends of the at least two pillar bumps and receiving an end of the at least one spacer. Mold compound covers the semiconductor substrate, the at least two pillars, the at least one spacer, and at least a portion of the semiconductor substrate.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Raymond Maliclic Baello, Rafael Jose Lizares Guevara
  • Patent number: 10580744
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a die and a seal ring. The die is configured to be in and on the semiconductor substrate. The seal ring is configured to be on the semiconductor substrate and adjacent to the die. The seal ring forms an open loop.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10522508
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: December 31, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ian Hu, Ming-Han Wang, Tsun-Lung Hsieh, Chih-Yi Huang, Chih-Pin Hung
  • Patent number: 10504781
    Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xianjie Ning
  • Patent number: 10490513
    Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a first plurality of levels. Each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The structure also includes a crack stop area which includes a crack stop structure having a second plurality of levels. The interconnect and crack stop structures have an equal number of levels. A third plurality of the crack stop structure levels include a high modulus layer unique to the respective crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for fabricating the structure is described.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10475753
    Abstract: An integrated circuit (IC) structure includes an active area of the IC structure insulator positioned over a substrate. The active area includes an interconnection structure comprised of a plurality of levels, each of the interconnect structure levels including an interlayer dielectric (ILD) layer, a barrier layer disposed over the ILD and a conductor metal layer over the barrier layer. The IC structure also includes a crack stop area which includes a crack stop structure having an equal plurality of levels as the interconnect structure. Each of the crack stop structure levels includes at least one of the layers of the interconnection structure at a same level. At least one crack stop structure level also includes a high modulus layer unique to the crack stop structure level as compared to the corresponding interconnect structure level. In another aspect of the invention, a method for producing the structure is described.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li, Xiao Hu Liu, Griselda Bonilla
  • Patent number: 10461047
    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Dae-Woo Kim, Sujit Sharan, Sairam Agraharam
  • Patent number: 10438903
    Abstract: A semiconductor device includes a chip, a first kerf adjacent the chip and having a first main direction, a second kerf adjacent the chip and having a second main direction. A kerf junction is formed by the first kerf and the second kerf. A crack stop barrier is located along a first portion of a perimeter of the kerf junction.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventor: Sylvia Baumann Winter
  • Patent number: 10418335
    Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Rae Cho, Sundae Kim, Hyunggil Baek, Namgyu Baek, Seunghun Shin, Donghoon Won
  • Patent number: 10410898
    Abstract: A mounting member includes a body having a surface including a mounting surface on which an object is mountable, a channel arranged in the body, and a first layer arranged on an inner surface of the channel. The first layer has a higher thermal conductivity than the body.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: September 10, 2019
    Assignee: KYOCERA Corporation
    Inventor: Masahiko Horiuchi
  • Patent number: 10411175
    Abstract: There is provided a light emitting element package including: a light emitting laminate having a structure in which semiconductor layers are laminated and having a first main surface and a second main surface opposing the first main surface; a terminal unit disposed on an electrode disposed on the second main surface; a molded unit disposed on the second main surface of the light emitting laminate and allowing a portion of the terminal unit to be exposed; and a wavelength conversion unit disposed on the first main surface of the light emitting laminate.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il Woo Park, Cheol Jun Yoo
  • Patent number: 10388607
    Abstract: An embodiment of a device includes a package body having a first sidewall, a top surface, and a bottom surface, and multiple pads that are exposed at the first sidewall and that are electrically coupled to one or more electrical components embedded within the package body. The device also includes a package surface conductor coupled to the first sidewall. The package surface conductor extends between and electrically couples the multiple pads, and the package surface conductor is formed from a first surface layer and a second surface layer formed on the first surface layer. The first surface layer directly contacts the multiple pads and the first sidewall and is formed from one or more electrically conductive first materials, and the second surface layer is formed from one or more second materials that are significantly more resistive to materials that can be used to remove the first materials.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: August 20, 2019
    Assignee: NXP USA, Inc.
    Inventors: Zhiwei Gong, Scott M. Hayes, Michael B. Vincent
  • Patent number: 10361151
    Abstract: A wiring board includes a low CTE (coefficient of thermal expansion) and high thermal conductivity isolator incorporated in a resin laminate by an adhesive and a bridging element disposed over the isolator and the resin laminate and electrically coupled to a first routing circuitry on the isolator and a second routing circuitry on the resin laminate. The isolator provides CTE-compensated contact interface for a semiconductor chip to be assembled thereon, and also provides primary heat conduction for the chip. The bridging element offers a reliable connecting channel for interconnecting contact pads on the isolator to terminal pads on the resin laminate.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: July 23, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10355472
    Abstract: An over temperature protection circuit includes a temperature sensor unit, a detection unit, and a filter unit. The temperature sensor unit detects a temperature and outputs a temperature detection signal. The detection unit has a first threshold for determining whether a temperature state is a normal state, and a second threshold for determining whether the temperature state is an over temperature state; and operates with respect to an internal ground. The detection unit determines the normal state or the over temperature state, based on the level of the temperature detection signal with respect to the first threshold and the second threshold; and outputs a state signal. The filter unit filters out a change of the state signal, produced in accordance with a change of the internal ground.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideki Iwata
  • Patent number: 10319681
    Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10319701
    Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Chung-Shi Liu
  • Patent number: 10314161
    Abstract: A circuit board, on which a packaged semiconductor integrated circuit is to be mounted, includes a substrate, a heat-dissipating connection pad, and a first open area. The substrate includes a substrate body having a main surface, a metal layer located on the main surface, and an insulating layer located on the metal layer. In the heat-dissipating connection pad, the metal layer is exposed from an opening in the insulating layer. The heat-dissipating connection pad is connectable to a heat-dissipating unit of the semiconductor integrated circuit via a bond. In the first open area, the metal layer is exposed from an opening in the insulating layer located outboard with respect to a periphery of the heat-dissipating connection pad.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 4, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinji Matsunaga
  • Patent number: 10304793
    Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsing Lu, Pei-Haw Tsao
  • Patent number: 10304783
    Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 10290559
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 10283501
    Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: May 7, 2019
    Assignee: GaN Systems Inc.
    Inventors: Thomas Macelwee, Greg P. Klowak, Howard Tweddle
  • Patent number: 10265805
    Abstract: Disclosed herein is a method of processing a workpiece having a plurality of streets provided on a face side thereof, the method including: a laser beam applying step of applying a laser beam having a wavelength that is transmittable through the workpiece along the streets while focusing the laser beam at a point within the workpiece, thereby forming modified layers in the workpiece along the streets and cracks extending from the modified layers to the face side; and a cutting step of, thereafter, cutting the workpiece from a reverse side thereof along the streets while supplying the workpiece with a cutting fluid, thereby removing the modified layers from the workpiece.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 23, 2019
    Assignee: DISCO CORPORATION
    Inventor: Yoshiaki Yodo
  • Patent number: 10249506
    Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 2, 2019
    Inventors: Thomas Macelwee, Greg P. Klowak, Howard Tweddle
  • Patent number: 10242148
    Abstract: The invention provides an integrated circuit. The integrated circuit includes a substrate having a first cell region and a second cell region. A first electronic device is disposed on the substrate in the first cell region. A second electronic device is disposed on the substrate in the second cell region. A first bottommost metal pattern overlaps the first cell region and the second cell region. The first bottommost metal pattern is coupled to the first electronic device and the second electronic device.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: March 26, 2019
    Assignee: MEDIATEK INC.
    Inventor: Lichiu Weng
  • Patent number: 10217723
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 26, 2019
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Patent number: RE47840
    Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: February 4, 2020
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Yoshiro Riho