Abstract: The present invention relates to an integrated electronic circuit and method of making comprising a first transistor (1) and a ferroelectric capacitor (2). The ferroelectric capacitor (2) comprises a first electrode layer composed of a non-ferroelectric material, a ferroelectric interlayer having a thickness that is less than the thickness of the first electrode layer, and a second electrode layer composed of a non-ferroelectric material, wherein the ferroelectric interlayer is arranged between the first electrode layer and the second electrode layer, and the first electrode layer is electrically conductively connected to a gate terminal of the first transistor (1).

Abstract: An alignment module for housing and cleaning masks. The alignment module comprises a mask stocker, a cleaning chamber, an alignment chamber, an alignment stage a transfer robot. The mask stocker is configured to house a mask cassette configured to store a plurality of masks. The cleaning chamber is configured to clean the plurality of masks by providing one or more cleaning gases into a chamber after a mask is inserted into the cleaning chamber. The alignment stage is configured to support a carrier and a substrate. The transfer robot is configured to transfer a mask from one or more of the alignment stage and the mask stocker to the cleaning chamber.

Abstract: An Fe—Co—Al alloy magnetic thin film contains, in terms of atomic ratio, 20% to 30% Co and 1.5% to 2.5% Al. The Fe—Co—Al alloy magnetic thin film has a crystallographic orientation such that the (100) plane is parallel to a substrate surface and the <100> direction is perpendicular to the substrate surface. The Fe—Co—Al alloy magnetic thin film has good magnetic properties, that is, a magnetization of 1440 emu/cc or more, a coercive force of less than 100 Oe, a damping factor of less than 0.01, and an FMR linewidth ?H at 30 GHz of less than 70 Oe.

Abstract: This method for producing a semiconductor device comprises: a first step wherein a plurality of semiconductor chips are affixed onto a supporting substrate such that circuit surfaces of the semiconductor chips face the supporting substrate; a second step wherein a plurality of sealed layers are formed at intervals by applying the sealing resin onto the semiconductor chips by three-dimensional modeling method, each sealed layer containing one or more semiconductor chips embedded in a sealing resin; a third step wherein the sealed layers are cured or solidified; and a fourth step wherein sealed bodies are obtained by separating the cured or solidified sealed layers from the supporting substrate.

Abstract: A solar cell module includes serially connected solar cells. A solar cell includes a carrier that is attached to the backside of the solar cell. Solar cells are attached to a top cover, and vias are formed through the carriers of the solar cells. A solar cell is electrically connected to an adjacent solar cell in the solar cell module with metal connections in the vias.

Abstract: A method comprises: patterning a substrate, including a conductive region, with photoresist exposed by lithography, where the substrate is mounted on a handle substrate; forming a comb structure with conductive fingers on the substrate by at least removing a portion of the conductive region of the substrate; removing the photoresist; forming, one atomic layer at a time, at least one atomic layer of at least one conductor over at least one sidewall of each conductive finger; attaching at least one insulator layer to the comb structure, and the substrate from which the comb structure is formed; and removing the handle substrate.

Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.

Abstract: According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

Abstract: The present invention relates to a method for forming a layer, to be patterned, of an element by using a fluorinated material, which has orthogonality, and a solvent, the method comprising: a first step of printing with the fluorinated material so as to form, on a surface of a substrate, a mask template provided with an exposure part and a non-exposure part; a second step of coating the exposure part with a material to be patterned; a the third step of lifting-off the non-exposure part with the fluorinated solvent so as to form the layer to be patterned in the exposure part.

Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

Abstract: The invention relates to a method for producing a support for the production of a semiconductor structure based on group III nitrides, characterised in that the method comprises the steps of: formation (100) of a buffer layer (20) on a substrate (10), said buffer layer comprising an upper surface layer based on group III nitrides, and deposition (200) of a crystalline layer (30) on the buffer layer, said crystalline layer being deposited from silicon atoms so as to cover the entire surface of the upper layer based on group III nitrides. The invention also relates to a support obtained by the method, to a semiconductor structure based on the support, and to the method for the production thereof.

Abstract: A mass flow sensor module and method of manufacture thereof are provided, wherein a semiconductor sensor die is integrated within an enhanced molded housing structure that maintains an air tight seal and protects the die from abrasive wear, and which also provides laminar flow of the liquid gas to be sensed. Since the die is embedded in the substrate; there is no need for a spacer for reducing die thickness induced flow turbulence. Moreover, the die surface is at the same level as the top surface of the substrate, such that there is no performance impact due to die thickness variation and therefore no die attach bond line thickness control requirement. In one embodiment, a thermal enhancement capability is provided.

Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

Abstract: A coating and developing apparatus 2 includes a first protection processing unit U01, a film forming unit U02, a first cleaning processing unit U03 and a control unit U08. The control unit U08 is configured to control the first protection processing unit U01 to form a first protective film on a peripheral portion Wc of a wafer W, control the film forming unit U02 to form a resist film on a front surface Wa of the wafer W, control the first cleaning processing unit U03 to supply a first cleaning liquid for removing the resist film to the peripheral portion Wc, control the first cleaning processing unit U03 to supply a second cleaning liquid for removing a metal component to the peripheral portion Wc, and control the first cleaning processing unit U03 to supply a third cleaning liquid for removing the first protective film PF1 to the peripheral portion Wc.

Abstract: An integrated circuit package including at least one integrated circuit component, at least one electromagnetic interference shielding layer and an insulating encapsulation is provided. The at least one integrated circuit component includes an active surface, a plurality of sidewalls connected to the active surface and a plurality of conductive pillars protruding from the active surface. The at least one electromagnetic interference shielding layer covers the sidewalls of the at least one integrated circuit component, and the at least one electromagnetic interference shielding layer is electrically grounded. The insulating encapsulation encapsulates the at least one integrated circuit component and the at least one electromagnetic interference shielding layer, and the conductive pillars of the at least one integrated circuit component are accessibly exposed by the insulating encapsulation. Methods of fabricating the integrated circuit package are also provided.

Abstract: A display device includes a first pixel, a second pixel, a first substrate, and a second substrate. The first pixel includes a first pixel electrode, a first conductive film, and a first transistor. The first pixel electrode is electrically connected to the first transistor. The first conductive film includes a region functioning as a common electrode. The second pixel includes a second pixel electrode, a second conductive film, and a second transistor. The second pixel electrode is electrically connected to the second transistor. The second conductive film includes a region functioning as a common electrode. The first conductive film and the second pixel electrode are provided on the same plane. A first insulating film is provided over the first conductive film and the second pixel electrode. The first pixel electrode and the second conductive film are provided over the first insulating film.

Abstract: Systems and methods for lead frame-based chip carriers for use with MEMS transducers. One embodiment provides a method for manufacturing a MEMS microphone package. In one exemplary embodiment, the method includes flip chip bonding a first plurality of I/O pads on an application specific integrated circuit to a plurality of traces on a lead frame. The method further includes removing at least one of the plurality of traces such that at least one of the first plurality of I/O pads is electrically isolated from the lead frame. The method further includes bonding the lead frame to a lid and electrically connecting, via at least one wire bond, a MEMS microphone mounted to the lid to the application specific integrated circuit using a second plurality of I/O pads of the application specific integrated circuit. The method further includes bonding a substrate to the lead frame to form an air tight volume within the lid.

Abstract: Selectively annealing one or more materials of a composite cathode occurs through selection of composite cathode material composition, particle shape and size of composite cathode material, microwave waveform, microwave duration, and environment. Electron conductor material and ion conducting material may be annealed in a staged process to substantially reduce cross contamination of resulting electron and ion conducting pathways while increasing the number or electron and ion conducting pathways in a composite cathode.

Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.

Abstract: A method for preparing CIGS absorber layers using CIGS nanoparticles on a substrate comprises one or more annealing steps that involve heating the CIGS nanoparticle film(s) to dry the film and possibly to fuse the CIGS nanoparticles together to form CIGS crystals. Generally, at least the final annealing step will induce particle fusion to form CIGS crystals. Reactive gas annealing has been found to facilitate the growth of larger grains in the resulting CIGS absorber layers and lead to improved photovoltaic performance of those layers. It is suspected that the presence of carbon in CIGS nanoparticle films hinders grain growth and limits the size of crystals which can be obtained in CIGS films upon annealing. It has been discovered that exposing the CIGS nanoparticle films to a reactive atmosphere containing sulfur can decrease the amount of carbon in the film, resulting in the growth of larger CIGS crystals upon annealing.

Abstract: A transmitter to generate a signal to be read by a reader is described. The transmitter includes a driver circuit; and at least two inductors connected to the driver circuit. The driver circuit controls the current flow through the inductor and the current flow results in a signal such that the signal strength is above the detection limit of the reader for each of the inductors which may have at least one null region. Additionally, the inductors are positioned such that the null regions of the inductors do not overlap.

Abstract: Improved high energy capacity designs for lithium ion batteries are described that take advantage of the properties of high specific capacity anode active compositions and high specific capacity cathode active compositions. In particular, specific electrode designs provide for achieving very high energy densities. Furthermore, the complex behavior of the active materials is used advantageously in a radical electrode balancing design that significantly reduced wasted electrode capacity in either electrode when cycling under realistic conditions of moderate to high discharge rates and/or over a reduced depth of discharge.

Abstract: A method of manufacturing a stacked semiconductor package includes forming a semiconductor package, the semiconductor package having one or more semiconductor chips on an upper surface of a printed circuit board (PCB), and a mold layer covering the upper surface of the PCB, marking the semiconductor package with an identification mark by scanning a laser of a laser supply apparatus onto the semiconductor package, controlling a focus level of the laser, and performing laser drilling on the mold layer of the semiconductor package to form openings.

Abstract: Presented herein is a device comprising an image sensor having a plurality of pixels disposed in a substrate and configured to sense light through a back side of the substrate and an RDL disposed on a front side of the substrate and having a plurality of conductive elements disposed in one or more dielectric layers. A sensor shield is disposed over the back side of the substrate and extending over the image sensor. At least one via contacts the sensor shield and extends from the sensor shield through at least a portion of the RDL and contacts at least one of the plurality of conductive elements.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

Abstract: A head gimbal assembly for a disk drive includes a flexure tail terminal region having flexure bond pads in electrical communication with the head. Each of the flexure bond pads includes a widened region of a corresponding one of a plurality of electrical traces in a conductive layer, and a discontinuous bond pad backing island in a structural layer that overlaps the widened region. The flexure tail terminal region also includes a plurality of discontinuous edge stiffener islands in the structural layer that do not overlap the widened region of any flexure bond pad, and that are disposed no more than 50 microns from one of the two opposing longitudinal outer edges of the flexure tail terminal region. At least one of the plurality of discontinuous bond pad backing islands is disposed no more than 50 microns from one of the two opposing longitudinal outer edges.

Abstract: A semiconductor device according to an embodiment comprises a base layer. A material layer is provided on the base layer. A lower layer portion is provided in lower parts of trenches or holes formed in the material layer and has a crystal structure in a direction not perpendicular to a surface of the base layer. An upper layer portion is provided on the lower layer portion in the trenches or the holes and has a crystal structure in a direction substantially perpendicular to the surface of the base layer.

Abstract: The present invention relates to a method for forming a silicon oxide nanopattern, in which the method can be used to easily form a nanodot or nanohole-type nanopattern, and a metal nanopattern formed by using the same can be properly applied to a next-generation magnetic recording medium for storage information, etc., a method for forming a metal nanopattern, and a magnetic recording medium for information storage using the same. The method for forming a silicon oxide nanopattern includes the steps of forming a block copolymer thin film including specific hard segments and soft segments containing a (meth)acrylate-based repeating unit on silicon oxide of a substrate; conducting orientation of the thin film; selectively removing the soft segments from the block copolymer thin film; and conducting reactive ion etching of silicon oxide using the block copolymer thin film from which the soft segments are removed, as a mask to form a silicon oxide nanodot or nanohole pattern.

Abstract: Provided is a method including forming a film including a predetermined element, oxygen and at least one element selected from a group consisting of nitrogen, carbon and boron on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate wherein the source gas contains the predetermined element, chlorine and oxygen with a chemical bond of the predetermined element and oxygen, and supplying a reactive gas to the substrate wherein the reactive gas contains the at least one element selected from the group consisting of nitrogen, carbon and boron.

Abstract: A method of manufacturing a display panel, the method including attaching a first carrier substrate to a first substrate; attaching a second carrier substrate to a second substrate; forming a thin film transistor (TFT) array on the first substrate; forming a color filter (CF) array on the second substrate; and coupling the first substrate with the second substrate to provide coupled first and second substrates, the first substrate being bonded to the first carrier substrate with a first intermediate layer therebetween, the second substrate being bonded to the second carrier substrate with a second intermediate layer therebetween, and an adhesive force of the first intermediate layer being weaker than an adhesive force of the second intermediate layer.

Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.

Abstract: An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.

Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

Abstract: A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.

Abstract: An integrated, integrated circuit singulation system is provided including scribing a substrate using mechanical cutting or a plurality of passes of laser cutting, and dicing the substrate using mechanical cutting or laser cutting.

Abstract: An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.

Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.

Abstract: Disclosed herein is a method of disposing phosphor layers, which can prevent damage to phosphors and also effectively dispose phosphor layers at desired locations of Light-Emitting Diodes (LEDs) when the phosphor layers are detached and disposed at the top surfaces of the LEDs. According to an embodiment, phosphor layers fabricated by filling phosphor layer pattern holes within an area of the vertical frame with a phosphor solution are detached from the phosphor layer pattern holes by applying force downwardly or upwardly in a vertical manner.

Abstract: Disclosed is an apparatus and method for manufacturing a thin film type solar cell, which enables the enhancement of productivity, the apparatus for manufacturing a thin film type solar cell including a first electrode forming unit; a first separation part; an optoelectric conversion layer forming unit; a contact line forming unit; a printing unit; and an etching process unit, wherein the etching process unit removes the optoelectric conversion layer in a second separation part to expose the first electrode in the second separation part through a wet etching process.

Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.

Abstract: Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

Abstract: A method of manufacturing a liquid crystal display having a touch sensor, the method including forming a plurality of thin film transistors on a first substrate, forming a plurality of pixel electrodes each coupled to a corresponding one of the thin film transistors, forming an insulating layer on the pixel electrodes, and forming, on the insulating layer, a plurality of first touch electrodes each having openings formed therein and a plurality of driving lines coupled to the first touch electrodes.

Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.

Abstract: A manufacturing method of a light-emitting device includes: a die-bonding process in which a semiconductor light emitting element is placed on a bonding target member via an adhesive containing a silicone resin so that a surface opposite to an exposure surface faces the bonding target member, and the adhesive is heated to bond the semiconductor light emitting element to the bonding target member; and a wire-bonding process in which a wire is connected to the exposure surface. The semiconductor light emitting element includes a laminated semiconductor layer having a light emitting layer and an electrode including a metal layer containing Au and provided on the laminated semiconductor layer and a covering layer containing Ni or Ta and covering the metal layer, the thickness of the covering layer being set smaller than 100 nm and the exposure surface to expose the covering layer to the outside being formed.

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract: This disclosure discloses a method of manufacturing a light-emitting device, comprising proving a single growth substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface, wherein the light-emitting stacks are electrically connected to each other in series via a first electrical connecting structure; forming an electronic device on the second major surface; and forming a second electrical connecting structure extending from the first major surface to the second major surface and electrically connecting the first light-emitting stacks and the electronic device, wherein the electronic device comprises a resistance, an inductance, capacitance, or a rectifying device, and wherein the material of the resistance comprises tantalum nitride (TaN), silicon-chromium alloy (SiCr), or nickel-chromium alloy (NiCr).

Abstract: MEMS and fabrication techniques for positioning the center of mass of released structures in MEMS are provided. A MEMS device includes a substrate and a released structure connected to the substrate via a flexure. The released structure includes a frame rotatable with respect to the substrate, and an elongate first member having a longitudinal axis extending perpendicularly from an undersurface of the frame and a free end remote from the frame. A recess is formed in an end face of the free end. The recess has a longitudinal axis substantially parallel to the longitudinal axis of the first member and a transverse area smaller than an area of the end face.

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer stack and a mirror. The semiconductor layer stack has an active layer for generating electromagnetic radiation. The minor is arranged on an underside of the semiconductor layer stack. The mirror has a first region and a second region, the first region containing silver and the second region containing gold. A method of producing such a semiconductor chip is also defined.