Processes Or Apparatus Adapted For Manufacture Or Treatment Of Semiconductor Or Solid-state Devices Or Of Parts Thereof (epo) Patents (Class 257/E21.001)

  • Patent number: 10193014
    Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: January 29, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Mingwei Zhu, Nag B. Patibandla, Rongjun Wang, Daniel Lee Diehl, Vivek Agrawal, Anantha Subramani
  • Patent number: 10139732
    Abstract: A coating and developing apparatus 2 includes a first protection processing unit U01, a film forming unit U02, a first cleaning processing unit U03 and a control unit U08. The control unit U08 is configured to control the first protection processing unit U01 to form a first protective film on a peripheral portion Wc of a wafer W, control the film forming unit U02 to form a resist film on a front surface Wa of the wafer W, control the first cleaning processing unit U03 to supply a first cleaning liquid for removing the resist film to the peripheral portion Wc, control the first cleaning processing unit U03 to supply a second cleaning liquid for removing a metal component to the peripheral portion Wc, and control the first cleaning processing unit U03 to supply a third cleaning liquid for removing the first protective film PF1 to the peripheral portion Wc.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 27, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shinichiro Kawakami, Hiroshi Mizunoura, Shinichi Hatakeyama
  • Patent number: 10134685
    Abstract: An integrated circuit package including at least one integrated circuit component, at least one electromagnetic interference shielding layer and an insulating encapsulation is provided. The at least one integrated circuit component includes an active surface, a plurality of sidewalls connected to the active surface and a plurality of conductive pillars protruding from the active surface. The at least one electromagnetic interference shielding layer covers the sidewalls of the at least one integrated circuit component, and the at least one electromagnetic interference shielding layer is electrically grounded. The insulating encapsulation encapsulates the at least one integrated circuit component and the at least one electromagnetic interference shielding layer, and the conductive pillars of the at least one integrated circuit component are accessibly exposed by the insulating encapsulation. Methods of fabricating the integrated circuit package are also provided.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 10128271
    Abstract: A display device includes a first pixel, a second pixel, a first substrate, and a second substrate. The first pixel includes a first pixel electrode, a first conductive film, and a first transistor. The first pixel electrode is electrically connected to the first transistor. The first conductive film includes a region functioning as a common electrode. The second pixel includes a second pixel electrode, a second conductive film, and a second transistor. The second pixel electrode is electrically connected to the second transistor. The second conductive film includes a region functioning as a common electrode. The first conductive film and the second pixel electrode are provided on the same plane. A first insulating film is provided over the first conductive film and the second pixel electrode. The first pixel electrode and the second conductive film are provided over the first insulating film.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Daisuke Kubota, Shunpei Yamazaki
  • Patent number: 10057688
    Abstract: Systems and methods for lead frame-based chip carriers for use with MEMS transducers. One embodiment provides a method for manufacturing a MEMS microphone package. In one exemplary embodiment, the method includes flip chip bonding a first plurality of I/O pads on an application specific integrated circuit to a plurality of traces on a lead frame. The method further includes removing at least one of the plurality of traces such that at least one of the first plurality of I/O pads is electrically isolated from the lead frame. The method further includes bonding the lead frame to a lid and electrically connecting, via at least one wire bond, a MEMS microphone mounted to the lid to the application specific integrated circuit using a second plurality of I/O pads of the application specific integrated circuit. The method further includes bonding a substrate to the lead frame to form an air tight volume within the lid.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 21, 2018
    Assignee: Robert Bosch GmbH
    Inventor: Jay Scott Salmon
  • Patent number: 10044028
    Abstract: Selectively annealing one or more materials of a composite cathode occurs through selection of composite cathode material composition, particle shape and size of composite cathode material, microwave waveform, microwave duration, and environment. Electron conductor material and ion conducting material may be annealed in a staged process to substantially reduce cross contamination of resulting electron and ion conducting pathways while increasing the number or electron and ion conducting pathways in a composite cathode.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 7, 2018
    Assignee: ITN ENERGY SYSTEMS, INC.
    Inventor: Andrew Colclasure
  • Patent number: 9929310
    Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 27, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Mingwei Zhu, Nag B. Patibandia, Rongjun Wang, Daniel Lee Diehl, Vivek Agrawal, Anantha Subramani
  • Patent number: 9922899
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 20, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Patent number: 9887304
    Abstract: A method for preparing CIGS absorber layers using CIGS nanoparticles on a substrate comprises one or more annealing steps that involve heating the CIGS nanoparticle film(s) to dry the film and possibly to fuse the CIGS nanoparticles together to form CIGS crystals. Generally, at least the final annealing step will induce particle fusion to form CIGS crystals. Reactive gas annealing has been found to facilitate the growth of larger grains in the resulting CIGS absorber layers and lead to improved photovoltaic performance of those layers. It is suspected that the presence of carbon in CIGS nanoparticle films hinders grain growth and limits the size of crystals which can be obtained in CIGS films upon annealing. It has been discovered that exposing the CIGS nanoparticle films to a reactive atmosphere containing sulfur can decrease the amount of carbon in the film, resulting in the growth of larger CIGS crystals upon annealing.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: February 6, 2018
    Inventors: Paul Kirkham, Cary Allen, Stephen Whitelegg
  • Patent number: 9864985
    Abstract: A transmitter to generate a signal to be read by a reader is described. The transmitter includes a driver circuit; and at least two inductors connected to the driver circuit. The driver circuit controls the current flow through the inductor and the current flow results in a signal such that the signal strength is above the detection limit of the reader for each of the inductors which may have at least one null region. Additionally, the inductors are positioned such that the null regions of the inductors do not overlap.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: January 9, 2018
    Assignee: SAMSUNG PAY, INC.
    Inventor: George Wallner
  • Patent number: 9780358
    Abstract: Improved high energy capacity designs for lithium ion batteries are described that take advantage of the properties of high specific capacity anode active compositions and high specific capacity cathode active compositions. In particular, specific electrode designs provide for achieving very high energy densities. Furthermore, the complex behavior of the active materials is used advantageously in a radical electrode balancing design that significantly reduced wasted electrode capacity in either electrode when cycling under realistic conditions of moderate to high discharge rates and/or over a reduced depth of discharge.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 3, 2017
    Assignee: Zenlabs Energy, Inc.
    Inventors: Charan Masarapu, Yogesh Kumar Anguchamy, Yongbong Han, Haixia Deng, Sujeet Kumar, Herman A. Lopez
  • Patent number: 9673185
    Abstract: A method of manufacturing a stacked semiconductor package includes forming a semiconductor package, the semiconductor package having one or more semiconductor chips on an upper surface of a printed circuit board (PCB), and a mold layer covering the upper surface of the PCB, marking the semiconductor package with an identification mark by scanning a laser of a laser supply apparatus onto the semiconductor package, controlling a focus level of the laser, and performing laser drilling on the mold layer of the semiconductor package to form openings.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 6, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-ho Joung, Jong-gyu Kim
  • Patent number: 9614000
    Abstract: Presented herein is a device comprising an image sensor having a plurality of pixels disposed in a substrate and configured to sense light through a back side of the substrate and an RDL disposed on a front side of the substrate and having a plurality of conductive elements disposed in one or more dielectric layers. A sensor shield is disposed over the back side of the substrate and extending over the image sensor. At least one via contacts the sensor shield and extends from the sensor shield through at least a portion of the RDL and contacts at least one of the plurality of conductive elements.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Fann Ting, Feng-Chi Hung, Jhy-Jyi Sze, Ching-Chun Wang, Dun-Nian Yaung
  • Patent number: 9607838
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 9601375
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: March 21, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Jungrae Park, Ajay Kumar, James S. Papanu, Prabhat Kumar
  • Patent number: 9530439
    Abstract: A head gimbal assembly for a disk drive includes a flexure tail terminal region having flexure bond pads in electrical communication with the head. Each of the flexure bond pads includes a widened region of a corresponding one of a plurality of electrical traces in a conductive layer, and a discontinuous bond pad backing island in a structural layer that overlaps the widened region. The flexure tail terminal region also includes a plurality of discontinuous edge stiffener islands in the structural layer that do not overlap the widened region of any flexure bond pad, and that are disposed no more than 50 microns from one of the two opposing longitudinal outer edges of the flexure tail terminal region. At least one of the plurality of discontinuous bond pad backing islands is disposed no more than 50 microns from one of the two opposing longitudinal outer edges.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: December 27, 2016
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yih-Jen D. Chen, Tzong-Shii Pan
  • Patent number: 9520560
    Abstract: A semiconductor device according to an embodiment comprises a base layer. A material layer is provided on the base layer. A lower layer portion is provided in lower parts of trenches or holes formed in the material layer and has a crystal structure in a direction not perpendicular to a surface of the base layer. An upper layer portion is provided on the lower layer portion in the trenches or the holes and has a crystal structure in a direction substantially perpendicular to the surface of the base layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: December 13, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Aoi Hidaka
  • Patent number: 9495991
    Abstract: The present invention relates to a method for forming a silicon oxide nanopattern, in which the method can be used to easily form a nanodot or nanohole-type nanopattern, and a metal nanopattern formed by using the same can be properly applied to a next-generation magnetic recording medium for storage information, etc., a method for forming a metal nanopattern, and a magnetic recording medium for information storage using the same. The method for forming a silicon oxide nanopattern includes the steps of forming a block copolymer thin film including specific hard segments and soft segments containing a (meth)acrylate-based repeating unit on silicon oxide of a substrate; conducting orientation of the thin film; selectively removing the soft segments from the block copolymer thin film; and conducting reactive ion etching of silicon oxide using the block copolymer thin film from which the soft segments are removed, as a mask to form a silicon oxide nanodot or nanohole pattern.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 15, 2016
    Assignees: LG CHEM, LTD., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Yang Kyoo Han, Je Gwon Lee, Hyun Jin Lee, No Ma Kim, Sung Soo Yoon, Eun Ji Shin, Yeon Sik Jung
  • Patent number: 9443718
    Abstract: Provided is a method including forming a film including a predetermined element, oxygen and at least one element selected from a group consisting of nitrogen, carbon and boron on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate wherein the source gas contains the predetermined element, chlorine and oxygen with a chemical bond of the predetermined element and oxygen, and supplying a reactive gas to the substrate wherein the reactive gas contains the at least one element selected from the group consisting of nitrogen, carbon and boron.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 13, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Katsuyoshi Harada, Yoshiro Hirose, Atsushi Sano
  • Patent number: 9354461
    Abstract: A method of manufacturing a display panel, the method including attaching a first carrier substrate to a first substrate; attaching a second carrier substrate to a second substrate; forming a thin film transistor (TFT) array on the first substrate; forming a color filter (CF) array on the second substrate; and coupling the first substrate with the second substrate to provide coupled first and second substrates, the first substrate being bonded to the first carrier substrate with a first intermediate layer therebetween, the second substrate being bonded to the second carrier substrate with a second intermediate layer therebetween, and an adhesive force of the first intermediate layer being weaker than an adhesive force of the second intermediate layer.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 31, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Jin Baek, Myung Hwan Park, Bo Ram Lee, Kun Hee Jo
  • Patent number: 9349814
    Abstract: Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tsung-Liang Chen, Hung-Wei Liu, Rohit Pal, Hsin-Neng Tai, Huey-Ming Wang, Tae Hoon Lee, Songkram Srivathanakul, Danni Chen
  • Patent number: 9040349
    Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: May 26, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do, David Jon Hiner
  • Patent number: 9041082
    Abstract: An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: May 26, 2015
    Assignees: International Business Machines Corporation, Centre National de la Recherche Scientifique
    Inventors: Catherine Anne Dubourdieu, Martin Michael Frank, Vijay Narayanan
  • Patent number: 9040419
    Abstract: A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 26, 2015
    Assignee: SK Hynix Inc.
    Inventor: Ho Young Son
  • Patent number: 9034731
    Abstract: An integrated, integrated circuit singulation system is provided including scribing a substrate using mechanical cutting or a plurality of passes of laser cutting, and dicing the substrate using mechanical cutting or laser cutting.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventor: Seung Wook Park
  • Patent number: 9029991
    Abstract: An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 12, 2015
    Assignee: Conexant Systems, Inc.
    Inventors: Robert W. Warren, Hyun Jung Lee, Nic Rossi
  • Patent number: 9029964
    Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 12, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ga Young Ha, Ki Seon Park
  • Patent number: 9023671
    Abstract: Disclosed herein is a method of disposing phosphor layers, which can prevent damage to phosphors and also effectively dispose phosphor layers at desired locations of Light-Emitting Diodes (LEDs) when the phosphor layers are detached and disposed at the top surfaces of the LEDs. According to an embodiment, phosphor layers fabricated by filling phosphor layer pattern holes within an area of the vertical frame with a phosphor solution are detached from the phosphor layer pattern holes by applying force downwardly or upwardly in a vertical manner.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: May 5, 2015
    Assignee: Lightizer Korea Co.
    Inventors: Jae Sik Min, Jae Young Jang, Jae Yeop Lee, Byoung Gu Cho
  • Patent number: 9018034
    Abstract: Disclosed is an apparatus and method for manufacturing a thin film type solar cell, which enables the enhancement of productivity, the apparatus for manufacturing a thin film type solar cell including a first electrode forming unit; a first separation part; an optoelectric conversion layer forming unit; a contact line forming unit; a printing unit; and an etching process unit, wherein the etching process unit removes the optoelectric conversion layer in a second separation part to expose the first electrode in the second separation part through a wet etching process.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: April 28, 2015
    Assignee: Jusung Engineering Co., Ltd.
    Inventor: Cheol Hoon Yang
  • Patent number: 9006849
    Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 14, 2015
    Inventor: Yimin Guo
  • Patent number: 9000508
    Abstract: Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Sunhil Shim, Jaehoon Jang, Sunghoi Hur, Hansoo Kim, Kihyun Kim
  • Patent number: 8993388
    Abstract: A method of manufacturing a liquid crystal display having a touch sensor, the method including forming a plurality of thin film transistors on a first substrate, forming a plurality of pixel electrodes each coupled to a corresponding one of the thin film transistors, forming an insulating layer on the pixel electrodes, and forming, on the insulating layer, a plurality of first touch electrodes each having openings formed therein and a plurality of driving lines coupled to the first touch electrodes.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 31, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Young Kim, Ji-Ryun Park, Se-Il Cho, Ki-Hoon Kim, Jung-Sun Kim, Hee-Sang Park
  • Patent number: 8987017
    Abstract: This disclosure discloses a method of manufacturing a light-emitting device, comprising proving a single growth substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface, wherein the light-emitting stacks are electrically connected to each other in series via a first electrical connecting structure; forming an electronic device on the second major surface; and forming a second electrical connecting structure extending from the first major surface to the second major surface and electrically connecting the first light-emitting stacks and the electronic device, wherein the electronic device comprises a resistance, an inductance, capacitance, or a rectifying device, and wherein the material of the resistance comprises tantalum nitride (TaN), silicon-chromium alloy (SiCr), or nickel-chromium alloy (NiCr).
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 24, 2015
    Assignee: Epistar Corporation
    Inventor: Chia-Liang Hsu
  • Patent number: 8987021
    Abstract: A manufacturing method of a light-emitting device includes: a die-bonding process in which a semiconductor light emitting element is placed on a bonding target member via an adhesive containing a silicone resin so that a surface opposite to an exposure surface faces the bonding target member, and the adhesive is heated to bond the semiconductor light emitting element to the bonding target member; and a wire-bonding process in which a wire is connected to the exposure surface. The semiconductor light emitting element includes a laminated semiconductor layer having a light emitting layer and an electrode including a metal layer containing Au and provided on the laminated semiconductor layer and a covering layer containing Ni or Ta and covering the metal layer, the thickness of the covering layer being set smaller than 100 nm and the exposure surface to expose the covering layer to the outside being formed.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 24, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Mineo Okuyama
  • Patent number: 8987029
    Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Applied Microstructures, Inc.
    Inventors: Jeffrey D. Chinn, Boris Kobrin, Romuald Nowak
  • Patent number: 8987078
    Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: March 24, 2015
    Assignees: International Business Machines Corporation, GLOBAL FOUNDRIES, Inc.
    Inventors: Jian Yu, Jeffrey B. Johnson, Zhengwen Li, Chengwen Pei, Michael Hargrove
  • Patent number: 8981404
    Abstract: An optoelectronic semiconductor chip includes a semiconductor layer stack and a mirror. The semiconductor layer stack has an active layer for generating electromagnetic radiation. The minor is arranged on an underside of the semiconductor layer stack. The mirror has a first region and a second region, the first region containing silver and the second region containing gold. A method of producing such a semiconductor chip is also defined.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 17, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Martin Rudolf Behringer, Christoph Klemp, Christoph Rupprich
  • Patent number: 8982440
    Abstract: MEMS and fabrication techniques for positioning the center of mass of released structures in MEMS are provided. A MEMS device includes a substrate and a released structure connected to the substrate via a flexure. The released structure includes a frame rotatable with respect to the substrate, and an elongate first member having a longitudinal axis extending perpendicularly from an undersurface of the frame and a free end remote from the frame. A recess is formed in an end face of the free end. The recess has a longitudinal axis substantially parallel to the longitudinal axis of the first member and a transverse area smaller than an area of the end face.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: March 17, 2015
    Assignee: CALIENT Technologies, Inc.
    Inventor: Chris Seung Bok Lee
  • Patent number: 8962363
    Abstract: Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an A, C, M-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the A-axis to form first and second inclined surfaces on the surface of the flat plate. The following mathematical formulae (I)-(III) are satisfied: 45 degrees??b?a?60 degrees (I) 45 degrees??b+a?60 degrees (II), 0 degrees?|a|?7.5 degrees, where angle ?b represents an angle formed between a surface of the edge and a radial direction of the dicing blade in a cross-sectional view which includes the M-axis and the C-axis. The angle a represents an angle formed between the principal surface and the M-axis.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akira Inoue, Toshiyuki Fujita, Toshiya Yokogawa
  • Patent number: 8945960
    Abstract: An optical device wafer has a plurality of optical devices formed on a front side and a plurality of crossing division lines for partitioning the optical devices. Each optical device has electrodes formed on the front side. A processing method includes: forming a groove on the front side of the wafer along each division line, the groove having a depth reaching a finished thickness; of forming a nonconductive reflective film on the front side of the wafer to thereby form the reflective film on at least the side surfaces of the groove; removing the reflective film formed on the electrodes to thereby expose the electrodes; and grinding a back side of the wafer to thereby reduce the thickness to the finished thickness until the groove is exposed to the back side of the wafer to divide the wafer into individual optical device chips.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8945963
    Abstract: An optical device processing method including: a groove forming step of forming a plurality of grooves on a front side of a sapphire substrate; a film forming step of forming an epitaxial film on the front side of the sapphire substrate after performing the groove forming step, thereby forming a plurality of optical devices and a plurality of crossing division lines for partitioning the optical devices; and a dividing step of dividing the sapphire substrate with the epitaxial film along the division lines after performing the film forming step, thereby obtaining a plurality of individual optical device chips.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 8936979
    Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: January 20, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Andy C. Wei, Robert Miller
  • Patent number: 8937330
    Abstract: The invention relates to a radiation-emitting component comprising a semiconductor body which emits electromagnetic radiation from a radiation exit surface during operation. The semiconductor body is arranged in a component housing having a cutout. The component further comprises an optical element which is connected to the component housing in a mechanically stable manner by means of a joining layer. The modulus of elasticity of the joining layer is lower than or equal to 30 MPa.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: January 20, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Joerg Erich Sorg, Ruediger Mueller, Raimund Schwarz
  • Patent number: 8932910
    Abstract: The invention relates to a method for producing chip stacks with the following method sequence: applying an especially dielectric and/or photostructurable base layer to one carrier side of a carrier which on its carrier side is provided with an adhesively acting adhesion zone and a less adhesively acting support zone, the base layer being applied largely over the entire surface at least to the support zone, building up the chip stacks on the base layer, potting of the chip stacks, detaching the carrier from the base layer. Moreover the invention relates to a carrier for executing this method.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: January 13, 2015
    Assignee: EV Group E. Thallner GmbH
    Inventor: Markus Wimplinger
  • Patent number: 8927988
    Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Hongbo Peng
  • Patent number: 8921983
    Abstract: A semiconductor device includes a first semiconductor die. A plurality of conductive vias is formed around the first semiconductor die. A first conductive layer is formed over a first surface of the first semiconductor die and electrically connects to the plurality of conductive vias. A second conductive layer is formed over a second surface of the first semiconductor die opposite the first surface and electrically connects to the plurality of conductive vias. A first passivation layer is formed over the first surface and includes openings that expose the first conductive layer. A second passivation layer is formed over the second surface and includes openings that expose the second conductive layer. Bonding pads are formed within the openings in the first and second passivation layers and are electrically connected to the first and second conductive layers. An interconnect structure is disposed within the openings in the first and second passivation layers.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: December 30, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Lionel Chien Hui Tay, Henry D. Bathan, Zigmund R. Camacho
  • Patent number: 8921163
    Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip having a bonding pad, a metal line electrically connected to the semiconductor chip and having a terminal contacting an external terminal, an insulation layer covering the metal line and having an opening that defines the terminal, and a molding layer molding the semiconductor chip, wherein the molding layer includes a recess pattern exposing the bonding pad and extending from the bonding pad to the terminal, and the metal line is embedded in the recess pattern to contact the bonding pad.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangwook Park, Jonggi Lee, Wonchul Lim
  • Patent number: 8916976
    Abstract: First semiconductor element 1 being buried in first insulating material 2; second semiconductor element 5 being covered by second insulating material 6; connection electrode 4 being buried in first insulating material 2 arranged between circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5; external connection terminal 8 being arranged on lower surface of first insulating material 2 facing in the same direction as lower surface of first semiconductor element 1 opposite to circuit surface thereof; connection electrode 4 forming a part of path for electrically connecting circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5 to each other; first semiconductor element 1 and external connection terminal 8 being electrically connected to each other by way of wire 3 and via 7 passing through region of insulating layer other than region thereof burying connection electrode 4.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: December 23, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masamoto Tago, Yoichiro Kurita
  • Patent number: 8916401
    Abstract: A method for fabricating a semiconductor light emitting device is provided. The method includes forming a semiconductor light emitting portion including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and a light emitting layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. The method also includes forming a first conductivity-type semiconductor side electrode connected to the first conductivity-type semiconductor layer; forming a second conductivity-type semiconductor side electrode connected to the second conductivity-type semiconductor layer; and forming an insulator film covering the semiconductor light emitting portion, such that a first portion of the insulator film is surrounded by the second conductivity-type semiconductor side electrode and is separated from the second conductivity-type semiconductor side electrode by a separation area.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 23, 2014
    Assignee: Nichia Corporation
    Inventor: Hiroaki Matsumura
  • Patent number: 8912013
    Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Seung H. Kang, Xia Li