Polishing method and polishing pad
A polishing method includes polishing a surface to be polished of a target object by using a polishing pad in which a cutout part been formed by cutting out a polishing surface from an outer circumferential end toward an inner part, and after polishing, separating the target object from the polishing pad at a position in contact with the cutout part.
This application is based upon and claims the benefit of priority Japanese Patent Application No. 2006-198895 filed on Jul. 21, 2006 in Japan, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a polishing method and polishing pad, and for example, a polishing method for polishing a copper (Cu) film, silicon oxide film and the like in a process of a method of manufacturing a semiconductor device and a polishing pad used therefor.
2. Related Art
With increasing integration and higher performance of semiconductor integrated circuits (LSI) in recent years, new micro processing technologies have been developed. Particularly, there have been moves recently to change a wiring material from conventional aluminum (Al) alloys to copper (Cu) or Cu allows (hereinafter called Cu together) having lower resistance to make LSI operate faster. It is difficult to apply a dry etching method, which is frequently used for forming Al alloy wires, to Cu for micro processing. For this reason, a damascene method is mainly adopted for Cu, in which a Cu film is deposited on a dielectric film to which groove machining has been provided and then the Cu film is removed except that in portions where embedded in a groove by chemical-mechanical polishing (CMP) to form embedded wiring. After forming a thin seed layer by a sputtering method or the like, the Cu film is generally formed into a laminated film having a thickness of several hundred nanometers by electrolytic plating. Further, when multi-layer Cu wiring is formed, particularly a method of forming wiring called a dual damascene structure can also be used. In this method, a dielectric film is deposited on lower layer wiring and predetermined via holes and trenches (wiring groove) for upper layer wiring are formed. Then, Cu to be a wiring material is embedded in the via holes and trenches simultaneously, and further unnecessary Cu in the upper layer is removed by CMP for flattening to form embedded wiring.
Recently, the use of a low dielectric constant material film with low relative dielectric constant (low-k film) has also been examined as an interlayer dielectric film. That is, an attempt has been made to reduce parasitic capacitance between wires by using a low-k film whose relative dielectric constant k is, for example, 3.5 or lower instead of a silicon oxide (SiO2 film) whose relative dielectric constant k is about 4.2. Moreover, a barrier metal film of tantalum (Ta) or the like is generally formed between the Cu film and the low-k film to prevent diffusion of Cu to the low-k film. Then, unnecessary portions of such a barrier metal film are also removed by CMP for flattening. In addition, unnecessary portions of the SiO2 film are removed by CMP for flattening.
The CMP method is, as described above, a technology widely used in processes of manufacturing semiconductor devices such as high-performance LSI and memory. In the CMP method, a wafer is polished while pressing a surface to be polished of the wafer against a rotating polishing pad (also called polishing cloth) having an approximately circular polishing surface. Here, when separating a wafer after being polished from the polishing pad, the wafer is conventionally caused to move from a polishing position to an outer circumference of the polishing pad by performing an overhang operation and to separate at a position where a portion of the wafer protrudes from the polishing pad. A purpose of performing this operation is to reliably separate the wafer after being polished from the polishing pad despite increased adsorption power between the wafer and the polishing pad due to polishing. On the other hand, an operation to add an extra swing distance to the wafer from the polishing position may be needed.
As a technology related to separation of a wafer from a polishing pad, methods of drilling a through-hole in a polishing pad and feeding compressed air from the polishing pad side to the wafer side have been disclosed (See, for example, Published Unexamined Japanese Patent Application No. 11-114810 (JP-A-11-114810) and Published Unexamined Japanese Patent Application No. 09-85617 (JP-A-09-85617)). However, in such a case, mechanisms for separating a wafer from a polishing pad become complicated, which may lead to increasing manufacturing costs and equipment investment costs. Further, a technology to provide a groove with a grid-like or concentric bottom in a polishing pad to store slurry has been disclosed regardless of separation of a wafer from a polishing pad (See, for example, Published Unexamined Japanese Patent Application No. 2000-755 (JP-A-2000-755)) has been disclosed. However, the technology provides nothing to simplify an operation to separate a wafer.
BRIEF SUMMARY OF THE INVENTIONA polishing method according to an embodiment of the present invention includes polishing a surface to be polished of a target object by using a polishing pad in which a cutout part been formed by cutting out a polishing surface from an outer circumferential end toward an inner part; and after polishing, separating the target object from the polishing pad at a position in contact with the cutout part.
A polishing method according to another embodiment of the present invention includes polishing a surface to be polished of a target object by using a polishing pad in which a cutout part been formed by cutting out a polishing surface from an outer circumferential end toward an inner part, after polishing, moving the target object to a position where a contact area between the target object and the polishing pad becomes smaller based on the cutout part formed in the polishing pad, and after moving, separating the target object from the polishing pad.
A polishing pad according to still another embodiment of the present invention includes a polishing surface for polishing a target object, and an outer circumferential side surface in which a plurality of cutout parts been formed from an outer circumferential end of the polishing surface toward an inner part to be cut through from the polishing surface to a back surface of the polishing surface.
BRIEF DESCRIPTION OF THE DRAWINGS
In a first embodiment, description will be given to a polishing pad that can easily perform an operation of separating a wafer or the like after being polished and a polishing method. The first embodiment will be described below with reference to drawings.
Then, as a low-k film formation step, a thin film of a low-k film 220 using porous low dielectric constant insulating material is formed on a substrate 200 having a thickness of, for example, 200 nm. Forming the low-k film 220 enables to obtain an interlayer dielectric film whose relative dielectric constant k is less than 3.5. Here, the low-k film 220 is formed, as an example, using LKD (Low-K Dielectric material manufactured by JSR) in which polymethyl siloxane that could become a low dielectric constant insulating material of relative dielectric constant of less than 2.5 is used. In addition to polymethyl siloxane, the low-k film 220 may also be formed by using at least one selected from the group consisting of a film having a siloxane backbone structures such as polysiloxane, hydrogen silsesquioxane, and methyl silsesquioxane, a film having as its main component an organic resin such as polyarylene ether, polybenzo-oxazole, and polybenzo-cyclobutene, and a porous film such as a porous silica film. Such a material for the low-k film 220 may have low dielectric constant whose relative dielectric constant is less than 2.5. An SOD (spin on dielectric coating) method can be used, for example, as a formation method in which a thin film is formed by spin-coating and heat-treating a solution. For example, the low-k film 220 can be formed by forming a film by a spinner, baking the film as a wafer on a hot plate in a nitrogen atmosphere, and finally curing the wafer at temperature higher than the baking temperature in the nitrogen atmosphere on the hot plate. By appropriately adjusting the low-k material and formation conditions, a porous dielectric film having predetermined physical property values can be obtained.
As a cap film formation step, a thin film of an SiOC film 222 is formed by depositing carbonation silicon (SiOC) having a thickness of, for example, 50 nm on the low-k film 220 as a cap dielectric film by the CVD method. By forming the SiOC film 222, patterns can be formed on the low-k film 220 while protecting the low-k film 220 on which it is difficult to perform lithography directly. In addition to SiOC, a cap dielectric film may also be formed by using at least one insulating material whose relative dielectric constant is 2.5 or more from the group consisting of TEOS (tetraethoxy silane), silicon carbide (SiC), silicon carbohydrate (SiCH), silicon carbo-nitride (SiCN), SiOCH and silane (SiH4). The cap dielectric film is formed here by the CVD method, but any other method may also be used.
Next, as an opening formation step, an opening, which is a wiring groove structure for preparing damascene wiring in a lithography step and a dry etching step, is formed inside the SiOC film 222, low-k film 220 and ground SiC film 212. The substrate 200 has a resist film formed on the SiOC film 222 through the lithography step such as a resist application step and exposure step (not shown). The exposed SiOC film 222 and the low-k film 220 positioned thereunder are removed using an anisotropic etching method using the ground SiC film 212 as an etching stopper before forming an opening by performing etching of the ground SiC film 212. Using the anisotropic etching method enables the opening to be formed approximately perpendicularly to the surface of the substrate 200. For example, the opening may be formed by a reactive ions etching method.
Then, as a barrier metal film formation step, a barrier metal film 240 using a barrier metal material is formed in the opening for wiring or to be a contact/via groove formed in the opening formation step and on the surface of the SiOC film 222. The barrier metal film 240 is formed by depositing a thin film of tantalum (Ta) with a thickness of, for example, 5 nm in a sputtering device using a sputtering method, which is one kind of physical vapor deposition (PVD) methods. The method of depositing the barrier metal material is not limited to the PVD process, and also an atomic layer vapor deposition (atomic layer deposition (ALD) method or atomic layer chemical vapor deposition (ALCVD) method) and the CVD method may be used. By using these methods, better coverage can be obtained than when the PVD process is used. Examples of the material for the barrier metal film include not only Ta but also tantalum nitride (TaN), titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), or a laminated film combining Ta and TaN or others.
Then, as a seed film formation step, a Cu thin film to be a cathode electrode of the next step, an electro-plating step, is deposited (formed) on the opening inner wall where the barrier metal film 240 is formed and substrate surface as a seed film by means of a physical vapor deposition (PVD) method such as sputtering. Here, the seed film with a thickness of, for example, 50 nm is deposited.
Then, as a plating step, a thin film of a Cu film 260 is deposited in the opening and on the substrate surface by an electrochemical deposition process such as electro-plating with the seed film acting as a cathode electrode. Here, after depositing the Cu film 260 having a thickness of, for example, 800 nm, annealing process is performed at 250° C. for 30 minutes. A target object as shown in
Polishing of the Cu film 260 has been described in the above description. When polishing an oxide film, for example, polishing may be performed under the following conditions. Slurry to be used is DLS-2 (manufactured by Hitachi Chemical Co. Ltd.) and TK-75 (manufactured by Kao Corporation) is used as a dispersing agent to be added thereto. FREX (manufactured by Ebara Corporation) is used as a polishing device. The polishing conditions in this case are, for example: polishing load (DF): 3.92×1 Pa (400 gf/cm2); the number of rotations of top ring (TR) : 107 min−1 (rpm); the number of rotations of turn table (TT): 100 min−1 (rpm); flow rate of slurry: 0.19 L/min (190 cc/min); and flow rate of dispersing agent: 0.007 L/min (7.0 cc/min). As the polishing pad 525, IC1000 (RODEL Co.), for example, is used. Polishing is performed for 300 seconds under the conditions described above.
Next, as a movement step denoted by S104 in
Then, as a separation step denoted by S106 in
As described above, after the substrate 300 is swung to a position where the substrate 300 is in contact with the polishing pad 525 in a movement operation after polishing, the substrate 300 is separated. The surface of the substrate polished in this way is then inspected for defects to examine the number of defects and distribution thereof. An apparatus for defect inspection manufactured by KLA-Tencor Corporation is used.
In contrast, in the polishing pad 525 of the first embodiment, the substrate 300 is separated from the polishing pad 525 while inside the polishing pad 525 and thus the end of the polishing pad 625 will not come into contact with the substrate 300. Since the contact area between the substrate 300 and the polishing pad 525 can be reduced by the recess 102 (groove processed part), the substrate 300 can be separated reliably. That is, if the substrate 300 is separated after moving the substrate 300 to a position in contact with the recess 102 while keeping inside the outer circumferential end like in the first embodiment, a region where dust concentrates and adheres can be eliminated or reduced as shown in
Here, the width W of the protrusion 104 shown in
Depth d of cutout shown in
The embodiment has been described with reference to concrete examples. However, the present invention is not limited to these concrete examples. For example, although a plurality of recesses 102 acting as cutout parts are arranged, one recess 102 acting as a cutout part can also be constructed. In such a case, rotation of the turn table 520 and movement of the substrate 300 for separation may be synchronized to separate the substrate 300 when the substrate 300 just overlaps with the recess 102.
Also, rotation of the turn table 520 maybe stopped to fix the substrate 300 to the recess 102. In such a case, however, rotation of the top ring 510 is preferably kept to mitigate adsorption power.
If a plurality of recesses 102 acting as cutout parts are arranged, it is preferable to arrange the recesses 102 regularly at a predetermined pitch to produce uniform contact with the substrate. Instead of arranging the recesses 102 regularly at a predetermined pitch, the recesses 102 may also be arranged at random intervals.
Also, the thickness of interlayer dielectric films, and the size, shape, and number of openings that are necessary for semiconductor integrated circuits and various kinds of semiconductor devices may suitably be selected and used.
In addition, all polishing methods, polishing pads, and methods of manufacturing semiconductor devices that are equipped with components of the present invention and suitably modifiable by a person skilled in the art are also included in the scope of the present invention.
Techniques normally used in semiconductor industry, for example, photo-lithography processes and cleaning before or after processing are omitted to simplify a description, but such techniques are naturally included in the scope of the present invention.
Additional advantages and modification will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
1. A polishing method, comprising:
- polishing a surface to be polished of a target object by using a polishing pad in which a cutout part been formed by cutting out a polishing surface from an outer circumferential end toward an inner part; and
- after polishing, separating the target object from the polishing pad at a position in contact with the cutout part.
2. The polishing method according to claim 1, wherein the surface to be polished of the target object is polished at a position not in contact with the cutout part.
3. The polishing method according to claim 1, wherein the polishing pad in which a plurality of cutout parts been formed regularly along outer circumferential parts of the polishing surface of the polishing pad is used.
4. The polishing method according to claim 1, wherein the target object is separated from the polishing pad without being moved up to a point outside the outer circumferential end of the polishing surface of the polishing pad.
5. The polishing method according to claim 1, wherein the target object is separated from the rotating polishing pad.
6. The polishing method according to claim 1, wherein the target object is separated while rotating.
7. The polishing method according to claim 6, wherein the target object is separated from the polishing pad after stopping the rotating polishing pad.
8. A polishing method, comprising:
- polishing a surface to be polished of a target object by using a polishing pad in which a cutout part been formed by cutting out a polishing surface from an outer circumferential end toward an inner part;
- after polishing, moving the target object to a position where a contact area between the target object and the polishing pad becomes smaller based on the cutout part formed in the polishing pad; and
- after moving, separating the target object from the polishing pad.
9. The polishing method according to claim 8, wherein the target object is separated from the polishing pad without being moved up to a point outside the outer circumferential end of the polishing surface of the polishing pad.
10. The polishing method according to claim 8, wherein the surface to be polished of the target object is polished at a position not in contact with the cutout part.
11. The polishing method according to claim 8, wherein the polishing pad in which a plurality of cutout parts been formed regularly along outer circumferential parts of the polishing surface of the polishing pad is used.
12. A polishing pad, comprising:
- a polishing surface for polishing a target object; and
- an outer circumferential side surface in which a plurality of cutout parts been formed from an outer circumferential end of the polishing surface toward an inner part to be cut through from the polishing surface to a back surface of the polishing surface.
13. The polishing pad according to claim 12, wherein the plurality of cutout parts are formed by a straight line from the outer circumferential end of the polishing surface toward the inner part.
14. The polishing pad according to claim 13, wherein the plurality of cutout parts have a cutout bottom formed by a straight line.
15. The polishing pad according to claim 13, wherein the plurality of cutout parts have a cutout bottom formed by a gentle curve.
16. The polishing pad according to claim 13, wherein the plurality of cutout parts have a cutout bottom formed by a semicircle.
17. The polishing pad according to claim 12, wherein the plurality of cutout parts are formed by a gentle curve from the outer circumferential end of the polishing surface toward the inner part.
18. The polishing pad according to claim 12, wherein the plurality of cutout parts are formed by a semicircle formed from the outer circumferential end of the polishing surface toward the inner part.
19. The polishing pad according to claim 12, wherein a corner between the polishing surface and the side surface of the plurality of cutout parts is formed as a curve.
20. The polishing pad according to claim 12, wherein a corner between the polishing surface and the side surface of the plurality of cutout parts is chamfered by a plane.
Type: Application
Filed: Jul 17, 2007
Publication Date: Jan 24, 2008
Inventors: Shunsuke Doi (Mie), Hiroyuki Yano (Kanagawa)
Application Number: 11/826,646
International Classification: B24B 29/00 (20060101); B24B 1/00 (20060101);