Apparatus to facilitate functional shock and vibration testing of device connections and related method
An apparatus and associated method are disclosed for facilitating the testing of device connections, including functional shock and vibration testing of peripheral card slots or any other desired connector interface. In part, a power supply located on the peripheral device, or some other external power source, is used to power fault detection circuitry. In this way, faults can be identified, such as through visual fault indicators, without the necessity of powering the system. In addition, simulated peripheral cards are provided that include adjustable weights so that the weight distribution of an actual card can be simulated without the necessity of having a functional peripheral in hand.
Latest Patents:
This application is a continuation application of Ser. No. 10/972,752, filed Oct. 25, 2004, and entitled “APPARATUS TO FACILITATE FUNCTIONAL SHOCK AND VIBRATION TESTING OF DEVICE CONNECTIONS AND RELATED METHOD,” which is hereby incorporated by reference in its entirety.
TECHNICAL FIELD OF THE INVENTIONThis invention relates to shock and vibration testing of mechanically connected electrical devices and, more particularly, to such testing for peripheral cards connected to slots in a computer chassis.
BACKGROUNDAs the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
When information handling systems, such as computer systems, are shipped to customers, failures can occur due to the shock and vibrations experienced by the system. For example, in a shipping environment, peripheral cards have the potential to “rock-up” to where the gold finger connectors on the card lose electrical continuity with contacts on the connector within the chassis. For any new platform or product, this rock-up condition is typically tested during shock and vibration test cycles. After shipping to customers, rock-up is often the cause of a significant number of initial product failures reported in the field. This failure rate can be particularly significant with larger form factor chassis.
With respect to peripheral cards, shock and vibration testing can be difficult to accomplish. In the case of technology transitions, such as a PCI bus to a PCI-Express (PCI-E) bus transition, functional peripheral devices are often not available early in the testing cycle. In addition, the functional systems within which the peripheral device will be included may not yet be available where the testing is occurring early in the development cycle for a new functional system. A further difficulty arises in the ability to identify when a peripheral card has rocked out of position because with current shock and vibration testing techniques, continuity of connection cannot be determined without first powering on the system. To power the system in traditional test environments, however, external power sources must be connected, thereby lengthening and complicating test cycles. In addition, the actual weight distribution of the peripheral card, in addition to the connector mechanics, may be a factor in connection faults that actually occur in the field. As such, when no functional peripheral cards are available for testing, the weight distribution for these functional peripheral cards is often difficult to take into consideration using traditional shock and vibration testing techniques.
SUMMARY OF THE INVENTIONThe present invention provides an apparatus and associated method for facilitating the testing of device connections, including functional shock and vibration testing of peripheral card slots or any other desired connector interface. In part, a power supply located on the peripheral device, or some other external power source, is used to power fault detection circuitry. In this way, faults can be identified, such as through visual fault indicators, without the necessity of powering the system under test (SUT). In addition, simulated peripheral cards are provided that include adjustable weights so that the weight distribution of an actual card can be simulated without the necessity of having a functional peripheral in hand.
DESCRIPTION OF THE DRAWINGSIt is noted that the appended drawings illustrate only exemplary embodiments of the invention and are, therefore, not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer, a server computer system, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.
As described below in detail below, an apparatus and associated method are disclosed for facilitating the testing of device connections, including functional shock and vibration testing of peripheral card slots or any other desired connector interface. In part, a power supply located on the peripheral device, or some other external power supply, is used to power fault detection circuitry so that faults can be identified without the necessity of powering the system. In addition, adjustable weights are provided so that the weight distribution of an actual peripheral card can be simulated without the necessity of having a functional peripheral in hand. Example embodiments are now described in further detail with respect to the drawings.
The power supply 104 is provided so that the system within which the peripheral test apparatus 100 is designed to be placed does not have to be powered. Rather, power supply 104 can provide the power utilized by the peripheral test apparatus 100 during operation. As depicted in
It is also noted that fault indicators other then visible fault indicators, such as LEDs, could be utilized, if desired. Also, if desired, the fault states for connections could be stored in memory device, such as an on-card memory device, and these fault conditions could be polled and stored at regular time intervals so that information concerning the timing of faults during testing could be determined. Memory devices that could be utilized include SRAM, DRAM and FLASH memories, FLASH systems such as removable or portable FLASH memory cards and memory sticks, and/or fixed or removable hard disks or any other desired recordable storage media. This time based tracking of faults would be helpful, for example, where a peripheral card becomes unseated at some point during the shock and vibration test but becomes seated by the end of the test. In addition, the time at which the connection was lost could be correlated to the test script so that the nature of the event that caused the fault could be determined. Still further, circuitry could be provided on the peripheral device that allows for wireless or wired communication to external devices that could record fault information during the test cycle or provide measurement processing. In addition, other data gathering devices could be included with respect to the peripheral device, such as accelerometers or other sensors. Other variations could be also be implemented, as desired, utilizing the on-card power supply to provide power for electronically controlling and recording testing results.
Looking back to
It is again noted that different logic circuitry could be utilized, if desired. For example, the latch 302A could be eliminated so that the fault indicator 252A would always show the current state of the connection. In other words, if the connection stripe 254A became reseated during test and a good connection existed at the end of the test, the fault indicator 252A would indicate a good connection, as would the fault indication signal 304A that is provided to the combining logic. In addition, if desired, an additional fault indicator could be added to the embodiment of
In one implementation, a D flip-flop latch circuit can be used for the latch 302A. And this D flip-flop can be configured such that it will output a signal indicating that a fault has occurred if a connection is lost at any time during the test. In particular, the D input to the D flip-flop latch can be set to a high logic level, for example, by connecting it to a logic high voltage, such as 3 volts. This logic high connection provides a constant, known input state for the D input. The clock of the D flip-flop latch is edge triggered and attached to a ground pin on the card edge connector 110. As discussed above, the connector 110, when properly seated, is configured to be effectively connected to the chassis ground even though the system is not powered. When the connection to ground is broken (indicating a fault), this fault event causes the CLOCK input to transition high due to a pull-up on the input (shown in more detail in
As noted above, circuitry could be utilized, if desired, to identify the current connection state for connector 110. And combination logic could be utilized, if desired, to identify the overall current connection state for connector 110. In the embodiment of
Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the present invention is not limited by these example arrangements. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the implementations and architectures. For example, equivalent elements may be substituted for those illustrated and described herein and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.
Claims
1. An apparatus for testing card slot connections, comprising:
- a card device body having a card edge connector configured to be seated within a slot connector for another device;
- a power source coupled to provide power to the card device body; and
- fault detection circuitry located on the card device body and coupled to the card edge connector and to the power source, the fault detection circuitry being configured to output at least one fault indication signal when a connection fault occurs between the card edge connector and the slot connector during a test procedure.
2. The apparatus of claim 1, wherein the power source comprises power supply circuitry located on the card device body.
3. The apparatus of claim 1, wherein the card device body comprises a peripheral card for an information handling system.
4. The apparatus of claim 1, wherein the card edge connector comprises a plurality of connections, and further comprising a plurality of fault indicators such that each fault indicator is associated with at least one connection and further comprising a plurality of control circuits such that each control circuit is associated with at least one fault indicator, the control circuits being configured to output a plurality of fault indication signals to control the fault indicators.
5. The apparatus of claim 4, further comprising combining logic coupled to receive a plurality of fault indication signals from the control circuits and to provide as an output a combined fault indication signal.
6. An information handling system for testing card slot connections, comprising:
- a chassis configured to hold components for the information handling system;
- a power supply for the information handling system coupled to the chassis;
- a motherboard coupled to the chassis, the motherboard having a slot connector;
- a card device body having a card edge connector seated within the slot connector;
- a power source coupled to provide power to the card device body, the power source being different from the power supply for the information handling system; and
- fault detection circuitry located on the card device body and coupled to the card edge connector and to the power source, the fault detection circuitry being configured to output at least one fault indication signal when a connection fault occurs between the card edge connector and the slot connector during a connection test procedure.
7. The information handling system of claim 6, wherein the peripheral card has a panel located at least at one end, and further comprising a visible fault indicator located on the panel so as to be viewable from outside the chassis.
8. The information handling system of claim 6, wherein the power source comprises power supply circuitry located on the motherboard, wherein the card device body and the motherboard have a common ground, wherein at least one ground connection on the card device body is coupled to the common ground through the slot connector, and wherein the fault detection circuitry is configured to output a fault indication signal if a connection fault occurs between the ground connection and the common ground.
9. The information handling system of claim 6, wherein the card edge connector comprises a plurality of connections and further comprising a plurality of fault indicators coupled to the plurality of connections.
10. A method for facilitating testing of card slot connections, comprising:
- seating a card edge connector of a first card device body within a slot connector on a second device body;
- powering connection fault detection circuitry on the first card device body;
- conducting shock and vibration testing that includes the first card device body and the second device body; and
- generating at least one fault indication signal using the connection fault detection circuitry when a connection fault occurs between the card edge connector for the first card device body and the slot connector for the second device body during the conducting step.
11. The method of claim 10, wherein the powering step comprises powering the connection fault detection circuitry on the first card device body utilizing circuitry located on the first device body.
12. The method of claim 11, further comprising providing a common ground connection between the first card device body and the second device body.
13. The method of claim 12, wherein the generating step comprises generating at least one fault indication signal associated with the common ground connection.
14. The method of claim 10, further comprising utilizing at least one visible fault indicator configured to indicate connection faults.
15. The method of claim 10, wherein the generating step comprises generating at least one fault indication signal indicating whether a connection fault occurred at any time during testing and generating at least one fault indication signal indicating a current condition for connection continuity.
16. The method of claim 10, further comprising providing a motherboard as the second device body and a peripheral card for the first card device body.
17. The method of claim 10, further comprising generating an individual fault indication signal for each connection on the card edge connector of the first card device body.
18. The method of claim 17, further comprising generating a combined fault indication signal based upon the individual fault indication signals.
19. The method of claim 10, further comprising providing at least one visible fault indicator.
20. The method of claim 10, further comprising powering the second device body with a separate power supply from the power source utilized for powering connection fault detection circuitry on the first card device body.
Type: Application
Filed: Oct 5, 2007
Publication Date: Feb 14, 2008
Applicant:
Inventors: Joshua Alperin (Round Rock, TX), Jeffrey Cardwell (Austin, TX), Matthew McGowan (Austin, TX)
Application Number: 11/973,136
International Classification: G01R 31/04 (20060101);