CHIP SCALE MODULE PACKAGE IN BGA SEMICONDUCTOR PACKAGE
A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate, and an application die attached to the integrated passive device (IPD). A method of manufacturing a semiconductor package includes providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate, and attaching an application die to the integrated passive device (IPD).
The present invention relates in general to semiconductor devices and, more particularly, to multi-chip semiconductor packages that have stacked dies.
BACKGROUND OF THE INVENTIONSemiconductors, or computer chips, are found in virtually every electrical product manufactured today. Chips are used not only in very sophisticated industrial and commercial electronic equipment, but also in many household and consumer items such as televisions, clothes washers and dryers, radios, and telephones. As products become smaller but more functional, there is a need to include more chips in the smaller products to perform the functionality. The reduction in size of cellular telephones is one example of how more and more capabilities are incorporated into smaller and smaller electronic products.
As the demand for semiconductor devices with low-cost, high performance, increased miniaturization, and greater packaging densities has increased, Multi-Chip Module (MCM) structures have been developed to meet the demand. MCM structures have a number of dies and other semiconductor components mounted within a single semiconductor package. The number of dies and other components can be mounted in a vertical manner, a lateral manner, or combinations thereof.
One such approach is to stack one die on top of another and then enclose the stack of dies in one package. The final package for a semiconductor with stacked dies is much smaller than would result if the dies were each packaged separately. In addition to providing a smaller size, stacked-die packages offer a number of advantages that relate to the manufacturing of the package, such as ease of handling and assembly.
In a stacked-die arrangement, the dies are wire-bonded sequentially, typically with automated wire-bonding equipment employing well-known thermal compression or ultrasonic wire-bonding techniques. During the wire-bonding process, the head of a wire-bonding apparatus applies a downward pressure on a conductive wire held in contact with a wire-bonding pad on the die to weld, or bond, the wire to the bonding pad on the die.
In many cases, stacked-die semiconductors can be fabricated faster and more cheaply than several semiconductors, each having a single die, which perform the same functions. A stacked-die approach is advantageous because of the increase in circuit density achieved.
A variety of semiconductor package configurations having stacked die arrangements are found in the art. However, the configurations currently known could stand to benefit from additional flexibility of implementing subcomponents such as integrated circuits (ICs) and integrated passive devices (IPDs) which can include resistors, capacitors, inductors, filters, and BALUNs. Accordingly, a need exists for a semiconductor package with such increased functionality. Additionally, a need exists for a semiconductor package which promotes higher performance while providing lower cost and a smaller footprint.
SUMMARY OF THE INVENTIONIn one embodiment, the present invention is a semiconductor package, comprising a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array substrate, and an application die attached to the integrated passive device.
In another embodiment, the present invention is a method of manufacturing a semiconductor package, comprising providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array substrate, and attaching an application die to the integrated passive device.
In another embodiment, the present invention is a semiconductor package, comprising a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the cavity of the thermally-enhanced substrate, and an application die attached to the integrated passive device.
In still another embodiment, the present invention is a method of manufacturing a semiconductor package, comprising providing a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the cavity of the thermally-enhanced substrate, and attaching an application die to the integrated passive device.
In still another embodiment, the present invention is a semiconductor package, comprising a ball grid array (BGA) substrate having integrated metal circuitry, a wafer level chip scale package (WLCSP) attached to the ball grid array (BGA) substrate, the wafer level chip scale package having a first integrated passive device (IPD), and an application die attached to the integrated passive device (IPD).
The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
Current semiconductor packaging trends toward delivering towards low cost, smaller size, and higher performance. To help achieve lower cost and smaller size packages with higher performance, the chip scale module package (CSMP) has been implemented. The present invention utilizes the CSMP to incorporate the CSMP into a standard ball grid array (BGA) semiconductor package to provide increased functionality and a smaller package footprint.
Turning to
Chip scale module packaging is an advanced system-in-package (SiP) which features a modular architecture that integrates mixed integrated circuit (IC) technologies and a wide variety of integrated passive devices such as resistors, capacitors, inductors, filters, BALUNs and interconnects directly onto the silicon substrate.
Package 16 is attached on the BGA substrate 28 by a solder paste, flux, or adhesive material at bump pad 26. To provide connectivity, the application die 22 can use wirebond 30 to connect the wire bond pad 32 of die 22 with the BGA metal layer circuitry and/or bond fingers 34. Similarly, application die 22 can utilize wirebond 36 to connect the wire bond pad 38 to external bond pads and/or bond fingers 40 located on package 16. An encapsulant 42 is formed over package 16 to provide structural support to package 16 within overall package 14.
Package 14 can be constructed utilizing standard molding or TOP mold gate techniques. By combining CSMP package 16 and BGA package 12 into package 14, package 14 can take advantage of the positive aspects of each package to provide enhanced device functionality for applications such as wireless local area networks (WLAN), Bluetooth or similar application specific integrated circuits (ASIC), digital signal processing (DSP), memory applications, gate arrays, PC chipsets, and the like. In addition, package 14 can achieve passive function integration through the use of integrated passive devices (IPDs) which are incorporated on the CSMP module 16 without the use of a standard external passive component.
Turning to
In the depicted embodiment, interconnectivity from the flip chip CSMP external pads to pads located on the BGA substrate 28 is provided at junction 44 using solder paste or a conductive epoxy.
In the fifth step of the method,
In an additional embodiment, a modified KGU flip chip CSMP can be incorporated in a modified thermally-enhanced package for a particular application. For purposes of conception,
Wire bonding can be incorporated into package 56 as follows. Wire bonds 72 provide electrical interconnectivity between bond pads 74 located on die 66 and bond pads 76 located as part of the modified thermally-enhanced package. Wire bonds 76 provide electrical connectivity between pads 80, also on die 66, and pads 82, located externally on CSMP package 58. Similarly, wire bonds 84 provide connectivity between pads 86 located as part of the modified thermally-enhanced substrate 57 and pads 88 located externally on modified CSMP package 58. Finally, solder balls 90 provide electrical connectivity to external electrical circuitry as depicted.
As a next step, the various wirebonding as previously described takes place as shown in
In an additional embodiment, a “Known Good” wafer level chip scale package/chip scale module package (WLCSP-CSMP) can be modified to be incorporated into a modified ball grid array (BGA) package to perform specific functionality for a particular application. Again, for purposes of conceptual illustration,
Connectivity of the modified WLCSP-CSMP to the BGA substrate 28 can be performed by wirebonds 102 connecting bond pads 104 located as part of die 98 to pads 106 connected to metal circuitry incorporated into BGA substrate 28. Additionally, junction 96 provides electrical connectivity between solder balls of the modified WLCSP-CSMP and additional pads 106 also connected to metal circuitry of the BGA substrate 28.
Package 94 can be constructed using standard molding or TOP mold gate techniques. The package 94 provides enhanced device functionality due to combining favorable aspects of the WLCSP-CSMP and BGA package designs for applications such as WLAN, Bluetooth, DSP, chipsets, and a host of related applications.
Package 94 adds passive function integration through the use of IPDs 98 as application dies 98 which are incorporated on the modified CSMP module as previously depicted without the requirement of using a standard external passive component.
In summary, the use of packages such as package 94, package 56, and package 14 provides enhanced functionality and serves to take advantage of positive aspects of older designs which are modified to create the packages 94, 56, and 14.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Claims
1. A semiconductor package comprising:
- a ball grid array (BGA) substrate having integrated metal layer circuitry;
- a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate; and
- an application die attached to the integrated passive device (IPD).
2. The semiconductor package of claim 1, wherein the flip chip CSMP is attached to the BGA substrate using an adhesive material.
3. The semiconductor package of claim 2, wherein the adhesive material further includes a solder paste or flux material.
4. The semiconductor package of claim 1, wherein the application die is wirebonded to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
5. The semiconductor package of claim 1, wherein the application die is wirebonded to the CSMP to provide electrical connectivity.
6. The semiconductor package of claim 1, wherein the CSMP is wirebonded to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
7. The semiconductor package of claim 1, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
8. The semiconductor package of claim 1, further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package.
9. The semiconductor package of claim 1, wherein the CSMP includes a grounded flip chip die for enhanced thermal performance.
10. A method of manufacturing a semiconductor package, comprising:
- providing a ball grid array (BGA) substrate having integrated metal layer circuitry;
- attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate; and
- attaching an application die to the integrated passive device (IPD).
11. The method of manufacturing a semiconductor package of claim 10, wherein the flip chip CSMP is attached to the BGA substrate using an adhesive material.
12. The method of manufacturing a semiconductor package of claim 11, wherein the adhesive material further includes a solder paste or flux material.
13. The method of manufacturing a semiconductor package of claim 10, further including wirebonding the application die to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
14. The method of manufacturing a semiconductor package of claim 10, further including wirebonding the application die to the CSMP to provide electrical connectivity.
15. The method of manufacturing a semiconductor package of claim 10, further including wirebonding the CSMP to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
16. The method of manufacturing a semiconductor package of claim 10, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
17. The method of manufacturing a semiconductor package of claim 1, further including forming an encapsulant over the CSMP for providing structural support to the CSMP within the semiconductor package.
18. The method of manufacturing a semiconductor package of claim 10, wherein the CSMP includes a grounded flip chip die for enhanced thermal performance.
19. A semiconductor package comprising:
- a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity;
- a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the cavity of the thermally-enhanced substrate; and
- an application die attached to the integrated passive device (IPD).
20. The semiconductor package of claim 19, wherein the flip chip CSMP is attached to the thermally-enhanced substrate using an adhesive material.
21. The semiconductor package of claim 19, wherein the application die is attached to the integrated passive device using an adhesive material.
22. The semiconductor package of claim 19, wherein the application die is wirebonded to a bond finger of the thermally-enhanced substrate to provide electrical connectivity.
23. The semiconductor package of claim 19, wherein the application die is bonded to the flip chip CSMP package to provide electrical connectivity.
24. The semiconductor package of claim 19, wherein the flip chip CSMP package is wirebonded to a bond finger of the thermally-enhanced package to provide electrical connectivity.
25. The semiconductor package of claim 19, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
26. The semiconductor package of claim 19, wherein the CSMP includes a thermally-enhanced flip chip die.
27. The semiconductor package of claim 19, further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package.
28. A method of manufacturing a semiconductor package comprising:
- providing a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity;
- attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the cavity of the thermally-enhanced substrate; and
- attaching an application die to the integrated passive device (IPD).
29. The method of manufacturing a semiconductor package of claim 28, wherein the flip chip CSMP is attached to the cavity of the thermally-enhanced substrate using an adhesive material.
30. The method of manufacturing a semiconductor package of claim 28, wherein the application die is attached to the integrated passive device using an adhesive material.
31. The method of manufacturing a semiconductor package of claim 28, wherein the application die is wirebonded to a bond finger of the thermally-enhanced substrate to provide electrical connectivity.
32. The method of manufacturing a semiconductor package of claim 28, wherein the application die is bonded to the flip chip CSMP package to provide electrical connectivity.
33. The method of manufacturing a semiconductor package of claim 28, wherein the flip chip CSMP package is wirebonded to a bond finger of the thermally-enhanced package to provide electrical connectivity.
34. The method of manufacturing a semiconductor package of claim 28, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
35. The method of manufacturing a semiconductor package of claim 28, wherein the CSMP includes a thermally-enhanced flip chip die.
36. The method of manufacturing a semiconductor package of claim 28, further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package.
37. A semiconductor package, comprising:
- a ball grid array (BGA) substrate having integrated metal circuitry;
- a wafer level chip scale package (WLCSP) attached to the ball grid array substrate, the wafer level chip scale package having a first integrated passive device (IPD); and
- an application die attached to the integrated passive device (IPD).
38. The semiconductor package of claim 37, wherein the WLCSP is attached to the BGA substrate, or the application die is attached to the IPD using an adhesive material.
39. The semiconductor package of claim 38, wherein the adhesive material further includes solder paste or flux-reflow material.
40. The semiconductor package of claim 37, wherein the application die further includes a second IPD or an integrated circuit (IC) device.
41. The semiconductor device of claim 37, wherein the WLCSP is wirebonded to the integrated metal circuitry of the BGA substrate to provide electrical connectivity.
42. The semiconductor device of claim 37, wherein a solder ball of the WLCSP is bonded to a ball pad located on the BGA substrate to provide electrical connectivity.
43. The semiconductor device of claim 37, further including an encapsulant formed over the WLCSP to provide structural support to the WLCSP within the semiconductor package.
Type: Application
Filed: Aug 15, 2006
Publication Date: Feb 21, 2008
Inventors: Leo A. Merilo (Singapore), Emmanuel A. Espiritu (Singapore), Dario S. Filoteo (Singapore), Rachel L. Abinan (Singapore)
Application Number: 11/464,699
International Classification: H01L 23/34 (20060101);