For Plural Devices Patents (Class 257/723)
  • Patent number: 10777537
    Abstract: An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Didier Lattard, Sebastien Thuries
  • Patent number: 10756005
    Abstract: A semiconductor device including one or more semiconductor dice, a lead frame including an array of signal-carrying leads electrically coupled with the semiconductor die, and a power supply connection for the at least one semiconductor die arranged centrally thereof.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10720416
    Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 10720409
    Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Hsien Huang, Yueh-Ting Lin, Wei-Yu Chen, An-Jhih Su
  • Patent number: 10714443
    Abstract: A semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 14, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hirokazu Saito
  • Patent number: 10707171
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Tomita Yoshihiro, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Patent number: 10699988
    Abstract: A method of forming a chip package structure can include: forming a substrate; forming a first cavity in the substrate; and installing a first chip in the first cavity. The method can also include forming a second cavity in the substrate; and installing a second chip in the second cavity. The first cavity is located at a first side of the substrate, and the second cavity is located at a second side of the substrate, where the first side of the substrate is opposite to the second side of the substrate.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 30, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Shijie Chen
  • Patent number: 10699983
    Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-soo Kim, Yong-hoon Kim, Hyun-ki Kim, Kyung-suk Oh
  • Patent number: 10679951
    Abstract: A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tzu-Shiun Sheu, Shin-Puu Jeng, Shih-Peng Tai, An-Jhih Su, Chi-Hsi Wu
  • Patent number: 10665568
    Abstract: To provide a technique of preventing, in an encapsulated circuit module having a metal shield layer covering a surface of a resin layer containing filler, the shield layer from falling off. In manufacturing encapsulated circuit modules, first, a substrate 100 is covered with a first resin 400 containing filler together with an electronic component 200. Next, a surface of the first resin 400 is covered with a second resin 500 containing no filler. Subsequently, a ground electrode 110 in the substrate 100 is exposed by snicking and then a shield layer 600 that covers the entire surface of the substrate 100 is formed by electroless plating. Thereafter, snipping is performed to obtain a number of encapsulated circuit modules.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 26, 2020
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Satoru Miwa
  • Patent number: 10665536
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Chewn-Pu Jou
  • Patent number: 10665538
    Abstract: A semiconductor apparatus includes a semiconductor device having a semiconductor circuit formed on a first main surface, and including a via having an opening at a second main surface, a first wiring disposed on the first main surface of the semiconductor device, partially exposed at a bottom surface of the via, and connected to the semiconductor circuit, a first insulating layer covering the first wiring, and a redistribution wiring extending from a contact portion in contact with the first wiring at the bottom surface of the via, through an inside of the via and onto the second main surface, where a first through hole is formed in the first wiring, and the contact portion is in contact with a plurality of surfaces of the first wiring.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 26, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Takuro Suyama
  • Patent number: 10658344
    Abstract: A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 19, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Matsuyama
  • Patent number: 10651053
    Abstract: The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shiang Liao, Chewn-Pu Jou
  • Patent number: 10643676
    Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sayed Mobin, John Thomas Contreras, Pranav Balachander
  • Patent number: 10636767
    Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 28, 2020
    Assignee: Invensas Corporation
    Inventor: Belgacem Haba
  • Patent number: 10617868
    Abstract: An implantable device having a biocompatible hermetic package made from a biocompatible electrically non-conductive substrate and a cover bonded to the substrate. In integrated circuit and passive circuits all bonded directly to the substrate.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 14, 2020
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Jerry Ok, Robert J Greenberg, Neil Hamilton Talbot, James S Little, Rongqing Dai, Jordan Matthew Neysmith, Kelly H McClure
  • Patent number: 10622294
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. Opposing edges of the upper card are located between vertical planes defined by the outer sidewalls of the upper portion of the casing.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 10616992
    Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 7, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yin-Ju Chen, Ming-Hao Wu, Cheng-Po Yu
  • Patent number: 10593653
    Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Yong Poo Chia
  • Patent number: 10566274
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami
  • Patent number: 10558525
    Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
  • Patent number: 10553513
    Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Hyun Park, Jae Choon Kim
  • Patent number: 10529651
    Abstract: A leadframe includes a common contact. A first transistor is disposed over the leadframe with a first interconnect structure of the first transistor disposed over the common contact. A second transistor is disposed over the leadframe with a second interconnect structure of the second transistor disposed over the common contact.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: January 7, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10522490
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 10515940
    Abstract: A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
  • Patent number: 10510687
    Abstract: Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Wensen Hung
  • Patent number: 10510726
    Abstract: A semiconductor device includes a base including interconnects, a first semiconductor chip including a first semiconductor element portion, and a second semiconductor chip including a second semiconductor element portion. The second semiconductor chip is electrically connected to the first semiconductor chip via at least one of the interconnects. The second semiconductor chip includes a first region, a first portion, and a second portion. The first region includes the second semiconductor element portion. The first portion is continuous with the first region. The second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction. The first direction is from the base toward the first region. The second portion, the first portion, and at least a portion of the first semiconductor chip each is positioned between the base and the first region.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 17, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tatsuya Kobayashi, Masayuki Uchida, Takashi Ito, Kazuo Shimokawa
  • Patent number: 10497670
    Abstract: A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-hoon Na, Hyun-jin Kim, Jang-woo Lee
  • Patent number: 10490528
    Abstract: Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 26, 2019
    Assignee: Invensas Corporation
    Inventors: Ashok S. Prabhu, Abiola Awujoola, Wael Zohni, Willmar Subido
  • Patent number: 10490461
    Abstract: A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 10475731
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 10467520
    Abstract: An RFID system includes an RFID antenna assembly configured to be positioned on a product module assembly of a processing system. The product module assembly is configured to releasably engage at least one product container. A first RFID tag assembly configured to be positioned on the at least one product container. The at least one product container is configured to position the first RFID tag assembly within a detection zone of the RFID antenna assembly whenever the product module assembly releasably engages the at least one product container.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 5, 2019
    Assignee: DEKA Products Limited Partnership
    Inventors: James J. Dattolo, David Blumberg, Jr., Eric J. VanWyk
  • Patent number: 10460771
    Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 29, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyun Chul Seo, Jun Sik Kim
  • Patent number: 10455691
    Abstract: An apparatus may include via pads and grid array pads associated with facilitating a connection through a package and to a component, and vias that are electrically connected to the via pads, wherein the vias are used to support high-speed differential signal pairs that are capable of causing crosstalk onto other high-speed differential signal pairs while propagating through the package. The apparatus may include interconnects that electrically connect the vias to the grid array pads, and that are capable of routing the high-speed differential signal pairs in a way that offsets the crosstalk that the high-speed differential signal pairs are capable of causing while propagating through the package. The apparatus may include additional interconnects that electrically connect the vias to additional vias that are to be used to facilitate routing the high-speed differential signal pairs to the component, without the high-speed differential signal pairs propagating through a printed circuit board.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 22, 2019
    Assignee: Juniper Networks, Inc.
    Inventor: David P. Chengson
  • Patent number: 10453818
    Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Chia-Wei Tu, Yian-Liang Kuo, Ru-Ying Huang
  • Patent number: 10453804
    Abstract: A package is described for a radio frequency die that has a backside conductive plate. One example includes a conductive plate, a semiconductor die having a front side and a back side, the back side being attached to the plate, a radio frequency component attached to the plate, a dielectric filled cavity in the plate adjacent to the radio frequency component, and a redistribution layer attached to the front side of the die for external connection.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Thorsten Meyer
  • Patent number: 10440788
    Abstract: An optoelectronic circuit including separate interconnected basic electronic circuits, each of which includes at least one light emitting diode and at least one integrated circuit chip that has a circuit for controlling the light emitting diode, the circuit being suitable for activating or deactivating the light emitting diode.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 8, 2019
    Assignee: Aledia
    Inventors: Frédéric Mercier, Xavier Hugon, Philippe Gilet
  • Patent number: 10426040
    Abstract: The invention relates to a method for producing a circuit board element having at least one electronic component, which component has a connection side defined by electrical contacts or a conductive layer and is connected to a temporary carrier for positioning and embedded in an insulating material; the component is attached in a specified position directly to a plastic film as a temporary carrier, whereupon a composite layer having at least a carrier and an electrical conductor, preferably also having an insulating material, is attached on the side of the component opposite the plastic film, with the carrier facing away from the component, and thereafter the plastic film is removed; then the component is embedded in insulating material. After the embedding of the component in the insulating material, an additional composite layer is preferably attached to the component and the embedding of the component on the side opposite the first composite layer.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: September 24, 2019
    Assignee: AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Johannes Stahr, Andreas Zluc
  • Patent number: 10403582
    Abstract: Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, an electronic component mounted on a surface of the substrate, and a composite molding member having conductivity that covers the surface of the substrate so as to embed the electronic component and that is connected to the power supply pattern. The composite molding member includes a resin material and a first filler blended in the resin material and containing 32 to 39 wt. % of a metal material composed mainly of Ni in Fe.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 3, 2019
    Assignee: TDK CORPORATION
    Inventor: Kenichi Kawabata
  • Patent number: 10396029
    Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koujirou Matsui, Takehiko Sakamoto, Kazuyuki Umezu, Tomoaki Uno
  • Patent number: 10381329
    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 10381327
    Abstract: A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: August 13, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Venkatesh P. Ramachandra, Michael Mostovoy, Hem Takiar, Gokul Kumar, Vinayak Ghatawade
  • Patent number: 10375867
    Abstract: The present invention provides an electronic device which includes an electromagnetic shield, can keep down a production cost, can be made to have a reduced thickness, and has a high degree of freedom in designing a wiring circuit. Further, the present invention provides a method for producing such an electronic device. The electronic device (1A) includes at least one high frequency functional component (21), an electrically conductive member (10) which electromagnetically shields the at least one high frequency functional component (21), and a resin molded body (23) in which at least part of the high frequency functional component (21) and at least part of the electrically conductive member (10) are embedded and fixed.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: August 6, 2019
    Assignee: OMRON Corporation
    Inventor: Wakahiro Kawai
  • Patent number: 10366727
    Abstract: A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyun Chul Seo, Jun Sik Kim
  • Patent number: 10361173
    Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package has a semiconductor die having pads thereon, first vias disposed on the first semiconductor die, the first vias coupled to the pads. A second semiconductor package is stacked on the first semiconductor package and includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface, a first memory die mounted on the bump-attach surface, coupled to the body, and a second memory die mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first memory die is different from the number of input/output (I/O) pins of the second memory die.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 23, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Ming-Tzong Yang
  • Patent number: 10354983
    Abstract: An embodiment package-on-package (PoP) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound. The plurality of conductive studs is attached to contact pads on the logic chip.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 10355337
    Abstract: A base carries a first chip and a second chip oriented differently with respect to the base and packaged in a package. Each chip integrates an antenna and a magnetic via. A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips even if the magnetic path is interrupted, and is formed by a first stretch coupled between the first magnetic-coupling element of the first chip and the first magnetic-coupling element of the second chip, and a second stretch coupled between the second magnetic-coupling element of the first chip and the second magnetic-coupling element of the second chip. The first stretch has a parallel portion extending parallel to the faces of the base. The first and second stretches have respective transverse portions extending on the main surfaces of the second chip, transverse to the parallel portion.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10354976
    Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 16, 2019
    Assignee: Invensas Corporation
    Inventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
  • Patent number: 10336610
    Abstract: A method for producing a micromechanical component is provided, In a preparatory step, a substrate device of the micromechanical component and/or a cap device of the micromechanical component is patterned. In a first sub-step, a first pressure and/or a first chemical composition being adjusted, and the substrate device and the cap device being connected to each other so that a first cavern is formed, sealed from an environment of the micromechanical component, the first pressure prevailing in the first cavity and/or the first chemical composition being enclosed. In a second sub-step, a second pressure and/or a second chemical composition being adjusted, and the substrate device and the cap device being connected to each other so that a second cavity is formed, sealed from the environment of the micromechanical component and from the first cavity, the second pressure prevailing in the second cavity and/or the second chemical composition being enclosed.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 2, 2019
    Assignee: ROBERT BOSCH GMBH
    Inventors: Heiko Stahl, Andreas Scheurle, Hendrik Specht, Marlene Winker, Ralf Hausner, Volker Schmitz