For Plural Devices Patents (Class 257/723)
  • Patent number: 11122697
    Abstract: An electronic medical device is disclosed here. An exemplary embodiment of the medical device includes a printed circuit board assembly, a protective inner shell surrounding at least a portion of the printed circuit board assembly, and an outer shell surrounding at least a portion of the protective inner shell. The printed circuit board assembly has a printed circuit board, electronic components mounted to the printed circuit board, a battery mounted to the printed circuit board, and an interface compatible with a physiological characteristic sensor component. The protective inner shell is formed by overmolding the printed circuit board assembly with a first material having low pressure and low temperature molding properties. The outer shell is formed by overmolding the protective inner shell with a second material that is different than the first material.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 14, 2021
    Assignee: MEDTRONIC MINIMED, INC.
    Inventors: Claire F. Ferraro, Shelley L. Thurk
  • Patent number: 11107758
    Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Sao-Ling Chiu
  • Patent number: 11075152
    Abstract: A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam Kang, Bong Ju Cho, Young Gwan Ko, Moon Il Kim
  • Patent number: 11075147
    Abstract: A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Vivek Arora, Ken Pham
  • Patent number: 11069734
    Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 20, 2021
    Assignee: INVENSAS CORPORATION
    Inventor: Rajesh Katkar
  • Patent number: 11056474
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 11049542
    Abstract: A semiconductor device may include: a first chip, configured to receive a command and an address; and a second chip, configured to receive the command and the address. The first chip may include: a weak cell address storage circuit configured to store a weak cell address; a refresh control circuit configured to generate a refresh address based on the weak cell address, when the second chip is selected by a chip address; and a bank in which a refresh operation is performed by the refresh address.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Na Yeon Kim
  • Patent number: 11037887
    Abstract: A method includes bonding a plurality of dies to a substrate. A first die of the plurality of dies is larger than a second die of the plurality of dies. The method includes adhering a first stress relief structure to the substrate. A distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method includes adhering a second stress relief structure to the substrate. A distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance. The first stress relief structure is discontinuous with respect to the second stress relief structure.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 11018123
    Abstract: A multi-chip module includes a first semiconductor component including a first set of connections having a first pitch dimension and at least a second set of connections having a second pitch dimension, wherein the first pitch dimension is smaller than the second pitch dimension. The multi-chip module further includes a second semiconductor component interconnected with the first set of connections of the first semiconductor component. The multi-chip module further includes at least a third semiconductor component interconnected with the second set of connections of the first semiconductor component and wherein a surface of the third semiconductor component is adhered to a surface of the second semiconductor component, wherein the surfaces at least partially overlap one another.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10998295
    Abstract: A semiconductor device includes: a first chip to restrict current flow in a first direction through a current path; a second chip to restrict the current flow in a second direction opposite to the first direction, through the current path; a wiring having one end connected to the first chip and the other end connected to the second chip, and provided as a part of the current path by relaying the first chip and the second chip; a lead frame having a first lead arranged and fixed with the first chip and a second lead is arranged and fixed with the second chip; and molding resin sealing the first chip, the second chip, the wiring and the lead frame. The wiring is a shunt resistor having a resistive body. The lead frame further has a sense terminal to detect a voltage drop across the resistive body.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: May 4, 2021
    Assignee: DENSO CORPORATION
    Inventors: Hiromasa Hayashi, Shunsuke Tomoto, Yusuke Mori
  • Patent number: 10998364
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes an image sensing element arranged within a substrate. One or more isolation structures are arranged within one or more trenches disposed on opposing sides of the image sensing element. The one or more isolation structures extend from a first surface of the substrate to within the substrate. The one or more isolation structures respectively include a reflective element configured to reflect electromagnetic radiation.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Cheng-Yuan Tsai, Keng-Yu Chou, Yeur-Luen Tu
  • Patent number: 10991681
    Abstract: A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The three-dimensional package structure is applicable to a POL, (Point of Load) converter.
    Type: Grant
    Filed: February 2, 2020
    Date of Patent: April 27, 2021
    Assignee: CYNTEC CO., LTD.
    Inventors: Da-Jung Chen, Chun-Tiao Liu, Chau-Chun Wen
  • Patent number: 10978392
    Abstract: An electrical chip includes a plurality of electrical signal processing circuits arranged side by side on a chip board, the electrical signal processing circuits that processes electrical signals transmitted to each of a plurality of lanes for each lane; and a power supply wiring network provided in an area overlapping with each of the plurality of electrical signal processing circuits and including wires formed into a mesh shape for supplying power to each of the plurality of electrical signal processing circuits, wherein the power supply wiring network includes a slit obtained by separating a part of the wires in each area corresponding to a boundary between the lanes.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: April 13, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Teruaki Yagoshi
  • Patent number: 10971441
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 10971476
    Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Ratibor Radojcic, Dong Wook Kim
  • Patent number: 10957679
    Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 23, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 10943843
    Abstract: A semiconductor package structure includes a conductive trace layer, a semiconductor die over the conductive trace layer, a structure enhancement layer surrounding the semiconductor die, and an encapsulant covering the semiconductor die and the structure enhancement layer. The structure enhancement layer coincides with a mass center plane of the semiconductor package structure. The mass center plane is parallel to a top surface of the semiconductor die. A method for manufacturing the semiconductor package structure is also provided.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiu-Chi Liu, Hsu-Nan Fang
  • Patent number: 10929636
    Abstract: An ultrasonic fingerprint sensor system of the present disclosure may be provided with a thick electrically nonconductive acoustic layer and thin electrode layer coupled to a piezoelectric layer of an ultrasonic transmitter or transceiver. The thick electrically nonconductive acoustic layer may have a high density or high acoustic impedance value, and may be adjacent to the piezoelectric layer. The thin electrode layer may be divided into electrode segments. The ultrasonic fingerprint sensor system may use flexible or rigid substrates, and may use an ultrasonic transceiver or an ultrasonic transmitter separate from an ultrasonic receiver.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yipeng Lu, Hrishikesh Vijaykumar Panchawagh, Kostadin Dimitrov Djordjev, Chin-Jen Tseng, Nicholas Ian Buchan, Tsongming Kao, Jae Hyeong Seo
  • Patent number: 10910355
    Abstract: A bezel-free display comprises a display substrate and an array of pixels. Pixel rows and pixel columns are separated by row and column distances and connected by row and column lines, respectively. A column driver is electrically connected to each of the column lines and a row driver is electrically connected to each of the row lines. Row-connection lines are electrically connected to each of the row lines or row drivers. In certain embodiments, each pixel in the column of pixels closest to a display substrate edge is spatially separated from the edge by a distance less than or equal to the column distance. At least one row driver is spatially separated from the corresponding row by a distance less than the column or row distance, at least one column driver is spatially separated from the corresponding column by a distance less than the column or row distance, or both.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 2, 2021
    Assignee: X Display Company Technology Limited
    Inventors: Ronald S. Cok, Brook Raymond
  • Patent number: 10879153
    Abstract: Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip package structure further includes a first photosensitive layer formed around sidewalls of the first chip and covering a top surface of the first chip and a second chip disposed over the first photosensitive layer. In addition, the first chip and the second chip are separated by the first photosensitive layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 10881004
    Abstract: An electronic component embedded substrate includes a first electronic component; a first insulating material covering at least a portion of the first electronic component; a first wiring layer disposed on one surface of the first insulating material; a second electronic component disposed on the first wiring layer and connected to the first electronic component by the first wiring layer; and a second insulating material covering at least a portion of the second electronic component, wherein the at least a portion of the first electronic component is exposed from the other surface of the first insulating material, opposite to the one surface of the first insulating material.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Eun Lee, Yong Hoon Kim, Kyung Hwan Ko
  • Patent number: 10850973
    Abstract: A Microelectromechanical systems (MEMS) structure comprises a MEMS wafer. A MEMS wafer includes a handle wafer with cavities bonded to a device wafer through a dielectric layer disposed between the handle and device wafers. The MEMS wafer also includes a moveable portion of the device wafer suspended over a cavity in the handle wafer. Four methods are described to create two or more enclosures having multiple gas pressure or compositions on a single substrate including, each enclosure containing a moveable portion. The methods include: A. Forming a secondary sealed enclosure, B. Creating multiple ambient enclosures during wafer bonding, C. Creating and breaching an internal gas reservoir, and D. Forming and subsequently sealing a controlled leak/breach into the enclosure.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 1, 2020
    Assignee: INVENSENSE, INC.
    Inventors: Michael Daneman, Martin Lim, Kegang Huang, Igor Tchertkov
  • Patent number: 10777537
    Abstract: An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Didier Lattard, Sebastien Thuries
  • Patent number: 10756005
    Abstract: A semiconductor device including one or more semiconductor dice, a lead frame including an array of signal-carrying leads electrically coupled with the semiconductor die, and a power supply connection for the at least one semiconductor die arranged centrally thereof.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10720409
    Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Hsien Huang, Yueh-Ting Lin, Wei-Yu Chen, An-Jhih Su
  • Patent number: 10720416
    Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 10714443
    Abstract: A semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 14, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hirokazu Saito
  • Patent number: 10707171
    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Tomita Yoshihiro, Eric J. Li, Shawna M. Liff, Javier A. Falcon, Joshua D. Heppner
  • Patent number: 10699983
    Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-soo Kim, Yong-hoon Kim, Hyun-ki Kim, Kyung-suk Oh
  • Patent number: 10699988
    Abstract: A method of forming a chip package structure can include: forming a substrate; forming a first cavity in the substrate; and installing a first chip in the first cavity. The method can also include forming a second cavity in the substrate; and installing a second chip in the second cavity. The first cavity is located at a first side of the substrate, and the second cavity is located at a second side of the substrate, where the first side of the substrate is opposite to the second side of the substrate.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 30, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Shijie Chen
  • Patent number: 10679951
    Abstract: A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tzu-Shiun Sheu, Shin-Puu Jeng, Shih-Peng Tai, An-Jhih Su, Chi-Hsi Wu
  • Patent number: 10665538
    Abstract: A semiconductor apparatus includes a semiconductor device having a semiconductor circuit formed on a first main surface, and including a via having an opening at a second main surface, a first wiring disposed on the first main surface of the semiconductor device, partially exposed at a bottom surface of the via, and connected to the semiconductor circuit, a first insulating layer covering the first wiring, and a redistribution wiring extending from a contact portion in contact with the first wiring at the bottom surface of the via, through an inside of the via and onto the second main surface, where a first through hole is formed in the first wiring, and the contact portion is in contact with a plurality of surfaces of the first wiring.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 26, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Takuro Suyama
  • Patent number: 10665568
    Abstract: To provide a technique of preventing, in an encapsulated circuit module having a metal shield layer covering a surface of a resin layer containing filler, the shield layer from falling off. In manufacturing encapsulated circuit modules, first, a substrate 100 is covered with a first resin 400 containing filler together with an electronic component 200. Next, a surface of the first resin 400 is covered with a second resin 500 containing no filler. Subsequently, a ground electrode 110 in the substrate 100 is exposed by snicking and then a shield layer 600 that covers the entire surface of the substrate 100 is formed by electroless plating. Thereafter, snipping is performed to obtain a number of encapsulated circuit modules.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 26, 2020
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Satoru Miwa
  • Patent number: 10665536
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Chewn-Pu Jou
  • Patent number: 10658344
    Abstract: A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 19, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Matsuyama
  • Patent number: 10651053
    Abstract: The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shiang Liao, Chewn-Pu Jou
  • Patent number: 10643676
    Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sayed Mobin, John Thomas Contreras, Pranav Balachander
  • Patent number: 10636767
    Abstract: Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 28, 2020
    Assignee: Invensas Corporation
    Inventor: Belgacem Haba
  • Patent number: 10617868
    Abstract: An implantable device having a biocompatible hermetic package made from a biocompatible electrically non-conductive substrate and a cover bonded to the substrate. In integrated circuit and passive circuits all bonded directly to the substrate.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 14, 2020
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Jerry Ok, Robert J Greenberg, Neil Hamilton Talbot, James S Little, Rongqing Dai, Jordan Matthew Neysmith, Kelly H McClure
  • Patent number: 10622294
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in the casing, and for forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. Opposing edges of the upper card are located between vertical planes defined by the outer sidewalls of the upper portion of the casing.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 10616992
    Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 7, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yin-Ju Chen, Ming-Hao Wu, Cheng-Po Yu
  • Patent number: 10593653
    Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Yong Poo Chia
  • Patent number: 10566274
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami
  • Patent number: 10558525
    Abstract: A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
  • Patent number: 10553513
    Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Hyun Park, Jae Choon Kim
  • Patent number: 10529651
    Abstract: A leadframe includes a common contact. A first transistor is disposed over the leadframe with a first interconnect structure of the first transistor disposed over the common contact. A second transistor is disposed over the leadframe with a second interconnect structure of the second transistor disposed over the common contact.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: January 7, 2020
    Assignee: Great Wall Semiconductor Corporation
    Inventor: Patrick M. Shea
  • Patent number: 10522490
    Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 10515940
    Abstract: A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
  • Patent number: 10510726
    Abstract: A semiconductor device includes a base including interconnects, a first semiconductor chip including a first semiconductor element portion, and a second semiconductor chip including a second semiconductor element portion. The second semiconductor chip is electrically connected to the first semiconductor chip via at least one of the interconnects. The second semiconductor chip includes a first region, a first portion, and a second portion. The first region includes the second semiconductor element portion. The first portion is continuous with the first region. The second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction. The first direction is from the base toward the first region. The second portion, the first portion, and at least a portion of the first semiconductor chip each is positioned between the base and the first region.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 17, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tatsuya Kobayashi, Masayuki Uchida, Takashi Ito, Kazuo Shimokawa
  • Patent number: 10510687
    Abstract: Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Wensen Hung