Method of and apparatus for thermal energy-to-electrical energy conversion using charge carrier excitation transfer through electrostatic coupling between hot and relatively cold juxtaposed surfaces separated by a small gap and using single carrier cold-side conversion

Abstract

An improved method of and apparatus for thermal-to-electric conversion involving relatively hot and cold juxtaposed surfaces separated by a small vacuum gap wherein the cold surface provides an array of single charge carrier converter elements along the surface and the hot surface transfers excitation energy to the opposing cold surface across the gap through Coulomb electrostatic coupling interaction.

Description

FIELD OF INVENTION

The present invention relates generally to the conversion of thermal energy to electric energy, being more particularly concerned with such conversion as effected by gap-separated juxtaposed hot-side radiator and cold-side charged carrier converter structures.

BACKGROUND OF INVENTION

Spurred by the initial proposal to effect such conversion using a thermo-photovoltaic approach (U.S. Pat. No. 6,084,173, issued Jul. 4, 2000 to Robert DiMatteo), we have been exploring the possibility of a coherent excitation transfer at such gaps that can produce a further increase in the throughput power. This led us to the theoretical proposal of developing a single charge carrier converter in which the excitation may be transferred very close to the gaps, as described in our Massachusetts Institute of Technology Research Laboratory for Electronics internal report (RLE 147 of September, 2005) entitled ‘Thermal to Electric Conversion based on a Quantum-Coupling Scheme’. Since this is pertinent to the present invention, its basic scheme will hereinafter be described in connection with FIG. 1.

While this provided an idealized outline of possible operation, it was not, however, until an unexpected breakthrough occurred quite recently that opened the door to a practically implementable device. That breakthrough resulted in a novel combination of coherent excitation transfer through electrostatic coupling between a relatively hot-sidesurface and a small-gap-separated juxtaposed cold-side converter surface, wherein the latter is of a novel single-carrier cold side converter construction. The DiMatteo proposal suggests that the gap be a vacuum gap; but what is important is that his gap should not comprise a solid or liquid. It may be a gas, and even more preferably, it could be a diluted gas with the mean-free-path longer than the gap separation.

The implementation of practical devices through fabrication by now well-known solid-state chip manufacturing technologies is now achievable, promising thermal-to-electric converter arrays of this character offering high power potential.

OBJECTS OF INVENTION

It is thus a primary object of the invention to provide a new and improved thermal-to-electric energy conversion method and novel apparatus or device structure utilizing the same, embodying an improved hot surface and a juxtaposed relatively cold converter surface separated by a small gap.

A further object is to provide such an apparatus employing novel excitation transfer through electrostatic coupling between the relatively hot and cold surfaces together with a new single-carrier cold-side converter chip-like structure.

Still another object is to provide novel chip arrays of such structures.

Other and further objects will be described hereinafter and will be more particularly pointed out in connection with the appended claims.

SUMMARY

In summary, from one of its viewpoints, the invention embraces a method of converting thermal to electric energy, that comprises, juxtaposing relatively cold-side conversion and relatively hot-side surfaces separated by a small gap; providing lower state electrons on or near the cold surface; Coulomb-coupling the lower state electrons to corresponding image charges on the hot surface; transferring energy from the hot-side surface through the image carrier coupling to said cold-side surface lower state electrons to excite them to a higher state; collecting the higher state electrons at or near the cold surface to generate a higher potential; and extracting the converted electric energy in response to said higher potential.

In its structure or device aspect, the invention embodies in a thermal-to-electric conversion apparatus, relatively hot and cold juxtaposed surfaces separated by a small gas or vacuum gap, the cold surface providing a chip array of single charge carrier converter elements, and the hot surface electrostatically transferring excitation energy to the opposing cold surface converter elements across the gap through Coulomb electrostatic coupling interaction.

Preferred designs and embodiments, including a best mode design, are hereinafter more fully presented.

DRAWINGS

The invention will now be described in connection with the accompanying drawings, the previously mentioned FIG. 1 of which is a basic schematic diagram of an idealized conception underlying the invention;

FIG. 2 is an expanded isometric schematic view of a preferred device for practicing the methodology of the invention embodying solid state conversion arrays as implementation;

FIG. 3 is a similar diagram of such an array of the novel thermal-to-electric converter elements of the type shown in FIG. 2; and

FIGS. 4 and 5 are respective load power density and efficiency of performance graphs attainable with such an embodiment of the invention.

DESCRIPTION OF PREFERRED EMBODIMENT (S)

Turning first to the roadmap of our said FIG. 1, this involves an idealized theoretical explanatory scheme consisting of a hot-side surface S_H and a juxtaposed cold-side carrier charge-to-electricity converter surface Sc separated by a small vacuum gap g. On the cold side, there is schematically shown a first quantum well W_C1 having a lower electron potential level 1 and an upper level 2 and wherein an electron is introduced or supplied into the lower level or state 1 from a source of electrons called a reservoir r₁, which may be at relative ground potential. As later explained, in practical implementation, the well W_C1 may be inherently provided in a quantum dot, such as an appropriate semi-conductor dot, and the electron reservoir r₁ may be a conductor of a conducting network interconnecting such dots in an array or matrix of dots distributed along the cold-side S_C as later more fully described in connection with the embodiments of FIGS. 2 and 3.

Electrostatic coupling to the hot side surface S_H produces a quantum-correlated image well charge on the hot side, This appears schematically in FIG. 1 as a well W_H with two levels connected to an electron reservoir r_h. As an electron is supplied from the cold-side reservoir r₁ to the cold-side level 1 of the well W_C1, accordingly, Coulomb electrostatic coupling between that electron and a matched carrier charge imaged on the hot side produces a quantum correlation between the cold side electron and such carrier, providing electrostatic interaction U that leads to excitation energy transfer from the hot side to the cold side, thereby elevating the electron in the cold-side well W_C1 up to higher potential level or state 2, as indicated by the upward arrow portion shown below the symbol U. From this upper state 2, the electron may tunnel, as shown schematically at V, through a potential barrier PB to a matched level 2¹ in a second quantum dot well WC₂ on its way to a second reservoir r₂ which is at elevated voltage relative to ground, as schematically illustrated at +. The well W_C2 permits only one level—level 2¹. The two cold-side reservoirs r₁ and r₂ are connected together through an electrical load, so-labeled. Thus, when elections are promoted in the first quantum well W_C1, they have the possibility of tunneling to the second well W_C2 and then continuing on to do electrical work before ending up in the first reservoir r₁ at ground.

The level of the hot-side well W_H relaxes to an electron reservoir r_h comprising a continuum of excitation levels, wherein the level a is coupled to each level in the reservoir with a matrix element m₂. Similarly, level b is coupled to each level in the corresponding continuum with matrix element m₃.

Electric fields between an electron on the hot side well W_H and an electron on the cold side, couple the product states |b>1> and |a>2> with coupling U such that excitation transfer can occur across the gap g. Level 1 of the well W_C1, in turn, relaxes to reservoir r₁ with matrix element m₁ and level 2′ of well W_C2 relaxes to reservoir r₂ with matrix element m₄.

The basic mechanism of the device is that high temperature on the hot side results in excited electrons in the hot-side image, with excitation transferred via electrostatic interaction coupling U (between the hot-side image charge, which is itself coupled to excited electrons and phonon modes, and the cold-side electron) to promote a cold-side electron from level 1 to level 2 in well W_C1.

In summary, thus, an electron reservoir on the cold side supplies an electron to a lower state; and coupling with the hot side causes the electron to be promoted to an excited state, and then the electron proceeds to a second electron reservoir at elevated potential. An electrical load connected between the two reservoirs can be driven from the electrical current caused by the promoted electrons. Such a scheme can work with either electrons or holes (or in principle, both). We have called it a “single carrier converter” since, in accordance with the invention, it is only a single carrier that is promoted at a time, as opposed to photovoltaics, as in the before-mentioned DiMatteo patent, in which electron-hole pairs are created.

Physical Implementations

FIG. 2 presents an exploded view of a preferred physical structure of a thermal-electric converter constructed in accordance with the invention to operate in accordance with the methodology thereof as outlined in FIG. 1. As before explained, the cold-side surface S_c of the device is shown juxtaposed to the hot-side heat emitter surface S_H with, for example, a micron or larger-dimensional vacuum gap g therebetween. The cold-side converter comprises an array of appropriate semi-conductor small elements or dots, two of which are shown as “Dot 1” and “Dot 2”, implemented as by well-known chip technology and in a chip substrate matrix schematically illustrated by S. In practice, these semi-conductor converter dots may assume any desired geometry, such as the rectangular boxes or bar elements shown, supporting and serving as quantum-confined electron energy excitation state wells (W_C1 and W_C2, FIG. 1) along (at or near) the surface S_c. Other forms of these semi-conductor elements may include small cylinders or wires, small quantum-well sheets or even molecules. The array of dot elements or the like will be conductor-interconnected, as earlier mentioned by, a network of conductors feeding and outputting electrons to and from the respective elements (reservoir r₁, r₂, etc. in FIG. 1) interconnecting the array of dot elements in series and/or in parallel fashion, as appropriate, and also formed into the substrate matrix S of the converter chip side of the device. In the device of FIG. 2, moreover, segments of these electron “reservoir” conductors are shown at “Reservoir 1” (r₁ in FIG. 1) and at “Reservoir 2” (r₂ in FIG. 1) as rectangular cross-section bus portions.

The breakthrough realization, in accordance with the invention, that in an appropriately dimensioned structure, the charge movement in the quantum dot on the cold side surface S_c will promote movement in the image charge on the nearby conductive hot-side surface S_H, and that this movement of the image charge would constitute a surface current, led to the two-level system model of the invention herein presented and with the same dynamics as the image charge, and hence the same classical power description. It has been found, moreover, that the equivalent coupling strength is quite large and independent of the gap thickness, at least in the limit that the system is electroquasistatic.

In the device of FIG. 2, the hot side surface S_H may accordingly be a simple flat surface as of a metal, semi-metal or highly doped semiconductor. The metal surface has surface image charges induced by the cold-side electrons and the charges act as an effective dipole with zero energy separation that is coupled to thermally excited electrons and phonos. Across the gap g, the cold-side is shown as comprising the before-mentioned two quantum dots on the surface S_C; Dot 1 having two levels (well W_C1 of FIG. 1) and they couple to the hot-side imaged dipole (image well W_H of FIG. 1) via the electrostatic Coulomb coupling interaction before described. Dot 2 has one level (in well W_C2 of FIG. 1) and it couples to the excited upper level of Dot 1 (state 2 in well W_C1 of FIG. 1) through the tunneling (V). The lower level of Dot 1 (level 1 in well W_C1), as before stated, relaxes to the ground voltage conductor Reservoir 1 (r₁ in FIG. 1). The Dot 2 level relaxes to conductor Reservoir 2 which is at the elevated voltage +. Reservoir conductor 1 is shown having a horizontal branch bus portion extending from the vertical leg of the bus conductor in order to couple the lower level of Dot 1, the branch being oriented horizontally to Dot 1 and facing the center of Dot 1, with a distance. Reservoir conductor 2 is shown parallel to Dot 1 and it runs parallely along the surface S_C next to Dot 2, with a distance. Where desired, these dot and conductor elements may also be oriented at other angles, including substantially perpendicular to the plane of the surface S_C.

The cold-side structure is repeated as an array over the surface S_C as shown in FIG. 3, with the Reservoir 1 conductor buses linked together, and the Reservoir 2 conductor buses linked together, and within Reservoirs 1 and 2 connected through the load as in FIG. 1.

In a simulated specific structural design of this implementation, we obtained the following exemplary results. The temperature on the hot-side is 1300K, and that on the cold-side, 300K. Dot 1 has x×y×z dimension 120 Å×100 Å×100 Å and is of the preferred material InSb. The energy separation of the Dot 1 levels is 0.2 eV. The relaxation time of InSb at 0.2 eV is 1.ps. The hot-side is metallic copper, in this equipment, of which relaxation time at 0.2 eV is 0.57 fs. Dot 2 has dimension 50 Å×100 Å×100 Å and is horizontally pointing to the top part of Dot 1. (FIG. 2 is not drawn to scale). Dot 2 is of material Ga_0.31In_0.69Sb. The distance between Dot 1 and Dot 2 is 100 Å. Reservoir 1 branch is horizontally positioned 50 Å away from the center of Dot 1. Reservoir 2 is located 50 Å next to Dot 2. Both reservoirs are preferably made up of n-type InSb doped such that its relaxation time at 0.2 eV is 10 ps. The relaxation time for an n-type InSb with doping level 3×10¹⁷ cm⁻³ at 0.2 eV is 52 ps, and it is expected that the relaxation time will decrease to zero as the doping increases, since this is the behavior at DC. Therefore there exists a doping level with any desired relaxation time. The surrounding matrix material substrate on the cold side is preferably GaSb.

As before mentioned, the electrostatic interaction between the surface charge and the cold-side dipole is independent of the vacuum gap thickness in the electroquasistatic regime. For thicknesses greater than the wavelength corresponding to the energy separation of cold-side levels 1 and 2 divided by 2π, however, the effects of transverse photons may compromise the device performance. The absorption wavelength corresponding to 0.2 eV is 6.2 μm, and hence the gap should be below about 1 μm in this case.

Shown in FIG. 4 and FIG. 5 are the power on load density and efficiency, respectively, as a function of voltage for the device. This is based upon the assumption that each device unit occupies an area of 1000 Å×1000 Å=10⁻¹⁰ m². The calculated maximum power on load density is 202 W/cm occurring at voltage 107 mV. FIG. 5 shows that the maximum efficiency 49.8% occurs at voltage 129 mV and the corresponding power on load density is 173 W/cm².

Further modifications will occur to those skilled in the art and such are considered to fall within the spirit and scope of the invention as defined in the appended claims.

Claims

1. In a thermal-to-electric conversion apparatus, relatively hot and cold juxtaposed surfaces separated by a small vacuum or gas gap, the cold surface providing a chip array of single charge carrier converter elements, and the hot surface electrostatically transferring excitation energy to the opposing cold surface converter elements across the gap through Coulomb electrostatic coupling interaction.

2. The conversion apparatus of claim 1 wherein an electron from a first electron reservoir is introduced into a lower level excitation state of each of the converter elements on the cold surface, and then Coulomb-couples across the gap to a carrier charge on the hot surface, producing a quantum correlation therebetween that leads to excitation transfer from the hot surface to the cold surface that promotes said electron to a higher level excitation state.

3. The conversion apparatus of claim 2 wherein said excited higher level state electron thereupon tunnels to a second cold-surface electron reservoir maintained at an elevated potential relative to said first reservoir, and an electrical load is connected between the reservoirs and driven by the current caused by the promoted electron(s).

4. The conversion apparatus of claim 3 wherein only a single type carrier charge is promoted at a time.

5. The conversion apparatus of claim 4 wherein the single carrier charge is one of electrons or holes.

6. The conversion apparatus of claim 3 wherein the converter elements comprise an array of semi-conductor elements that are chip-integrated along the cold surface in a matrix substrate and interconnected by a network of electron reservoir conductors or buses within the chip substrate to provide the appropriate series and/or parallel connections amongst and between the elements of the array.

7. The conversion apparatus of claim 6 wherein the sets of said respective first and second electron reservoir conductors or buses in the array are commonly connected to opposite sides of said load.

8. The conversion apparatus of claim 6 wherein the semi-conductor elements are of InSb material and/or Ga0.31In0.69Sb material.

9. The conversion apparatus of claim 6 wherein the material of the hot surface is selected from the group consisting of flat metal, metallic copper, semi-metal, and highly doped semiconductor material.

10. The conversion apparatus of claim 6 wherein the election reservoir conductors or buses are of doped n-type InSb.

11. The conversion apparatus of claim 6 wherein the chip matrix substrate on the cold side is GaSb.

12. The conversion apparatus of claim 6 wherein the hot surface is about 1300K and the relatively cold surface is about 300K.

13. The conversion apparatus of claim 6 wherein the carrier converter elements are in the form of an array of one or more of semi-conductor dots or bars of varied geometry, semi-conductor short cylinders or wires, and small sheets providing quantum wells integrated within the chip substrate.

14. The conversion apparatus of claim 13 wherein the semi-conductor elements and the interconnecting conductors or buses are integrated in the substrate, with some oriented parallel to the cold surface, and some horizontally and/or vertically oriented.

15. The conversion apparatus of claim 13 wherein dimensions of the dots or bars are of the order of about 50 to 120 Å.

16. A method of converting thermal to electric energy, that comprises, juxtaposing relatively cold-side conversion and relatively hot-side radiating surfaces separated by a small gap; providing lower state electrons on or near the cold surface; Coulomb-coupling the lower state electrons to the carrier charges on the hot surface; transferring heat from the hot-side surface through the coupling to said cold-side surface lower-state electrons to excite them to a higher state; collecting the higher state electrons at or near the cold surface to generate a higher potential; and extracting the resulting converted electric energy in response to said higher potential.

17. The method of claim 16 wherein the conversion cold-side surface comprises an array of interconnected converter elements each having respective quantum wells supporting the lower and higher electron states, and maintained at a ground potential.

18. The method of claim 17 wherein said collecting of the higher state electrons is effected by tunneling between such ground wells and higher potential wells on the cold side.

19. The method of claim 16 wherein the converter elements are caused to promote only a single type of carrier charge at a time.

20. The method of claim 19 wherein the single carrier type charge is one of electrons or holes.