Plasma display and voltage generator thereof
In a plasma display and a voltage generator thereof, a first electrode of a transistor is coupled to a scan electrode. In addition, a cathode of a Zener diode is coupled to a second electrode of the transistor, and an anode of the Zener diode is coupled to a power source generating a scan voltage. A first resistor is coupled between the first electrode of the transistor and a control electrode of the transistor, and a second resistor is coupled between the control electrode of the transistor and the anode of the Zener diode. A final voltage during a reset period is generated by the power source generating the scan voltage.
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for PLASMA DISPLAY AND VOLTAGE GENERATOR THEREOF earlier filed in the Korean Intellectual Property Office on 11 Sep. 2006 and there duly assigned Serial No. 10-2006-0087368.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a plasma display device and a voltage generator thereof.
2. Description of the Related Art
A plasma display uses a Plasma Display Panel (PDP) that uses a plasma generated by a gas discharge process to display characters or images. The PDP includes, depending on its size, more than several scores to millions of pixels arranged in a matrix pattern.
One frame of such a plasma display is divided into a plurality of subfields having weight values, and each subfield includes a reset period, an address period, and a sustain period. The reset period is for initializing the status of each discharge cell so as to facilitate an addressing operation on the discharge cell. The address period is for selecting turn-on/turn-off cells (i.e., cells to be turned on or off). In addition, the sustain period is for causing the cells to either continue a discharge for displaying an image on the addressed cells or to remain inactive.
In general, during the reset period, to initialize a state of the discharge cell, a voltage at the scan electrode is gradually increased to a Vset voltage, and is gradually decreased to a Vnf voltage. In addition, during the address period, a scan pulse having a scan voltage VscL and an address pulse having a Va voltage are respectively supplied to the scan and address electrodes of the discharge cell to be turned-on. In general, the VscL voltage and the Vnf voltage are set to be the same level. Accordingly, since an address discharge is not appropriately generated when the Vnf voltage is equal to the VscL voltage, a low discharge may be generated. In addition, when an address voltage level is increased to prevent the low discharge, the address discharge is generated in the turn-off discharge cell, and therefore misfiring may occur.
SUMMARY OF THE INVENTIONThe present invention has been made in an effort to provide a plasma display which prevents a low discharge and a driving method thereof.
In addition, the present invention has been made in an effort to provide a voltage generator for reducing the number of power sources in a plasma display which prevents a low discharge.
An exemplary plasma display according to an embodiment of the present invention includes: a scan electrode to receive a scan voltage; a power source to supply the scan voltage; a first transistor having a first electrode electrically coupled to the scan electrode; a Zener diode having a cathode electrically coupled to a second electrode of the first transistor and having an anode electrically coupled to the power source; at least one first resistor electrically coupled between the scan electrode and a control electrode of the first transistor; and at least one second resistor electrically coupled between the control electrode of the first transistor and the second electrode of the first transistor.
A voltage at the first electrode of the first transistor may be a first voltage higher than the scan voltage. The first voltage may be a final voltage finally supplied to the scan electrode during a reset period.
The plasma display may further include a second transistor electrically coupled between the anode of the Zener diode and the power source.
The second transistor may perform as a ramp switch to gradually decrease a voltage at the scan electrode to a first voltage higher than the scan voltage during a reset period upon the second transistor being turned on.
The plasma display may further include a third transistor electrically coupled between the scan electrode and the power source, the scan voltage being supplied to the scan electrode upon the third transistor being turned on.
At least one of the first and second resistors may be a variable resistor. At least one of the first and second resistors may be a resistor that varies according to temperature.
An exemplary voltage generator for generating a first voltage higher than a second voltage supplied by a power source includes: a Zener diode including an anode electrically coupled to the power source; a transistor including a first electrode electrically coupled to a cathode of the Zener diode; at least one first resistor electrically coupled between the anode of the Zener diode and a control electrode of the transistor; and at least one second resistor electrically coupled between the control electrode of the transistor and a second electrode of the transistor, the first voltage being generated at the second electrode of the transistor.
At least one of the first and second resistors may be a variable resistor.
The first and second voltages may drive a plasma display.
The second voltage may be a scan voltage supplied to a scan electrode of a plasma display, and the first voltage may be a final voltage finally supplied during a reset period of the plasma display.
A more complete appreciation of the present invention and many of the attendant advantages thereof, will be readily apparent as the present invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.
Throughout this specification and the claims which follow, when it is described that an element is “coupled” to another element, the element may be “directly coupled” to the other element or “electrically coupled” to the other element through a third element. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
In addition, wall charges mentioned in the following description mean charges formed and accumulated on a wall (e.g., a dielectric layer) close to an electrode of a discharge cell. A wall charge will be described as being “formed” or “accumulated” on the electrode, although the wall charges do not actually touch the electrodes. Furthermore, a wall voltage means a potential difference formed on the wall of the discharge cell by the wall charge.
When it is described in the specification that a voltage is maintained, it should not be understood to strictly imply that the voltage is maintained exactly at a predetermined voltage. To the contrary, even if a voltage difference between two points varies, the voltage difference is expressed to be maintained at a predetermined voltage in the case that the variance is within a range allowed in design constraints or in the case that the variance is caused due to a parasitic component that is usually disregarded by a person of ordinary skill in the art. In addition, since threshold voltages of semiconductor elements (e.g., a transistor and a diode) are very low compared to a discharge voltage, they are considered to be 0V.
A plasma display according to an exemplary embodiment of the present invention, and a voltage generator thereof is described below with reference to the drawing figures.
As shown in
The PDP 100 includes a plurality of address electrodes A1 to Am extending in a column direction, and a plurality of sustain and scan electrodes X1 to Xn and Y1 to Yn in pairs extending in a row direction. The sustain electrodes X1-Xn are formed in respective correspondence to the scan electrodes Y1 to Yn, and ends of the sustain electrodes X1-Xn are connected in common. In addition, the PDP 100 includes a substrate (not shown) having the sustain and scan electrodes X1-Xn and Y1 to Yn, and a substrate (not shown) having the address electrodes A1-Am. The two substrates are arranged to face each other with a discharge space between them so that the scan electrodes Y1 to Yn and the sustain electrodes X1-Xn may cross the address electrodes A1-Am. Discharge spaces provided at crossing regions of the address electrodes and X and Y electrodes form discharge cells. This formation of the plasma display panel 100 is an example, and other formations of a panel for supplying driving waveforms that will be described may be applied to the present invention.
The controller 200 receives external video signals, and outputs an address driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. In addition, the controller 200 divides a frame into a plurality of subfields, and each subfield has a reset period, an address period, and a sustain period in a temporal manner.
After receiving the address driving control signal from the controller 200, the address electrode driver 300 supplies a display data signal for selecting discharge cells to be displayed to the respective address electrodes A1 to Am.
The sustain electrode driver 500 receives the sustain electrode driving control signal from the controller 200, and supplies a driving voltage to the sustain electrodes.
The scan electrode driver 400 receives the scan electrode driving control signal from the controller 200, and supplies the driving voltage to the scan electrodes.
Driving waveforms of the plasma display according to the exemplary embodiment of the present invention are described below with reference to
As shown in
During the rising period of the reset period, while the A and X electrodes are maintained at a reference voltage (0V in
During the falling period of the reset period, the voltage at the Y electrode is gradually decreased from the Vs voltage to a negative voltage Vnf while the A electrode is maintained at the reference voltage and the X electrode is biased to a Ve voltage. While the voltage of the Y electrode decreases, a weak discharge occurs between the Y and X electrodes and between the Y and A electrodes. Accordingly, the negative (−) wall charges formed on the Y electrode and the positive (+) wall charges formed on the X and A electrodes are eliminated. In general, the Vnf voltage is usually set close to a discharge firing voltage between the Y and X electrodes. Then, the wall voltage between the Y and X electrodes becomes near 0V, and accordingly, a discharge cell that has not experienced an address discharge in the address period may be prevented from misfiring (the misfiring between the Y and X electrodes) in the sustain period. In addition, the wall voltage between the Y and A electrodes is determined by a level of the Vnf voltage, because the A electrode is maintained at the reference voltage.
Subsequently, during the address period, a scan pulse of a negative voltage VscL and an address pulse of a positive voltage Va are respectively supplied to Y and A electrodes to select discharge cells to be turned-on, while the X electrode is maintained at the Ve voltage. Non-selected Y electrodes are biased at a voltage VscH that is higher than the voltage VscL, and the reference voltage is supplied to the A electrodes of the turn-off cells (i.e., cells to be turned off). Then, the (+) wall charges are formed on the Y electrode and the (−) wall charges are formed on the A and X electrodes since an address discharge is generated on the discharge cell formed by the A electrode receiving the Va voltage and the Y electrode receiving the VscL voltage. For such an operation, the scan electrode driver 400 selects a Y electrode receiving the scan pulse of the scan voltage VscL among the Y electrodes Y1 to Yn. For example, in a single driving method, the Y electrode may be selected according to an order of arrangement of the Y electrodes in the vertical direction. When a Y electrode is selected, the address electrode driver 300 selects cells to be turned-on among cells formed on the selected Y electrode. That is, the address electrode driver 300 selects A electrodes to which the address pulse of the voltage of Va is supplied among the A electrodes A1 to Am.
In further detail, while the scan pulse of the VscL voltage is supplied to the scan electrode of a first row (Y1 in
The scan voltage VscL according to the exemplary embodiment of the present invention is lower than the Vnf voltage, which is a final voltage supplied to the Y electrode during the reset period, by a ΔV voltage. A reason why the address discharge is generated in the discharge cell when the scan voltage VscL is lower than the Vnf voltage and the Va voltage is supplied, and a reason why the low discharge is generated are described below.
During the reset period, when the Vnf voltage that is the final voltage is supplied to the Y electrode, a sum of the wall voltage between the A and Y electrodes and the externally supplied Vnf voltage between the A and Y electrodes is set to be a discharge firing voltage Vfay between the A and Y electrodes.
A discharge may normally be generated when the scan voltage VscL is supplied to the Y electrode and 0V is supplied to the A electrode during the address period, because a voltage that is higher than the Vfay voltage is formed between the A and Y electrode. However, in the above case, the discharge is not generated since a discharge delay is longer than widths of the scan and address pulses.
When the Va voltage is supplied to the A electrode and the scan voltage VscL is supplied to the Y electrode, the voltage that is higher than the Vfay voltage is formed between the A and Y electrodes, the discharge delay is reduced to be shorter than the widths of the scan and address pulses, and the discharge may be generated. In general, when the scan voltage that is equal to the Vnf voltage is supplied to the Y electrode, the discharge may be generated since the voltage that is higher than the Vfay voltage is formed between the A and Y electrodes. However, when the VscL voltage, which is lower than the Vnf voltage by the ΔV voltage, is supplied to the Y electrode as in the exemplary embodiment of the present invention, the voltage between the A and Y electrodes is further increased, the discharge delay is further reduced, and therefore, the address discharge may be appropriately generated. Accordingly, the low address discharge may be prevented.
During the sustain period, the sustain pulses of opposite phases, which are a high level voltage Vs and a low level voltage 0V, are supplied to the Y electrode and the X electrode. Then, a sustain discharge is generated in the selected discharge cell during the address period. The number of sustain pulses corresponds to the weight value of the corresponding subfield.
In general, as in the driving waveform according to the exemplary embodiment of the present invention, to differently set the Vnf voltage that is the final voltage during the reset period and the VscL voltage that is the scan voltage during the address period, it is necessary to separately provide a power source for generating the Vnf voltage and a power source for generating the VscL voltage. Hereinafter, the scan electrode driver 400 for generating two voltages using a single power source is described.
As shown in
The plurality of scan ICs 410 respectively include a transistor YH, a transistor YL, a terminal Ta, and a terminal Tb in common. A drain of the transistor YH is coupled to the terminal Ta, and a source of the transistor YL is coupled to the terminal Tb. A source of the transistor YH is coupled to a drain of the transistor YL, and a node of the transistors YH and YL is coupled to one of the scan electrodes Y1 to Yn. A voltage VscH is supplied to the terminal Ta by a power source VscH.
A drain of the transistor Yscl is coupled to the terminal Tb of the scan IC 410, and a source thereof is coupled to a power source VscL for supplying the VscL voltage. The ΔV voltage generator 420 is coupled between the terminal Tb and a drain of the transistor Yfr, and the source of the transistor Yfr is coupled to the power source VscL for supplying the VscL voltage. The transistor Yfr is a ramp switch, and it is turned on to supply a predetermined current to the Y electrode and gradually decreases the voltage at the Y electrode. A method of supplying the predetermined current to the Y electrode through the transistor Yfr and gradually decreasing the voltage at the Y electrode is well known to those skilled in the art, and therefore detailed descriptions thereof have been omitted. The ΔV voltage generator 420 generates a voltage ΔV (Vnf−VscL) shown in
The other Y electrode driving circuit 430 is coupled to the terminal Tb and the Y electrode, and generates various driving waveforms (e.g., the rising waveform of the reset period, and the sustain pulse) supplied to the Y electrode. The configuration of the other Y electrode driving circuit 430 is not directly related to the exemplary embodiment of the present invention, and therefore a description thereof has been omitted.
During the falling period of the reset period, the transistor Yfr and respective transistors YL of the plurality of scan ICs 410 are turned on, and the voltage at the Y electrode is gradually decreased to the voltage Vnf (VscL+ΔV) by the ΔV voltage generator 420. The voltage at the Y electrode is gradually decreased to the VscL voltage when the transistor Yfr is turned on, but the ΔV voltage generated by the ΔV voltage generator 420 is added, and therefore the voltage at the Y electrode is decreased to the voltage Vnf (VscL+ΔV).
During the address period, the transistor Yscl is turned on, the transistor YL of the scan IC corresponding to the scan electrode to be selected is turned on, and the scan voltage VscL is supplied to the corresponding Y electrode. The transistor YH is turned on and the VscH voltage is supplied to the Y electrode not to be selected in the scan IC corresponding to the Y electrode not to be selected.
Hereinafter, the ΔV voltage generator 420 for generating a voltage difference of ΔV is described in more detail with reference to
The ΔV voltage generator 420a includes a transistor Q1 and resistors R1 and R2. The transistor Q1 is a bipolar transistor.
A collector of the transistor Q1 is coupled to the terminal Tb of the plurality of scan ICs 410, and an emitter thereof is coupled to the drain of the transistor Yfr. A terminal of the resistor R1 is coupled to the collector of the transistor Q1 (i.e., the terminal Tb), and another terminal of the resistor R1 is coupled to a base of the transistor Q1. A terminal of the resistor R2 is coupled to the base of the transistor Q1 and another terminal of the resistor R2 is coupled to the emitter of the transistor Q1. In addition, the resistors R1 and R2 are coupled to each other, and a node thereof is coupled to the base of the transistor Q1.
When a current Io is low, the transistor Q1 is turned off, and the current Io flows to the resistors R1 and R2. However, when the current Io flows sufficiently enough to turn on the transistor Q1, the current Io flows to the resistors R1 and R2 and the transistor Q1. In this case, a collector-emitter voltage VCE of the transistor Q1 is given by Equation 1.
VCE=I1*R1+I2*R2 Equation 1
In Equation 1, when a base current of the transistor Q1 is ignored, the current I1 is given as I1≈I2. The current I2 is given as I2=VBE/R2. Accordingly, the collector-emitter voltage VCE of the transistor Q1 is given by Equation 2.
VCE=(1+R1/R2)*VBE Equation 2
The collector-emitter voltage VCE of the transistor Q1 is the ΔV voltage generated by the ΔV voltage generator 420a. Referring to Equation 2, the collector-emitter voltage (VCE=ΔV) of the transistor Q1 may be established to be a desired value in proportion to a base-emitter voltage VBE of the transistor Q1 when a ratio of the resistance values of the resistors R1 and R2 is adjusted.
That is, the voltage ΔV given by Equation 2 may be generated by the ΔV voltage generator 420a according to the first exemplary embodiment of the present invention, and a value of ΔV is determined by the resistance values of the resistors R1 and R2 and the base-emitter voltage VBE of the transistor Q1. When the base-emitter voltage VBE of the transistor Q1 is set to a predetermined value by the characteristics of the transistor Q1, the desired ΔV may be obtained by changing the values of the resistors R1 and R2. Particularly, it is necessary to set the ΔV to various values to improve the low discharge in
In addition, rather than using fixed resistors, variable resistors may be used for the resistors R1 and R2 as shown in
In addition, a resistor that varies according to temperature may be used for the resistors R1 and R2. That is, the resistors R1 and R2 may be set to have a Positive Temperature Coefficient (PTC) (i.e., a characteristic of increasing resistance as the temperature increases), or they may be set to have a Negative Temperature Coefficient (NTC) (i.e., a characteristic of decreasing resistance as the temperature increases). When the temperature is decreased, the wall charges in the discharge cell are not actively changed, and the low address discharge deteriorates. In this case, when the resistor R1 is set to have an NTC and the resistor R2 is set to have a PTC, the value of ΔV is further increased by Equation 2 when the temperature is decreased. Accordingly, the problem of the low address discharge at a low temperature may be solved. In other cases, the problem caused by the temperature may be solved by appropriately setting the resistors R1 and R2 to vary according to temperature.
It has been described that the transistor Q1 is a bipolar transistor according to the first exemplary embodiment of the present invention. However, the present invention is not limited thereto, and a Metal-Oxide Semiconductor Field Effect Transistor (hereinafter referred to as a “MOSFET”) or an Insulated Gate Bipolar Transistor (hereinafter referred to as an “IGBT”) may be used, as described below.
As shown in
Since the ΔV voltage generator 420b according to the second exemplary embodiment of the present invention uses the MOSFET transistor M1, the ΔV voltage, which is a drain-source voltage VDS of the transistor M1, is given by Equation 3.
VDS=(1+R1/R2)*VGS Equation 3
In Equation 3, VGS denotes a gate-source voltage of the transistor M1. As shown in Equation 3, when the transistor M1 is a MOSFET, the base-emitter voltage VBE of the transistor Q1 in Equation 2 is changed to a gate-source voltage VGS of the transistor M1.
As described above, in the ΔV voltage generator 420b according to the second exemplary embodiment of the present invention, the value of ΔV is determined by the gate-source voltage (VGS) of the transistor M1 and the values of the resistors R1 and R2, as shown in Equation 3.
In addition, in the ΔV voltage generator 420b according to the second exemplary embodiment of the present invention, the resistors R1 and R2 may be replaced by the variable resistors in a like manner to the first exemplary embodiment of the present invention, and they may be replace by resistors that vary according to temperature.
As shown in
Since the ΔV voltage generator 420c according to the third exemplary embodiment of the present invention uses an IGBT transistor Z1, the ΔV voltage, which is a collector-emitter voltage VCE of the transistor Z1, is given by Equation 4.
VCE=(1+R1/R2)*VGE Equation 4
In Equation 4, VGE denotes a gate-emitter voltage of the transistor Z1. As shown in Equation 4, when the transistor Z1 is an IGBT, the base-emitter voltage VBE of the transistor Q1 is replaced by a gate-emitter voltage VGE of the transistor Z1.
As described above, in the ΔV voltage generator 420c according to the third exemplary embodiment of the present invention, the value of ΔV is determined by the gate-emitter voltage VGE of the transistor Z1 and the values of the resistors R1 and R2.
In addition, in the ΔV voltage generator 420c according to the third exemplary embodiment of the present invention, the resistors R1 and R2 may be replaced by variable resistors in a like manner to the first exemplary embodiment of the present invention, and they may be replaced by resistors that vary according to temperature.
A ΔV voltage generator for generating a greater ΔV voltage is described as follows.
As shown in
The ΔV voltage generated by the ΔV voltage generator 420d according to the fourth exemplary embodiment of the present invention is obtained by substituting (VBE+Vz) for VBE in Equation 2. When a base current of the transistor Q1 is ignored, I1≈I2 and I2=(VBE+Vz)/R2. Accordingly, when I1≈I2 and I2=(VBE+Vz)/R2 are applied to Equation 1, the ΔV voltage generated by ΔV voltage generator 420d according to the fourth exemplary embodiment of the present invention is given by Equation 5.
ΔV=(1+R1/R2)*(Vz+VBE) Equation 5
Accordingly, the ΔV voltage generated by the ΔV voltage generator 420d according to the fourth exemplary embodiment of the present invention may be greater than the ΔV voltage according to the first exemplary embodiment of the present invention. In general, since VBE is a lower value, there is a limit in forming a high ΔV value even when a ratio of R1 and R2 is adjusted. However, according to the fourth exemplary embodiment of the present invention, the ΔV voltage value is determined by the VBE value and the Vz value. Accordingly, since the Zener diode Dz having a high Vz value is used, a greater ΔV value may be realized.
In addition, in the ΔV voltage generator 420d according to the fourth exemplary embodiment of the present invention, a constant ΔV value may be obtained when temperature changes.
As shown in
ΔV+δV=[1+{(R1+δR1)/(R2+δR2)}]*[(Vz+δVz)+(VBE−δVBE)] Equation 6
In Equation 6, ΔV, Vz, VBE, R1, and R2 are values at room temperature, and δVz, δVBE, δR1, and δR2 are variation values according to temperature. Since polarity of the pn diode formed between the base and the emitter of the transistor Q1 is opposite to that of the Zener diode Dz, it is shown as −δVBE.
Since the temperature of the resistors changes according to the ratio of R1 and R2, the temperature change of the resistors is relatively lower than that of the Zener diode Dz and the transistor Q1. Accordingly, when a first term in Equation 6 is considered, a temperature coefficient variation of the two diodes is given as (δVz−δVBE), and therefore they offset each other. Particularly, when using a transistor and a Zener diode having a characteristic of δVz=δVBE, the temperature change of the ΔV value may be minimized.
In addition, a MOSFET or an IGBT may be used for the bipolar transistor Q1 in the ΔV voltage generator according to the fourth exemplary embodiment of the present invention in a like manner to the second and third exemplary embodiments of the present invention.
The ΔV voltage generated by the ΔV voltage generator 420e according to the fifth exemplary embodiment of the present invention is obtained by substituting (VGS+Vz) for VGS in Equation 3. In addition, the ΔV voltage generated by the ΔV voltage generator 420f according to the sixth exemplary embodiment of the present invention is obtained by substituting (VGE+Vz) for VGE in Equation 4.
In a like manner of the fourth exemplary embodiment of the present invention, the high ΔV value may be obtained and the temperature change of the ΔV voltage value may be minimized according to the fifth and sixth exemplary embodiments of the present invention.
Rather than using resistors R1 and R2, a variable resistor may be used, and a resistor that varies according to temperature may be used in the fourth to sixth exemplary embodiments of the present invention.
While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
According to the exemplary embodiments of the present invention, the final voltage and the scan voltage of the reset period may be generated by using a single power source. In addition, since the resistors R1 and R2 are simply changed, the ΔV value may be variously realized. Furthermore, since the Zener diode is additionally provided, a further increased ΔV value may be realized, and the temperature change of the ΔV value may be minimized.
Claims
1. A plasma display comprising:
- a scan electrode to receive a scan voltage;
- a power source to supply the scan voltage;
- a first transistor having a first electrode electrically coupled to the scan electrode;
- a Zener diode having a cathode electrically coupled to a second electrode of the first transistor and having an anode electrically coupled to the power source;
- at least one first resistor electrically coupled between the scan electrode and a control electrode of the first transistor; and
- at least one second resistor electrically coupled between the control electrode of the first transistor and the second electrode of the first transistor.
2. The plasma display of claim 1, wherein a voltage at the first electrode of the first transistor is a first voltage higher than the scan voltage.
3. The plasma display of claim 2, wherein the first voltage is a final voltage finally supplied to the scan electrode during a reset period.
4. The plasma display of claim 1, further comprising a second transistor electrically coupled between the anode of the Zener diode and the power source.
5. The plasma display of claim 4, wherein the second transistor performs as a ramp switch to gradually decrease a voltage at the scan electrode to a first voltage higher than the scan voltage during a reset period upon the second transistor being turned on.
6. The plasma display of claim 5, further comprising a third transistor electrically coupled between the scan electrode and the power source, the scan voltage being supplied to the scan electrode upon the third transistor being turned on.
7. The plasma display of claim 1, wherein at least one of the first and second resistors is a variable resistor.
8. The plasma display of claim 1, wherein at least one of the first and second resistors is a resistor that varies according to temperature.
9. A voltage generator for generating a first voltage higher than a second voltage supplied by a power source, the voltage generator comprising:
- a Zener diode including an anode electrically coupled to the power source;
- a transistor including a first electrode electrically coupled to a cathode of the Zener diode;
- at least one first resistor electrically coupled between the anode of the Zener diode and a control electrode of the transistor; and
- at least one second resistor electrically coupled between the control electrode of the transistor and a second electrode of the transistor, the first voltage being generated at the second electrode of the transistor.
10. The voltage generator of claim 9, wherein at least one of the first and second resistors is a variable resistor.
11. The voltage generator of claim 9, wherein the first and second voltages drive a plasma display.
12. The voltage generator of claim 9, wherein the second voltage is a scan voltage supplied to a scan electrode of a plasma display, and the first voltage is a final voltage finally supplied during a reset period of the plasma display.
Type: Application
Filed: Sep 10, 2007
Publication Date: Mar 13, 2008
Inventors: Jeong-Hoon Kim (Suwon-si), Jung-Pil Park (Suwon-si), Suk-Ki Kim (Suwon-si), Jung-Soo An (Suwon-si)
Application Number: 11/898,218
International Classification: G09G 3/28 (20060101); G05F 3/08 (20060101);