Method And Apparatus For A Two-Wire Serial Command Bus Interface
A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.
This application is a divisional of U.S. application Ser. No. 11/713,241 filed Mar. 1, 2007, which is a divisional of U.S. application Ser. No. 10/171,820, filed Jun. 13, 2002, both of which are hereby incorporated by reference.
FIELD OF THE INVENTIONThe present invention relates generally to digital communication between a transmitter and a receiver, and more particularly to communication between a video source device and a video display device.
BACKGROUND OF THE INVENTIONThe DDC bus 60 is a serial 2-wire interface that has one data line and one clock line. This serial protocol is believed to have been developed, at least in part by the Philips Corporation of Holland. Philips part #PCA9515 is an integrated circuit which implements the so-called I2C bus. One of the primary purposes of the DDC bus 60, when used as an I2C bus, is to read an EDID PROM 70 (extended data interface device programmable read only memory) which includes data concerning the receiver 30. The DDC bus 60 can also be used for data transfer with HDCP 80 (high-bandwidth digital content protection), which is an encryption device that provides content protection.
Several problems are associated with the DDC bus 60 that make it undesirable for certain applications. One problem is that it can not be of an extended physical length due to electrical issues such as overwhelmed capacitive load budgets and transmission line effects that degrade signal timing parameters. Another problem is that its data carrying capacity is limited to about 400 kilobits/second. The data on the DDC bus 60 can be easily eavesdropped and even manipulated and since it may connect to several devices in the transmitter 20, security is also an issue. Finally, any attempt to solve these problems would need to take into consideration legacy issues for the purpose of backward compatibility. That is, the DDC bus is very widely used and any attempt to improve upon it would need to be compatible with transmitters and receivers that use the standard DDC bus interface.
Accordingly, what is needed is a method and apparatus for a DDC compatible two-wire serial command interface which allows for high speed data transmission, extended cable length, data security and still provide backward compatibility.
SUMMARY OF THE INVENTIONThe present invention provides a system and method for intelligently remapping a two-wire interface between a transmitter and a receiver. The remapping allows for high speed data transmission and data security and is not constrained by length issues. Additionally, a transmitter-side firewall prevents unauthorized access.
A method for bi-directional transmission of data between a source and a sink over a two-wire interface, in accordance with the present invention, includes remapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.
A system for bi-directional transmission of data between a source and sink over a two-wire interface, in accordance with the present invention, includes a first translator that is responsive to and operative to develop a first local bus signal and is responsive to and operative to develop a different protocol signal. A first buffer is responsive to and operative to develop the first local bus signal and is responsive to and operative to develop a buffered data signal and a buffered clock signal. Logic is responsive to the first local bus signal and operative to controlling a first switch coupled to the two-wire interface wherein the switch connects to the first translator, the first buffer or a firewall setting. A second translator is responsive to and operative to develop the different protocol signal and is responsive to and operative to develop a second local bus signal when the first switch is connected to the first translator and a second switch coupled to the two-wire interface is connected to the second translator. A second buffer is responsive to and operative to develop the buffered data signal and the buffered clock signal and is responsive to and operative to develop the second local bus signal when the first switch is connected to the first buffer and the second switch coupled to the two-wire interface is connected to the second buffer.
A method for buffering data between a source and a sink over a two-wire interface, in accordance with yet another aspect of the present invention, includes buffering on the source a data signal and a clock signal received from a local bus on the source. Transmitting, from the source to the sink, the data and clock signals over the two-wire interface. Buffering at the sink the data and clock signals. Retransmitting from the sink the data and clock signals over the two-wire interface to the source as needed; and logic on the source that performs a firewall function by selectively closing access to the two-wire interface.
A system for buffering data between a source and a sink over a two-wire interface, in accordance with the present invention, includes a first buffer responsive to a first local bus signal and responsive to and operative to develop a buffered data signal and a buffered clock signal. A logic is responsive to the first local bus signal and operative to controlling a first switch coupled to the two-wire interface wherein the switch connects to the first buffer or a firewall setting. A second buffer is responsive to and operative to develop the buffered data signal and the buffered clock signal and is responsive to and operative to develop a second local bus signal when the first switch is connected to the first buffer and a second switch coupled to the two-wire interface is connected to the second buffer.
A system for buffering data between a source and a sink over a two-wire interface, in accordance with the present invention, includes a first buffer that is responsive to a first local bus signal and operative to develop a buffered data signal and a buffered clock signal. A logic is responsive to the first local bus and operative to controlling a first switch coupled to the two-wire interface wherein the switch connects to the first buffer or a firewall setting. The sink is coupled to the two-wire interface and is responsive to the buffered data signal and the buffered clock signal when the switch is connected to the first buffer.
An advantage of the present invention is that it is fully compatible with legacy hardware. It intelligently detects whether a device can support new or old protocols and adjusts accordingly. Additionally, even in the absence of new protocol compatibility, it improves upon legacy systems by increasing available cable length and also by providing a transmitter-side firewall. Also, security is improved and new protocols can be designed to be more readily sent through a receiver to another device or another level, for example, though a repeater coupled to two receivers.
These and other advantages of the present invention will become apparent to those skilled in the art after reading the following descriptions and studying the various figures of the drawings.
If switches 120 and 130 are left in their default modes, improvements are still evident over prior art systems due to the presence of the buffers 100 and 110 and firewall setting 240. By buffering, the length of the DDC wires can be extended. On the transmitter 140, switch 120 can be placed at firewall setting 240 by logic 160. When firewall setting 240 is selected, access to the transmitter 140 via DDC wires 170 is cut off. Advantageously, this provides greater security on the transmitter 140 since access via the DDC wires 170 can be controlled and is no longer in a perpetually connected state. Additionally, in the context of the present invention, it should be understood that the terms “protocol” and “mode” can be used interchangeably and refer to a specified format of data communication or data transfer.
It should be understood that the receiver 150 could also send information to the transmitter 140. It will also be appreciated that, in some circumstances, the receiver 150 can initiate communications with the transmitter.
In an additional embodiment, both default and new modes (as shown in
The present invention provides a method and apparatus for a two-wire serial command bus interface. The re-mapping allows for high-speed data transmission, data security and is not constrained by length issues. Additionally, a transmitter side firewall prevents unauthorized access.
An advantage of the present invention is that it is fully compatible with legacy hardware. It intelligently detects whether a device can support new or old protocols and adjusts accordingly. Additionally, even in the absence of new protocol compatibility, it improves upon legacy systems by increasing available cable length and also by providing a transmitter-side firewall.
While this invention has been described in terms certain preferred embodiments, it will be appreciated by those skilled in the art that certain modifications, permutations and equivalents thereof are within the inventive scope of the present invention. It is therefore intended that the following appended claims include all such modifications, permutations and equivalents as fall within the true spirit and scope of the present invention.
Claims
1. A system for transmission of a signal between a source and sink over a single-wire interface comprising:
- a first translator responsive to and operative to develop a first local bus signal and responsive to and operative to develop a different protocol signal;
- a first buffer responsive to and operative to develop the first local bus signal and responsive to and operative to develop a buffered signal;
- a logic responsive to the first local bus signal and operative to control a first switch coupled to the single-wire interface wherein the switch connects to the first translator, to the first buffer, or to a isolation setting;
- a second translator responsive to and operative to develop the different protocol signal and responsive to and operative to develop a second local bus signal when the first switch is connected to the first translator and a second switch coupled to the single-wire interface is connected to the second translator; and
- a second buffer responsive to and operative to develop the buffered signal and responsive to and operative to develop the second local bus signal when the first switch is connected to the first buffer and the second switch coupled to the single-wire interface is connected to the second buffer.
2. A system as in claim 1, wherein the signal is one of a data signal and a clock signal.
3. A system for transmission of at least one information signal over a wire interface, the system comprising:
- a transmitter including: (a) a first translator responsive to and operative to develop a first local bus signal and responsive to and operative to develop a different protocol signal; (b) a first buffer responsive to and operative to develop the first local bus signal and responsive to and operative to develop a buffered information signal; and (c) a logic responsive to the first local bus signal and operative to control a first switch coupled to the wire interface wherein the first switch connects to the first translator, to the first buffer, or to an isolation setting; and
- a receiver including: (d) a second translator responsive to and operative to develop the different protocol signal and responsive to and operative to develop a second local bus signal when the first switch is connected to the first translator and a second switch coupled to the wire interface is connected to the second translator; (e) a second buffer responsive to and operative to develop the buffered data signal and the buffered clock signal and responsive to and operative to develop the second local bus signal when the first switch is connected to the first buffer and the second switch coupled to the wire interface is connected to the second buffer; and
- a control that controls connectivity of at least one of the first translator, first buffer, second translator, and second buffer during operation.
4. A system as in claim 3, wherein the at least one information signal is selected from the set of information signals consisting of: a serial data signal, a serial clock signal, and both a serial clock signal and a serial data signal.
5. A system as in claim 4, wherein when the selected information signal is both a serial clock signal and a serial data signal, then:
- (i) the transmitter first translator includes a first translator clock portion and a first translator data portion for translating the transmitter clock signal and transmitter data signal respectively;
- (ii) the transmitter first buffer includes a first buffer clock portion and a first buffer data portion for buffering the transmitter clock signal and the transmitter data signal respectively;
- (iii) the receiver second translator includes a second translator clock portion and a second translator data portion for translating the receiver clock signal and receiver data signal respectively; and
- (iv) the receiver second buffer includes a second buffer clock portion and a second buffer data portion for buffering the receiver clock signal and the receiver data signal respectively.
6. A system as in claim 3, wherein the system further includes a second switch within the receiver, and the control controls the state of the first and second switches in a default position where the wire interface is connected to at least one of the first and second buffers or to at least one of the first and second translators.
7. A system as in claim 3, wherein the information signal comprises a data signal and the buffered information signal comprises a buffered data signal.
8. A system as in claim 3, wherein the information signal comprises a clock signal and the buffered information signal comprises a buffered clock signal.
9. A system as in claim 3, wherein the information signal comprises a data signal and a clock signal and the buffered information signal comprises a buffered data signal and a buffered clock signal.
10. A system as in claim 3, wherein the wire interface comprises a single wire interface for communicating one or a serial clock information signal and a serial data information signal.
11. A system as in claim 3, wherein the wire interface is a single-wire interface for communicating one or a serial clock information signal and a serial data information signal.
12. A system as in claim 3, wherein the wire interface is a two-wire interface for communicating both a serial clock information signal and a serial data information signal.
13. A system for communicating at least one information signal over a wired interface, the system comprising:
- a transmitter; and
- a receiver;
- at least one of the transmitter and receiver including: (a) a first translator responsive operative to develop at least one of (i) a different protocol signal from a local bus signal, and (ii) a local bus signal from a different protocol signal; (b) a first buffer operative to develop at least one of (i) a buffered signal from a local bus signal, and (ii) a local bus signal from a buffered signal; and (c) a first switch for enabling or disabling a coupling between the wire interface and one of the first buffer and the first translator, the switch having a default state in which the coupling is enabled to couple the wire interface to the first buffer and an optional controlled state in which the coupling to the first buffer is disabled and enabled to the first translator.
14. A system as in claim 13, further comprising a logic unit responsive to the first local bus signal and operative to control the first switch to alter the switch state from the default state coupling the wire interface to the first buffer and the optional controlled state coupling the wire interface to the first translator.
15. A system as in claim 13, wherein the logic unit is coupled with the transmitter, the first switch is a switch in the transmitter, and the switch controls a coupling of the first translator or the first buffer within the transmitter to the wire interface.
16. A system as in claim 13, wherein only one of the transmitter and receiver includes the first translator, the first buffer, and the first switch.
17. A system as in claim 13, wherein only the transmitter includes the first translator, the first buffer, and the first switch.
18. A system as in claim 13, wherein only the receiver includes the first translator, the first buffer, and the first switch.
19. A system as in claim 13, wherein the first buffer includes a first buffer circuit.
20. A system as in claim 19, wherein the first buffer further includes a second buffer circuit.
21. A system as in claim 19, wherein the first buffer circuit is adapted for buffering a serial data signal.
22. A system as in claim 20, wherein the second buffer circuit is adapted for buffering a serial clock signal.
23. A system as in claim 13, wherein one of the transmitter and the receiver include the first buffer and the first translator and the first switch and the other of the transmitter and the receiver do not include the first buffer and the first translator and the first switch.
24. A system as in claim 13, wherein the buffered signal includes a buffered data signal and a buffered clock signal.
25. A system as in claim 13, wherein the local bus signal includes a local bus data signal and a local bus clock signal.
26. A system as in claim 13, wherein the local bus data signal comprises a serial data signal (SDA).
27. A system as in claim 13, wherein the local bus clock signal comprises a serial clock signal (SCL).
28. A system for buffering information between a transmitter and a receiver over a wire interface, the system comprising:
- a transmitter including: a first buffer responsive to a first local bus signal and operative to develop a buffered information signal; and a logic unit responsive to the first local bus signal and operative to control a first switch coupled to the wire interface, wherein the first switch connects to the first buffer or an isolation setting; and
- the receiver coupled to the wire interface and responsive to the buffered information signal when the switch is connected to the first buffer.
29. A system as in claim 28, wherein the safe setting comprises a firewall setting wherein access to the wire interface is selectively closed.
30. A system as in claim 28, wherein the first switch may alternately connect to a translator.
31. A system for buffering information between a transmitter and a receiver over a wire interface, the system comprising:
- a receiver including: a first buffer responsive to a first local bus signal and operative to develop a buffered information signal; and a logic unit responsive to the first local bus signal and operative to control a first switch coupled to the wire interface, wherein the first switch connects to the first buffer or an isolation setting; and
- the transmitter coupled to the wire interface and responsive to the buffered information signal when the switch is connected to the first buffer.
32. A system as in claim 31, wherein the safe setting comprises a firewall setting wherein access to the wire interface is selectively closed.
33. A system as in claim 31, wherein the first switch may alternately connect to a translator.
34. A method for communicating at least one information signal over a wired interface between a transmitter and a receiver, the method comprising:
- a transmitter; and
- a receiver;
- at least one of the transmitter and receiver including: (a) developing a first translation, within at least one of the transmitter and the receiver, including at least one of (i) a different protocol signal from a local bus signal, and (ii) a local bus signal from a different protocol signal; (b) generating at least one of (i) a buffered signal from a local bus signal, and (ii) a local bus signal from a buffered signal; and (c) switching to couple either the first translation or one of the at least one of (i) a buffered signal from the local bus signal, and (ii) the local bus signal from the buffered signal to the wired interface.
35. A method of transmitting two frequency signals over a two-wire interface comprising:
- mixing a first frequency signal on a first bus and a second frequency signal on a second bus by using a first switch to alternately connect the first bus and the second bus to the two-wire interface;
- transmitting the first frequency signal and the second frequency signal over the two-wire interface; and
- separating the first frequency signal from the second frequency signal by using a second switch to alternately connect a third bus for carrying the first frequency signal and a fourth bus for carrying the second frequency signal to the two-wire interface.
36. A system for transmitting two frequency signals over a two-wire interface comprising:
- a first switch for alternately connecting a first bus carrying a first frequency signal and a second bus carrying a second frequency signal to the two-wire interface;
- the two-wire interface for transmitting the first frequency signal and the second frequency signal; and
- a second switch for separating the first frequency signal from the second frequency signal by alternately connecting a third bus for carrying the first frequency signal and a fourth bus for carrying the second frequency signal to the two-wire interface.
37. A method of transmitting two voltage signals over a two-wire interface comprising:
- mixing a first voltage signal on a first bus and a second voltage signal on a second bus by using a first switch to alternately connect the first bus and the second bus to the two-wire interface;
- transmitting the first voltage signal and the second voltage signal over the two-wire interface; and
- separating the first voltage signal from the second voltage signal by using a second switch to alternately connect a third bus for carrying the first voltage signal and a fourth bus for carrying the second voltage signal to the two-wire interface.
38. A system for transmitting two voltage signals over a two-wire interface comprising:
- a first switch for alternately connecting a first bus carrying a first voltage signal and a second bus carrying a second voltage signal to the two-wire interface;
- the two-wire interface for transmitting the first voltage signal and the second voltage signal; and
- a second switch for separating the first voltage signal from the second voltage signal by alternately connecting a third bus for carrying the first voltage signal and a fourth bus for carrying the second voltage signal to the two-wire interface.
Type: Application
Filed: Feb 28, 2008
Publication Date: Jun 19, 2008
Inventor: Jim Lyle (Santa Clara, CA)
Application Number: 12/039,597
International Classification: H04L 12/43 (20060101);